5 files changed, 217 insertions, 0 deletions
diff --git a/mk/builtin/mod.mk b/mk/builtin/mod.mk
new file mode 100644
index 0000000..18d7b32
--- /dev/null
+++ b/mk/builtin/mod.mk
@@ -0,0 +1,5 @@
+cores := peakrdl_intfs
+
+define core/peakrdl_intfs
+  $(this)/rtl_dirs := peakrdl_intfs
+endef
diff --git a/mk/builtin/peakrdl_intfs/apb3_intf.sv b/mk/builtin/peakrdl_intfs/apb3_intf.sv
new file mode 100644
index 0000000..d18d3a0
--- /dev/null
+++ b/mk/builtin/peakrdl_intfs/apb3_intf.sv
@@ -0,0 +1,40 @@
+interface apb3_intf #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 32
+);
+    // Command
+    logic PSEL;
+    logic PENABLE;
+    logic PWRITE;
+    logic [ADDR_WIDTH-1:0] PADDR;
+    logic [DATA_WIDTH-1:0] PWDATA;
+
+    // Response
+    logic [DATA_WIDTH-1:0] PRDATA;
+    logic PREADY;
+    logic PSLVERR;
+
+    modport master (
+        output PSEL,
+        output PENABLE,
+        output PWRITE,
+        output PADDR,
+        output PWDATA,
+
+        input PRDATA,
+        input PREADY,
+        input PSLVERR
+    );
+
+    modport slave (
+        input PSEL,
+        input PENABLE,
+        input PWRITE,
+        input PADDR,
+        input PWDATA,
+
+        output PRDATA,
+        output PREADY,
+        output PSLVERR
+    );
+endinterface
diff --git a/mk/builtin/peakrdl_intfs/apb4_intf.sv b/mk/builtin/peakrdl_intfs/apb4_intf.sv
new file mode 100644
index 0000000..4a554f8
--- /dev/null
+++ b/mk/builtin/peakrdl_intfs/apb4_intf.sv
@@ -0,0 +1,46 @@
+interface apb4_intf #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 32
+);
+    // Command
+    logic PSEL;
+    logic PENABLE;
+    logic PWRITE;
+    logic [2:0] PPROT;
+    logic [ADDR_WIDTH-1:0] PADDR;
+    logic [DATA_WIDTH-1:0] PWDATA;
+    logic [DATA_WIDTH/8-1:0] PSTRB;
+
+    // Response
+    logic [DATA_WIDTH-1:0] PRDATA;
+    logic PREADY;
+    logic PSLVERR;
+
+    modport master (
+        output PSEL,
+        output PENABLE,
+        output PWRITE,
+        output PPROT,
+        output PADDR,
+        output PWDATA,
+        output PSTRB,
+
+        input PRDATA,
+        input PREADY,
+        input PSLVERR
+    );
+
+    modport slave (
+        input PSEL,
+        input PENABLE,
+        input PWRITE,
+        input PPROT,
+        input PADDR,
+        input PWDATA,
+        input PSTRB,
+
+        output PRDATA,
+        output PREADY,
+        output PSLVERR
+    );
+endinterface
diff --git a/mk/builtin/peakrdl_intfs/avalon_mm_intf.sv b/mk/builtin/peakrdl_intfs/avalon_mm_intf.sv
new file mode 100644
index 0000000..1d3d0c3
--- /dev/null
+++ b/mk/builtin/peakrdl_intfs/avalon_mm_intf.sv
@@ -0,0 +1,46 @@
+interface avalon_mm_intf #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 32 // Important! Avalon uses word addressing
+);
+    // Command
+    logic read;
+    logic write;
+    logic waitrequest;
+    logic [ADDR_WIDTH-1:0] address;
+    logic [DATA_WIDTH-1:0] writedata;
+    logic [DATA_WIDTH/8-1:0] byteenable;
+
+    // Response
+    logic readdatavalid;
+    logic writeresponsevalid;
+    logic [DATA_WIDTH-1:0] readdata;
+    logic [1:0] response;
+
+    modport host (
+        output read,
+        output write,
+        input waitrequest,
+        output address,
+        output writedata,
+        output byteenable,
+
+        input readdatavalid,
+        input writeresponsevalid,
+        input readdata,
+        input response
+    );
+
+    modport agent (
+        input read,
+        input write,
+        output waitrequest,
+        input address,
+        input writedata,
+        input byteenable,
+
+        output readdatavalid,
+        output writeresponsevalid,
+        output readdata,
+        output response
+    );
+endinterface
diff --git a/mk/builtin/peakrdl_intfs/axi4lite_intf.sv b/mk/builtin/peakrdl_intfs/axi4lite_intf.sv
new file mode 100644
index 0000000..b0a232d
--- /dev/null
+++ b/mk/builtin/peakrdl_intfs/axi4lite_intf.sv
@@ -0,0 +1,80 @@
+interface axi4lite_intf #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 32
+);
+    logic AWREADY;
+    logic AWVALID;
+    logic [ADDR_WIDTH-1:0] AWADDR;
+    logic [2:0] AWPROT;
+
+    logic WREADY;
+    logic WVALID;
+    logic [DATA_WIDTH-1:0] WDATA;
+    logic [DATA_WIDTH/8-1:0] WSTRB;
+
+    logic BREADY;
+    logic BVALID;
+    logic [1:0] BRESP;
+
+    logic ARREADY;
+    logic ARVALID;
+    logic [ADDR_WIDTH-1:0] ARADDR;
+    logic [2:0] ARPROT;
+
+    logic RREADY;
+    logic RVALID;
+    logic [DATA_WIDTH-1:0] RDATA;
+    logic [1:0] RRESP;
+
+    modport master (
+        input AWREADY,
+        output AWVALID,
+        output AWADDR,
+        output AWPROT,
+
+        input WREADY,
+        output WVALID,
+        output WDATA,
+        output WSTRB,
+
+        output BREADY,
+        input BVALID,
+        input BRESP,
+
+        input ARREADY,
+        output ARVALID,
+        output ARADDR,
+        output ARPROT,
+
+        output RREADY,
+        input RVALID,
+        input RDATA,
+        input RRESP
+    );
+
+    modport slave (
+        output AWREADY,
+        input AWVALID,
+        input AWADDR,
+        input AWPROT,
+
+        output WREADY,
+        input WVALID,
+        input WDATA,
+        input WSTRB,
+
+        input BREADY,
+        output BVALID,
+        output BRESP,
+
+        output ARREADY,
+        input ARVALID,
+        input ARADDR,
+        input ARPROT,
+
+        input RREADY,
+        output RVALID,
+        output RDATA,
+        output RRESP
+    );
+endinterface