diff options
| -rw-r--r-- | gfx_hw.tcl | 1 | ||||
| -rw-r--r-- | rtl/gfx/gfx_fixed_fma_dot.sv | 33 | ||||
| -rw-r--r-- | rtl/gfx/gfx_pipes.sv | 25 |
3 files changed, 43 insertions, 16 deletions
@@ -54,6 +54,7 @@ add_fileset_file gfx_pipeline_flow.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_pipeline_f add_fileset_file gfx_fold_flow.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_fold_flow.sv add_fileset_file gfx_skid_flow.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_skid_flow.sv add_fileset_file gfx_skid_buf.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_skid_buf.sv +add_fileset_file gfx_pipes.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_pipes.sv add_fileset_file gfx_dot.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_dot.sv add_fileset_file gfx_transpose.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_transpose.sv add_fileset_file gfx_scanout.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_scanout.sv diff --git a/rtl/gfx/gfx_fixed_fma_dot.sv b/rtl/gfx/gfx_fixed_fma_dot.sv index 2831d08..c19b49e 100644 --- a/rtl/gfx/gfx_fixed_fma_dot.sv +++ b/rtl/gfx/gfx_fixed_fma_dot.sv @@ -14,7 +14,7 @@ module gfx_fixed_fma_dot output fixed q ); - fixed q0, a1_hold[`FIXED_FMA_STAGES], b1_hold[`FIXED_FMA_STAGES]; + fixed q0, a1_hold, b1_hold; gfx_fixed_fma fma0 ( @@ -24,25 +24,26 @@ module gfx_fixed_fma_dot .* ); - gfx_fixed_fma fma1 + gfx_pipes #(.WIDTH($bits(fixed)), .DEPTH(`FIXED_FMA_STAGES)) a_pipes ( - .a(a1_hold[`FIXED_FMA_STAGES - 1]), - .b(b1_hold[`FIXED_FMA_STAGES - 1]), - .c(q0), + .in(a1), + .out(a1_hold), .* ); - integer i; - - always_ff @(posedge clk) - if (!stall) begin - a1_hold[0] <= a1; - b1_hold[0] <= b1; + gfx_pipes #(.WIDTH($bits(fixed)), .DEPTH(`FIXED_FMA_STAGES)) b_pipes + ( + .in(b1), + .out(b1_hold), + .* + ); - for (i = 1; i < `FIXED_FMA_STAGES; ++i) begin - a1_hold[i] <= a1_hold[i - 1]; - b1_hold[i] <= b1_hold[i - 1]; - end - end + gfx_fixed_fma fma1 + ( + .a(a1_hold), + .b(b1_hold), + .c(q0), + .* + ); endmodule diff --git a/rtl/gfx/gfx_pipes.sv b/rtl/gfx/gfx_pipes.sv new file mode 100644 index 0000000..55ebd19 --- /dev/null +++ b/rtl/gfx/gfx_pipes.sv @@ -0,0 +1,25 @@ +module gfx_pipes +#(parameter WIDTH=0, DEPTH=0) +( + input logic clk, + + input logic[WIDTH - 1:0] in, + input logic stall, + + output logic[WIDTH - 1:0] out +); + + logic[WIDTH - 1:0] pipes[DEPTH]; + + assign out = pipes[DEPTH - 1]; + + integer i; + always_ff @(posedge clk) + if (!stall) begin + pipes[0] <= in; + + for (i = 1; i < DEPTH; ++i) + pipes[i] <= pipes[i - 1]; + end + +endmodule |