diff options
| -rw-r--r-- | platform.qsys | 41 | ||||
| -rw-r--r-- | vga_controller_hw.tcl | 137 |
2 files changed, 177 insertions, 1 deletions
diff --git a/platform.qsys b/platform.qsys index 7d5bfe2..65f39d2 100644 --- a/platform.qsys +++ b/platform.qsys @@ -105,6 +105,14 @@ type = "int"; } } + element vga_controller_0 + { + datum _sortIndex + { + value = "9"; + type = "int"; + } + } element vram { datum _sortIndex @@ -153,6 +161,11 @@ type="clock" dir="start" /> <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" /> + <interface + name="vga_controller_0_dac" + internal="vga_controller_0.dac" + type="conduit" + dir="end" /> <interface name="vram_wire" internal="vram.wire" type="conduit" dir="end" /> <module name="address_span_extender_0" @@ -727,7 +740,9 @@ name="master_0" kind="conspiracion_bus_master" version="1.0" - enabled="1" /> + enabled="1"> + <parameter name="AUTO_IRQ_INTERRUPTS_USED" value="0" /> + </module> <module name="pio_0" kind="altera_avalon_pio" version="20.1" enabled="1"> <parameter name="bitClearingEdgeCapReg" value="false" /> <parameter name="bitModifyingOutReg" value="true" /> @@ -958,6 +973,11 @@ <parameter name="watchdogPulse" value="2" /> </module> <module + name="vga_controller_0" + kind="vga_controller" + version="1.0" + enabled="1" /> + <module name="vram" kind="altera_avalon_new_sdram_controller" version="20.1" @@ -1025,6 +1045,15 @@ <connection kind="avalon" version="20.1" + start="vga_controller_0.avalon_master" + end="vram.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection + kind="avalon" + version="20.1" start="master_0.avalon_master" end="address_span_extender_0.windowed_slave"> <parameter name="arbitrationPriority" value="1" /> @@ -1065,6 +1094,11 @@ end="master_0.clock" /> <connection kind="clock" version="20.1" start="pll_0.outclk2" end="vram.clk" /> <connection + kind="clock" + version="20.1" + start="pll_0.outclk2" + end="vga_controller_0.clock_sink" /> + <connection kind="reset" version="20.1" start="clk_0.clk_reset" @@ -1087,6 +1121,11 @@ version="20.1" start="clk_0.clk_reset" end="master_0.reset_sink" /> + <connection + kind="reset" + version="20.1" + start="clk_0.clk_reset" + end="vga_controller_0.reset_sink" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" /> <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> diff --git a/vga_controller_hw.tcl b/vga_controller_hw.tcl new file mode 100644 index 0000000..2816d9c --- /dev/null +++ b/vga_controller_hw.tcl @@ -0,0 +1,137 @@ +# TCL File Generated by Component Editor 20.1 +# Thu Nov 03 11:42:18 CST 2022 +# DO NOT MODIFY + + +# +# vga_controller "vga_controller" v1.0 +# Alejandro Soto 2022.11.03.11:42:18 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module vga_controller +# +set_module_property DESCRIPTION "" +set_module_property NAME vga_controller +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "Alejandro Soto" +set_module_property DISPLAY_NAME vga_controller +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL vga +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file vga.sv SYSTEM_VERILOG PATH rtl/vga.sv TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock_sink +# +add_interface clock_sink clock end +set_interface_property clock_sink clockRate 0 +set_interface_property clock_sink ENABLED true +set_interface_property clock_sink EXPORT_OF "" +set_interface_property clock_sink PORT_NAME_MAP "" +set_interface_property clock_sink CMSIS_SVD_VARIABLES "" +set_interface_property clock_sink SVD_ADDRESS_GROUP "" + +add_interface_port clock_sink clk clk Input 1 + + +# +# connection point reset_sink +# +add_interface reset_sink reset end +set_interface_property reset_sink associatedClock clock_sink +set_interface_property reset_sink synchronousEdges DEASSERT +set_interface_property reset_sink ENABLED true +set_interface_property reset_sink EXPORT_OF "" +set_interface_property reset_sink PORT_NAME_MAP "" +set_interface_property reset_sink CMSIS_SVD_VARIABLES "" +set_interface_property reset_sink SVD_ADDRESS_GROUP "" + +add_interface_port reset_sink rst_n reset_n Input 1 + + +# +# connection point avalon_master +# +add_interface avalon_master avalon start +set_interface_property avalon_master addressUnits SYMBOLS +set_interface_property avalon_master associatedClock clock_sink +set_interface_property avalon_master associatedReset reset_sink +set_interface_property avalon_master bitsPerSymbol 8 +set_interface_property avalon_master burstOnBurstBoundariesOnly false +set_interface_property avalon_master burstcountUnits WORDS +set_interface_property avalon_master doStreamReads false +set_interface_property avalon_master doStreamWrites false +set_interface_property avalon_master holdTime 0 +set_interface_property avalon_master linewrapBursts false +set_interface_property avalon_master maximumPendingReadTransactions 0 +set_interface_property avalon_master maximumPendingWriteTransactions 0 +set_interface_property avalon_master readLatency 0 +set_interface_property avalon_master readWaitTime 1 +set_interface_property avalon_master setupTime 0 +set_interface_property avalon_master timingUnits Cycles +set_interface_property avalon_master writeWaitTime 0 +set_interface_property avalon_master ENABLED true +set_interface_property avalon_master EXPORT_OF "" +set_interface_property avalon_master PORT_NAME_MAP "" +set_interface_property avalon_master CMSIS_SVD_VARIABLES "" +set_interface_property avalon_master SVD_ADDRESS_GROUP "" + +add_interface_port avalon_master avl_address address Output 26 +add_interface_port avalon_master avl_read read Output 1 +add_interface_port avalon_master avl_readdata readdata Input 32 +add_interface_port avalon_master avl_waitrequest waitrequest Input 1 + + +# +# connection point dac +# +add_interface dac conduit end +set_interface_property dac associatedClock clock_sink +set_interface_property dac associatedReset "" +set_interface_property dac ENABLED true +set_interface_property dac EXPORT_OF "" +set_interface_property dac PORT_NAME_MAP "" +set_interface_property dac CMSIS_SVD_VARIABLES "" +set_interface_property dac SVD_ADDRESS_GROUP "" + +add_interface_port dac vga_clk clk Output 1 +add_interface_port dac vga_hsync hsync Output 1 +add_interface_port dac vga_vsync vsync Output 1 +add_interface_port dac vga_blank_n blank_n Output 1 +add_interface_port dac vga_sync_n sync_n Output 1 +add_interface_port dac vga_r r Output 8 +add_interface_port dac vga_g g Output 8 +add_interface_port dac vga_b b Output 8 + |