diff options
| -rw-r--r-- | conspiracion.qsf | 1 | ||||
| -rw-r--r-- | rtl/core/control/control.sv | 19 | ||||
| -rw-r--r-- | rtl/core/control/exception.sv | 28 |
3 files changed, 38 insertions, 10 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf index 9ed8bb7..a75f0df 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -140,6 +140,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/branch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/control.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/cycles.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/data.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/exception.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/issue.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/ldst/pop.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/stall.sv diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index ec8f773..cc8f160 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -54,20 +54,14 @@ module core_control coproc ); - logic ldst, ldst_pre, ldst_increment, - ldst_writeback, pop_valid, exception, high_vectors; - - logic[2:0] vector_offset; - word mem_offset, vector; + logic ldst, ldst_pre, ldst_increment, ldst_writeback, pop_valid; + word mem_offset; reg_num r_shift, popped_upper, popped_lower, popped; reg_list mem_regs, next_regs_upper, next_regs_lower; assign reg_mode = `MODE_SVC; //TODO assign mem_data_wr = rd_value_b; assign popped = ldst_increment ? popped_lower : popped_upper; - assign exception = undefined; //TODO - assign high_vectors = 0; //TODO - assign vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00}; ctrl_cycle cycle, next_cycle; @@ -122,8 +116,13 @@ module core_control .* ); - always_comb - vector_offset = 3'b001; //TODO + word vector; + logic exception; + + core_control_exception ctrl_exc + ( + .* + ); always_ff @(posedge clk) begin wb_alu_flags <= alu_flags; diff --git a/rtl/core/control/exception.sv b/rtl/core/control/exception.sv new file mode 100644 index 0000000..9a64cd5 --- /dev/null +++ b/rtl/core/control/exception.sv @@ -0,0 +1,28 @@ +`include "core/uarch.sv" + +module core_control_exception +( + input logic clk, + + input logic undefined, + + output word vector, + output logic exception +); + + logic high_vectors; + logic[2:0] vector_offset; + + assign exception = undefined; //TODO + assign high_vectors = 0; //TODO + assign vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00}; + + always_comb + vector_offset = 3'b001; //TODO + + //TODO: spsr_<mode> = cpsr + //TODO: actualizar modo + //TODO: deshabilitar IRQs/FIQs dependiendo de modo + //TODO: Considerar que data abort usa + 8, no + 4 + +endmodule |