diff options
| -rw-r--r-- | cache_hw.tcl | 8 | ||||
| -rw-r--r-- | demo/cache.c | 10 | ||||
| -rw-r--r-- | rtl/cache/defs.sv | 10 | ||||
| -rw-r--r-- | tb/top/conspiracion.cpp | 4 |
4 files changed, 16 insertions, 16 deletions
diff --git a/cache_hw.tcl b/cache_hw.tcl index cedffb4..93c8748 100644 --- a/cache_hw.tcl +++ b/cache_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 20.1 -# Wed Oct 04 09:06:39 GMT 2023 +# Wed Oct 04 21:42:03 GMT 2023 # DO NOT MODIFY # -# cache "8KiB 1-way cache w/ controller" v1.0 -# 2023.10.04.09:06:39 +# cache "64KiB 1-way cache w/ controller" v1.0 +# 2023.10.04.21:42:03 # # @@ -24,7 +24,7 @@ set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property AUTHOR "" -set_module_property DISPLAY_NAME "8KiB 1-way cache w/ controller" +set_module_property DISPLAY_NAME "64KiB 1-way cache w/ controller" set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property REPORT_TO_TALKBACK false diff --git a/demo/cache.c b/demo/cache.c index d2a22cd..c9e56f0 100644 --- a/demo/cache.c +++ b/demo/cache.c @@ -7,12 +7,12 @@ #define CACHE_STATUS_CACHED (1 << 1) #define CACHE_STATUS_STATE_MASK 0x0000000c #define CACHE_STATUS_STATE_SHIFT 2 -#define CACHE_STATUS_INDEX_MASK 0x00001ff0 +#define CACHE_STATUS_INDEX_MASK 0x0000fff0 #define CACHE_STATUS_INDEX_SHIFT 4 -#define CACHE_STATUS_INDEX_BITS 9 -#define CACHE_STATUS_TAG_MASK 0x1fffe000 -#define CACHE_STATUS_TAG_SHIFT 13 -#define CACHE_STATUS_TAG_BITS 16 +#define CACHE_STATUS_INDEX_BITS 12 +#define CACHE_STATUS_TAG_MASK 0x1fff0000 +#define CACHE_STATUS_TAG_SHIFT 16 +#define CACHE_STATUS_TAG_BITS 13 #define CACHE_STATUS_STATE_I 0b00 #define CACHE_STATUS_STATE_S 0b01 #define CACHE_STATUS_STATE_E 0b10 diff --git a/rtl/cache/defs.sv b/rtl/cache/defs.sv index 0546c4d..d7c43dc 100644 --- a/rtl/cache/defs.sv +++ b/rtl/cache/defs.sv @@ -13,18 +13,18 @@ typedef logic[31:0] word; `endif /* Tenemos 512MiB de SDRAM, el resto del espacio es I/O (uncached). Usamos - * 512 líneas direct-mapped de 16 bytes cada una. El core solo realiza + * 4096 líneas direct-mapped de 16 bytes cada una. El core solo realiza * operaciones alineadas. Por tanto, cada dirección de 32 bits consta de: * - 2 bits que siempre son 0 (traducidos a byteenable por core) * - 2 bits de offset (ya que para cache la unidad direccionable es la word) - * - 9 bits de index - * - 16 bits de tag + * - 12 bits de index + * - 13 bits de tag * - 3 bits que son == 0 si cached, != 0 si uncached */ typedef logic[1:0] addr_mbz; typedef logic[1:0] addr_offset; -typedef logic[8:0] addr_index; -typedef logic[15:0] addr_tag; +typedef logic[11:0] addr_index; +typedef logic[12:0] addr_tag; typedef logic[2:0] addr_io_region; typedef logic[26:0] addr_cacheable; diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp index f074583..00a672e 100644 --- a/tb/top/conspiracion.cpp +++ b/tb/top/conspiracion.cpp @@ -514,8 +514,8 @@ int main(int argc, char **argv) if (!ok || (ok >> 29)) return ok; - unsigned tag = (addr >> 11) & ((1 << 16) - 1); - unsigned index = (addr >> 2) & ((1 << 9) - 1); + unsigned tag = (addr >> 14) & ((1 << 13) - 1); + unsigned index = (addr >> 2) & ((1 << 12) - 1); for (std::size_t i = 0; i < sizeof caches / sizeof caches[0]; ++i) { const auto *cache = caches[i]; |