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-rw-r--r--rtl/core/control/control.sv5
1 files changed, 3 insertions, 2 deletions
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 95d3bb9..c2484ef 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -238,9 +238,10 @@ module core_control
mem_offset <= alu_b;
end
+ writeback <= mem_ready && !mem_write;
if(mem_ready) begin
+ rd <= final_rd;
wr_value <= mem_data_rd;
- writeback <= !mem_write;
end
if(cycle != TRANSFER || mem_ready) begin
@@ -249,8 +250,8 @@ module core_control
saved_base <= q_alu;
if(pop_valid) begin
- rd <= popped;
rb <= popped;
+ final_rd <= popped;
end else
rb <= final_rd; // Viene de dec_ldst.rd
end