diff options
| -rw-r--r-- | gfx_hw.tcl | 4 | ||||
| -rw-r--r-- | rtl/gfx/gfx_raster.sv | 4 | ||||
| -rw-r--r-- | rtl/gfx/gfx_raster_coarse.sv (renamed from rtl/gfx/gfx_coarse.sv) | 2 | ||||
| -rw-r--r-- | rtl/gfx/gfx_raster_fine.sv (renamed from rtl/gfx/gfx_fine.sv) | 2 |
4 files changed, 6 insertions, 6 deletions
@@ -65,8 +65,8 @@ add_fileset_file gfx_setup_edge.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_setup_edge.sv add_fileset_file gfx_setup_bounds.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_setup_bounds.sv add_fileset_file gfx_setup_offsets.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_setup_offsets.sv add_fileset_file gfx_raster.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_raster.sv -add_fileset_file gfx_fine.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_fine.sv -add_fileset_file gfx_coarse.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_coarse.sv +add_fileset_file gfx_raster_fine.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_raster_fine.sv +add_fileset_file gfx_raster_coarse.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_raster_coarse.sv # diff --git a/rtl/gfx/gfx_raster.sv b/rtl/gfx/gfx_raster.sv index e30ad43..c61cbb5 100644 --- a/rtl/gfx/gfx_raster.sv +++ b/rtl/gfx/gfx_raster.sv @@ -41,7 +41,7 @@ module gfx_raster fixed_tri coarse_corners; raster_xy coarse_pos; - gfx_coarse coarse + gfx_raster_coarse coarse ( .in_valid(setup_valid), .in_ready(coarse_ready), @@ -83,7 +83,7 @@ module gfx_raster generate for (i = 0; i < `GFX_RASTER_SIZE; ++i) begin: fine_x for (j = 0; j < `GFX_RASTER_SIZE; ++j) begin: fine_y - gfx_fine #(.X(i), .Y(j)) fine + gfx_raster_fine #(.X(i), .Y(j)) fine ( .stall(fine_stall), diff --git a/rtl/gfx/gfx_coarse.sv b/rtl/gfx/gfx_raster_coarse.sv index 840c647..7a047ee 100644 --- a/rtl/gfx/gfx_coarse.sv +++ b/rtl/gfx/gfx_raster_coarse.sv @@ -1,6 +1,6 @@ `include "gfx/gfx_defs.sv" -module gfx_coarse +module gfx_raster_coarse ( input logic clk, rst_n, diff --git a/rtl/gfx/gfx_fine.sv b/rtl/gfx/gfx_raster_fine.sv index 6238025..2cb9c6a 100644 --- a/rtl/gfx/gfx_fine.sv +++ b/rtl/gfx/gfx_raster_fine.sv @@ -1,6 +1,6 @@ `include "gfx/gfx_defs.sv" -module gfx_fine +module gfx_raster_fine #(parameter X=0, Y=0) ( input logic clk, |