diff options
| -rw-r--r-- | platform/wavelet3d/mod.mk | 2 | ||||
| -rw-r--r-- | platform/wavelet3d/w3d_interconnect.sv | 123 | ||||
| -rw-r--r-- | platform/wavelet3d/w3d_top.sv | 32 | ||||
| -rw-r--r-- | target/w3d_de1soc/w3d_de1soc.sv | 22 |
4 files changed, 136 insertions, 43 deletions
diff --git a/platform/wavelet3d/mod.mk b/platform/wavelet3d/mod.mk index b78f01a..7fc8b03 100644 --- a/platform/wavelet3d/mod.mk +++ b/platform/wavelet3d/mod.mk @@ -1,7 +1,7 @@ subdirs := host_sw define core - $(this)/deps := axixbar if_common gfx w3d_host_sw + $(this)/deps := axixbar if_common gfx vdc w3d_host_sw $(this)/rtl_top := w3d_top $(this)/rtl_dirs := . diff --git a/platform/wavelet3d/w3d_interconnect.sv b/platform/wavelet3d/w3d_interconnect.sv index 6f5fa66..c874c4b 100644 --- a/platform/wavelet3d/w3d_interconnect.sv +++ b/platform/wavelet3d/w3d_interconnect.sv @@ -7,10 +7,12 @@ module w3d_interconnect host_dbus, host_ibus, sgdma_mem, + vdc_stream, if_axib.m dram, if_axil.m gfx_ctrl, + vdc_ctrl, sgdma_ctrl, external_io ); @@ -26,7 +28,8 @@ module w3d_interconnect .gfx_vram, .host_dbus(dram_host.s), .host_ibus, - .sgdma_mem + .sgdma_mem, + .vdc_stream ); w3d_interconnect_host_data data @@ -44,6 +47,7 @@ module w3d_interconnect .srst_n, .host(mmio_axi.s), .gfx_ctrl, + .vdc_ctrl, .sgdma_ctrl, .external_io ); @@ -59,6 +63,7 @@ module w3d_interconnect_dram host_dbus, host_ibus, sgdma_mem, + vdc_stream, if_axib.m dram ); @@ -69,59 +74,68 @@ module w3d_interconnect_dram endfunction defparam - xbar.NM = 4, + xbar.NM = 5, xbar.NS = 1, xbar.OPT_LOWPOWER = 0, xbar.SLAVE_ADDR = '0, xbar.SLAVE_MASK = '0, xbar.C_AXI_ID_WIDTH = 8; + //FIXME: Lower-numbered masters (last in {..., ...}) always win + axixbar xbar ( .S_AXI_ACLK(clk), .S_AXI_ARESETN(srst_n), .S_AXI_AWVALID({ + sgdma_mem.awvalid, gfx_vram.awvalid, host_dbus.awvalid, host_ibus.awvalid, - sgdma_mem.awvalid + vdc_stream.awvalid }), .S_AXI_AWREADY({ + sgdma_mem.awready, gfx_vram.awready, host_dbus.awready, host_ibus.awready, - sgdma_mem.awready + vdc_stream.awready }), .S_AXI_AWID({ + sgdma_mem.awid, gfx_vram.awid, host_dbus.awid, host_ibus.awid, - sgdma_mem.awid + vdc_stream.awid }), .S_AXI_AWADDR({ + sgdma_mem.awaddr, vram_addr(gfx_vram.awaddr), host_dbus.awaddr, host_ibus.awaddr, - sgdma_mem.awaddr + vram_addr(vdc_stream.awaddr) }), .S_AXI_AWLEN({ + sgdma_mem.awlen, gfx_vram.awlen, host_dbus.awlen, host_ibus.awlen, - sgdma_mem.awlen + vdc_stream.awlen }), .S_AXI_AWSIZE({ + sgdma_mem.awsize, gfx_vram.awsize, host_dbus.awsize, host_ibus.awsize, - sgdma_mem.awsize + vdc_stream.awsize }), .S_AXI_AWBURST({ + sgdma_mem.awburst, gfx_vram.awburst, host_dbus.awburst, host_ibus.awburst, - sgdma_mem.awburst + vdc_stream.awburst }), .S_AXI_AWLOCK('0), .S_AXI_AWCACHE('0), @@ -129,102 +143,118 @@ module w3d_interconnect_dram .S_AXI_AWQOS('0), .S_AXI_WVALID({ + sgdma_mem.wvalid, gfx_vram.wvalid, host_dbus.wvalid, host_ibus.wvalid, - sgdma_mem.wvalid + vdc_stream.wvalid }), .S_AXI_WREADY({ + sgdma_mem.wready, gfx_vram.wready, host_dbus.wready, host_ibus.wready, - sgdma_mem.wready + vdc_stream.wready }), .S_AXI_WDATA({ + sgdma_mem.wdata, gfx_vram.wdata, host_dbus.wdata, host_ibus.wdata, - sgdma_mem.wdata + vdc_stream.wdata }), .S_AXI_WSTRB({ + sgdma_mem.wstrb, gfx_vram.wstrb, host_dbus.wstrb, host_ibus.wstrb, - sgdma_mem.wstrb + vdc_stream.wstrb }), .S_AXI_WLAST({ + sgdma_mem.wlast, gfx_vram.wlast, host_dbus.wlast, host_ibus.wlast, - sgdma_mem.wlast + vdc_stream.wlast }), .S_AXI_BVALID({ + sgdma_mem.bvalid, gfx_vram.bvalid, host_dbus.bvalid, host_ibus.bvalid, - sgdma_mem.bvalid + vdc_stream.bvalid }), .S_AXI_BREADY({ + sgdma_mem.bready, gfx_vram.bready, host_dbus.bready, host_ibus.bready, - sgdma_mem.bready + vdc_stream.bready }), .S_AXI_BID({ + sgdma_mem.bid, gfx_vram.bid, host_dbus.bid, host_ibus.bid, - sgdma_mem.bid + vdc_stream.bid }), .S_AXI_BRESP({ + sgdma_mem.bresp, gfx_vram.bresp, host_dbus.bresp, host_ibus.bresp, - sgdma_mem.bresp + vdc_stream.bresp }), .S_AXI_ARVALID({ + sgdma_mem.arvalid, gfx_vram.arvalid, host_dbus.arvalid, host_ibus.arvalid, - sgdma_mem.arvalid + vdc_stream.arvalid }), .S_AXI_ARREADY({ + sgdma_mem.arready, gfx_vram.arready, host_dbus.arready, host_ibus.arready, - sgdma_mem.arready + vdc_stream.arready }), .S_AXI_ARID({ + sgdma_mem.arid, gfx_vram.arid, host_dbus.arid, host_ibus.arid, - sgdma_mem.arid + vdc_stream.arid }), .S_AXI_ARADDR({ + sgdma_mem.araddr, vram_addr(gfx_vram.araddr), host_dbus.araddr, host_ibus.araddr, - sgdma_mem.araddr + vram_addr(vdc_stream.araddr) }), .S_AXI_ARLEN({ + sgdma_mem.arlen, gfx_vram.arlen, host_dbus.arlen, host_ibus.arlen, - sgdma_mem.arlen + vdc_stream.arlen }), .S_AXI_ARSIZE({ + sgdma_mem.arsize, gfx_vram.arsize, host_dbus.arsize, host_ibus.arsize, - sgdma_mem.arsize + vdc_stream.arsize }), .S_AXI_ARBURST({ + sgdma_mem.arburst, gfx_vram.arburst, host_dbus.arburst, host_ibus.arburst, - sgdma_mem.arburst + vdc_stream.arburst }), .S_AXI_ARLOCK('0), .S_AXI_ARCACHE('0), @@ -232,40 +262,46 @@ module w3d_interconnect_dram .S_AXI_ARQOS('0), .S_AXI_RVALID({ + sgdma_mem.rvalid, gfx_vram.rvalid, host_dbus.rvalid, host_ibus.rvalid, - sgdma_mem.rvalid + vdc_stream.rvalid }), .S_AXI_RREADY({ + sgdma_mem.rready, gfx_vram.rready, host_dbus.rready, host_ibus.rready, - sgdma_mem.rready + vdc_stream.rready }), .S_AXI_RID({ + sgdma_mem.rid, gfx_vram.rid, host_dbus.rid, host_ibus.rid, - sgdma_mem.rid + vdc_stream.rid }), .S_AXI_RDATA({ + sgdma_mem.rdata, gfx_vram.rdata, host_dbus.rdata, host_ibus.rdata, - sgdma_mem.rdata + vdc_stream.rdata }), .S_AXI_RRESP({ + sgdma_mem.rresp, gfx_vram.rresp, host_dbus.rresp, host_ibus.rresp, - sgdma_mem.rresp + vdc_stream.rresp }), .S_AXI_RLAST({ + sgdma_mem.rlast, gfx_vram.rlast, host_dbus.rlast, host_ibus.rlast, - sgdma_mem.rlast + vdc_stream.rlast }), .M_AXI_AWVALID(dram.awvalid), @@ -606,31 +642,36 @@ module w3d_interconnect_host_mmio if_axil.s host, if_axil.m gfx_ctrl, + vdc_ctrl, sgdma_ctrl, external_io ); localparam logic[31:0] GFX_CTRL_BASE = 32'h2000_0000, - GFX_CTRL_MASK = 32'hf800_0000, + GFX_CTRL_MASK = 32'hfc00_0000, + VDC_CTRL_BASE = 32'h2400_0000, + VDC_CTRL_MASK = 32'hfc00_0000, SGDMA_CTRL_BASE = 32'h2800_0000, - SGDMA_CTRL_MASK = 32'hf800_0000, + SGDMA_CTRL_MASK = 32'hfc00_0000, EXTERNAL_IO_BASE = 32'h3000_0000, EXTERNAL_IO_MASK = 32'hf000_0000; defparam xbar.NM = 1; - defparam xbar.NS = 3; + defparam xbar.NS = 4; defparam xbar.OPT_LOWPOWER = 0; defparam xbar.SLAVE_ADDR = { EXTERNAL_IO_BASE, SGDMA_CTRL_BASE, + VDC_CTRL_BASE, GFX_CTRL_BASE }; defparam xbar.SLAVE_MASK = { EXTERNAL_IO_MASK, SGDMA_CTRL_MASK, + VDC_CTRL_MASK, GFX_CTRL_MASK }; @@ -666,34 +707,40 @@ module w3d_interconnect_host_mmio .M_AXI_AWADDR({ external_io.awaddr, sgdma_ctrl.awaddr, + vdc_ctrl.awaddr, gfx_ctrl.awaddr }), .M_AXI_AWPROT(), .M_AXI_AWVALID({ external_io.awvalid, sgdma_ctrl.awvalid, + vdc_ctrl.awvalid, gfx_ctrl.awvalid }), .M_AXI_AWREADY({ external_io.awready, sgdma_ctrl.awready, + vdc_ctrl.awready, gfx_ctrl.awready }), .M_AXI_WDATA({ external_io.wdata, sgdma_ctrl.wdata, + vdc_ctrl.wdata, gfx_ctrl.wdata }), .M_AXI_WSTRB(), .M_AXI_WVALID({ external_io.wvalid, sgdma_ctrl.wvalid, + vdc_ctrl.wvalid, gfx_ctrl.wvalid }), .M_AXI_WREADY({ external_io.wready, sgdma_ctrl.wready, + vdc_ctrl.wready, gfx_ctrl.wready }), @@ -701,45 +748,53 @@ module w3d_interconnect_host_mmio .M_AXI_BVALID({ external_io.bvalid, sgdma_ctrl.bvalid, + vdc_ctrl.bvalid, gfx_ctrl.bvalid }), .M_AXI_BREADY({ external_io.bready, sgdma_ctrl.bready, + vdc_ctrl.bready, gfx_ctrl.bready }), .M_AXI_ARADDR({ external_io.araddr, sgdma_ctrl.araddr, + vdc_ctrl.araddr, gfx_ctrl.araddr }), .M_AXI_ARPROT(), .M_AXI_ARVALID({ external_io.arvalid, sgdma_ctrl.arvalid, + vdc_ctrl.arvalid, gfx_ctrl.arvalid }), .M_AXI_ARREADY({ external_io.arready, sgdma_ctrl.arready, + vdc_ctrl.arready, gfx_ctrl.arready }), .M_AXI_RDATA({ external_io.rdata, sgdma_ctrl.rdata, + vdc_ctrl.rdata, gfx_ctrl.rdata }), .M_AXI_RRESP('0), .M_AXI_RVALID({ external_io.rvalid, sgdma_ctrl.rvalid, + vdc_ctrl.rvalid, gfx_ctrl.rvalid }), .M_AXI_RREADY({ external_io.rready, sgdma_ctrl.rready, + vdc_ctrl.rready, gfx_ctrl.rready }) ); diff --git a/platform/wavelet3d/w3d_top.sv b/platform/wavelet3d/w3d_top.sv index e196b8f..24a81f7 100644 --- a/platform/wavelet3d/w3d_top.sv +++ b/platform/wavelet3d/w3d_top.sv @@ -57,6 +57,14 @@ module w3d_top output logic mmio_rready, input logic[31:0] mmio_rdata, + input logic dac_ready, + output logic dac_last, + dac_first, + dac_valid, + output logic[9:0] dac_b, + dac_g, + dac_r, + input logic jtag_tck, jtag_tms, jtag_tdi, @@ -64,8 +72,9 @@ module w3d_top ); if_tap host_jtag(); - if_axib dram(), gfx_vram(), host_dbus(), host_ibus(), sgdma_mem(); - if_axil mmio(), gfx_ctrl(), sgdma_ctrl(); + if_axib dram(), gfx_vram(), host_dbus(), host_ibus(), sgdma_mem(), vdc_stream(); + if_axil mmio(), gfx_ctrl(), sgdma_ctrl(), vdc_ctrl(); + vdc_dac dac(); assign dram_awid = dram.s.awid; assign dram_awlen = dram.s.awlen; @@ -125,6 +134,14 @@ module w3d_top assign host_jtag.m.tms = jtag_tms; assign host_jtag.m.tdi = jtag_tdi; + assign dac_b = dac.rx.pix.b; + assign dac_g = dac.rx.pix.g; + assign dac_r = dac.rx.pix.r; + assign dac_last = dac.rx.last; + assign dac_first = dac.rx.first; + assign dac_valid = dac.rx.valid; + assign dac.rx.ready = dac_ready; + if_rst_sync rst_sync ( .clk, @@ -141,6 +158,15 @@ module w3d_top .host_ctrl(gfx_ctrl.s) ); + vdc_top vdc + ( + .clk, + .rst_n, + .dac(dac.tx), + .host(vdc_ctrl.s), + .stream(vdc_stream.m) + ); + w3d_host host ( .clk, @@ -165,11 +191,13 @@ module w3d_top .srst_n, .dram(dram.m), .gfx_ctrl(gfx_ctrl.m), + .vdc_ctrl(vdc_ctrl.m), .gfx_vram(gfx_vram.s), .host_dbus(host_dbus.s), .host_ibus(host_ibus.s), .sgdma_mem(sgdma_mem.s), .sgdma_ctrl(sgdma_ctrl.m), + .vdc_stream(vdc_stream.s), .external_io(mmio.m) ); diff --git a/target/w3d_de1soc/w3d_de1soc.sv b/target/w3d_de1soc/w3d_de1soc.sv index 14c31be..10796bc 100644 --- a/target/w3d_de1soc/w3d_de1soc.sv +++ b/target/w3d_de1soc/w3d_de1soc.sv @@ -71,6 +71,9 @@ module w3d_de1soc logic[2:0] mmio_full_arprot, mmio_full_awprot; logic[3:0] mmio_full_arcache, mmio_full_awcache; + logic dac_first, dac_last, dac_ready, dac_valid; + logic[9:0] dac_r, dac_g, dac_b; + debounce reset_debounce ( .clk(sys_clk), @@ -187,12 +190,11 @@ module w3d_de1soc .io_axi_bridge_s0_rvalid(mmio_full_rvalid), .io_axi_bridge_s0_rready(mmio_full_rready), .intc_0_interrupt_sender_irq(), //TODO - //TODO TODO TODO - .pixfifo_avalon_dc_buffer_sink_ready(), - .pixfifo_avalon_dc_buffer_sink_startofpacket(1), - .pixfifo_avalon_dc_buffer_sink_endofpacket(0), - .pixfifo_avalon_dc_buffer_sink_valid(1), - .pixfifo_avalon_dc_buffer_sink_data({10'h3ff, 10'h000, 10'h000}), + .pixfifo_avalon_dc_buffer_sink_ready(dac_ready), + .pixfifo_avalon_dc_buffer_sink_startofpacket(dac_first), + .pixfifo_avalon_dc_buffer_sink_endofpacket(dac_last), + .pixfifo_avalon_dc_buffer_sink_valid(dac_valid), + .pixfifo_avalon_dc_buffer_sink_data({dac_r, dac_g, dac_b}), .sys_clock_out_clk_1_clk(sys_clk), .sys_rst_out_reset_1_reset_n(sys_rst_n) ); @@ -248,6 +250,14 @@ module w3d_de1soc .mmio_rready, .mmio_rdata, + .dac_b, + .dac_g, + .dac_r, + .dac_last, + .dac_first, + .dac_ready, + .dac_valid, + //TODO Altera Virtual JTAG .jtag_tck(0), .jtag_tms(0), |