diff options
| -rw-r--r-- | rtl/core/control/ldst/ldst.sv | 3 | ||||
| -rw-r--r-- | rtl/core/control/psr.sv | 1 | ||||
| -rw-r--r-- | tb/sim/irq.S | 19 |
3 files changed, 22 insertions, 1 deletions
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv index 027fb0a..c8f0dcb 100644 --- a/rtl/core/control/ldst/ldst.sv +++ b/rtl/core/control/ldst/ldst.sv @@ -105,6 +105,7 @@ module core_control_ldst end mem_start <= !cycle.transfer || (mem_ready && pop_valid); - end + end else if(cycle.escalate) + ldst <= 0; end endmodule diff --git a/rtl/core/control/psr.sv b/rtl/core/control/psr.sv index 07bf4e5..ff9b13f 100644 --- a/rtl/core/control/psr.sv +++ b/rtl/core/control/psr.sv @@ -77,6 +77,7 @@ module core_control_psr psr_wr_control <= 1; exception_spsr <= cpsr_rd; end else if(next_cycle.exception) begin + psr <= 0; psr_saved <= 1; psr_wr_flags <= 1; end else if(next_cycle.psr) diff --git a/tb/sim/irq.S b/tb/sim/irq.S index 35ce2c9..2ed4621 100644 --- a/tb/sim/irq.S +++ b/tb/sim/irq.S @@ -29,6 +29,25 @@ reset: str r1, [r2, #4] .wfi: + # Una secuencia de load-stores intensos como esta se encuentra en el + # código de calibración de delay loop del kernel. Antes del commit + # con título 'Fix register corruption when interrupting a load-store', + # una IRQ justo aquí provcaba que el core entrara en un estado indefinido. + # En el caso de Linux, eso resultaba en kernel panics indepurables. + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] tst r0, r0 beq .wfi |