diff options
| -rw-r--r-- | cache_hw.tcl | 256 | ||||
| -rw-r--r-- | core_hw.tcl | 2 | ||||
| -rw-r--r-- | platform.qsys | 213 | ||||
| -rw-r--r-- | rtl/cache/cache.sv | 64 | ||||
| -rw-r--r-- | rtl/cache/cache_control.sv (renamed from rtl/cache/control.sv) | 0 | ||||
| -rw-r--r-- | rtl/cache/defs.sv | 8 | ||||
| -rw-r--r-- | rtl/core/cp15/cache_ops.sv (renamed from rtl/core/cp15/cache.sv) | 0 |
7 files changed, 488 insertions, 55 deletions
diff --git a/cache_hw.tcl b/cache_hw.tcl new file mode 100644 index 0000000..7cae804 --- /dev/null +++ b/cache_hw.tcl @@ -0,0 +1,256 @@ +# TCL File Generated by Component Editor 20.1 +# Sat Sep 30 02:25:24 GMT 2023 +# DO NOT MODIFY + + +# +# cache "8KiB 1-way cache w/ controller" v1.0 +# 2023.09.30.02:25:24 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module cache +# +set_module_property DESCRIPTION "" +set_module_property NAME cache +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME "8KiB 1-way cache w/ controller" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL cache +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file cache.sv SYSTEM_VERILOG PATH rtl/cache/cache.sv TOP_LEVEL_FILE +add_fileset_file cache_control.sv SYSTEM_VERILOG PATH rtl/cache/cache_control.sv +add_fileset_file defs.sv SYSTEM_VERILOG PATH rtl/cache/defs.sv +add_fileset_file offsets.sv SYSTEM_VERILOG PATH rtl/cache/offsets.sv +add_fileset_file routing.sv SYSTEM_VERILOG PATH rtl/cache/routing.sv +add_fileset_file sram.sv SYSTEM_VERILOG PATH rtl/cache/sram.sv + + +# +# parameters +# +add_parameter TOKEN_AT_RESET INTEGER 0 +set_parameter_property TOKEN_AT_RESET DEFAULT_VALUE 0 +set_parameter_property TOKEN_AT_RESET DISPLAY_NAME TOKEN_AT_RESET +set_parameter_property TOKEN_AT_RESET TYPE INTEGER +set_parameter_property TOKEN_AT_RESET UNITS None +set_parameter_property TOKEN_AT_RESET ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property TOKEN_AT_RESET AFFECTS_GENERATION false +set_parameter_property TOKEN_AT_RESET HDL_PARAMETER true + + +# +# display items +# + + +# +# connection point clock_sink +# +add_interface clock_sink clock end +set_interface_property clock_sink clockRate 0 +set_interface_property clock_sink ENABLED true +set_interface_property clock_sink EXPORT_OF "" +set_interface_property clock_sink PORT_NAME_MAP "" +set_interface_property clock_sink CMSIS_SVD_VARIABLES "" +set_interface_property clock_sink SVD_ADDRESS_GROUP "" + +add_interface_port clock_sink clk clk Input 1 + + +# +# connection point reset_sink +# +add_interface reset_sink reset end +set_interface_property reset_sink associatedClock clock_sink +set_interface_property reset_sink synchronousEdges DEASSERT +set_interface_property reset_sink ENABLED true +set_interface_property reset_sink EXPORT_OF "" +set_interface_property reset_sink PORT_NAME_MAP "" +set_interface_property reset_sink CMSIS_SVD_VARIABLES "" +set_interface_property reset_sink SVD_ADDRESS_GROUP "" + +add_interface_port reset_sink rst_n reset_n Input 1 + + +# +# connection point core +# +add_interface core avalon end +set_interface_property core addressUnits WORDS +set_interface_property core associatedClock clock_sink +set_interface_property core associatedReset reset_sink +set_interface_property core bitsPerSymbol 8 +set_interface_property core burstOnBurstBoundariesOnly false +set_interface_property core burstcountUnits WORDS +set_interface_property core explicitAddressSpan 0 +set_interface_property core holdTime 0 +set_interface_property core linewrapBursts false +set_interface_property core maximumPendingReadTransactions 0 +set_interface_property core maximumPendingWriteTransactions 0 +set_interface_property core readLatency 0 +set_interface_property core readWaitTime 1 +set_interface_property core setupTime 0 +set_interface_property core timingUnits Cycles +set_interface_property core writeWaitTime 0 +set_interface_property core ENABLED true +set_interface_property core EXPORT_OF "" +set_interface_property core PORT_NAME_MAP "" +set_interface_property core CMSIS_SVD_VARIABLES "" +set_interface_property core SVD_ADDRESS_GROUP "" + +add_interface_port core core_address address Input 30 +add_interface_port core core_read read Input 1 +add_interface_port core core_write write Input 1 +add_interface_port core core_waitrequest waitrequest Output 1 +add_interface_port core core_readdata readdata Output 32 +add_interface_port core core_writedata writedata Input 32 +add_interface_port core core_byteenable byteenable Input 4 +set_interface_assignment core embeddedsw.configuration.isFlash 0 +set_interface_assignment core embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment core embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment core embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point out_data +# +add_interface out_data avalon_streaming start +set_interface_property out_data associatedClock clock_sink +set_interface_property out_data associatedReset reset_sink +set_interface_property out_data dataBitsPerSymbol 8 +set_interface_property out_data errorDescriptor "" +set_interface_property out_data firstSymbolInHighOrderBits true +set_interface_property out_data maxChannel 0 +set_interface_property out_data readyLatency 0 +set_interface_property out_data ENABLED true +set_interface_property out_data EXPORT_OF "" +set_interface_property out_data PORT_NAME_MAP "" +set_interface_property out_data CMSIS_SVD_VARIABLES "" +set_interface_property out_data SVD_ADDRESS_GROUP "" + +add_interface_port out_data out_data_ready ready Input 1 +add_interface_port out_data out_data_valid valid Output 1 +add_interface_port out_data out_data data Output 160 + + +# +# connection point in_data +# +add_interface in_data avalon_streaming end +set_interface_property in_data associatedClock clock_sink +set_interface_property in_data associatedReset reset_sink +set_interface_property in_data dataBitsPerSymbol 8 +set_interface_property in_data errorDescriptor "" +set_interface_property in_data firstSymbolInHighOrderBits true +set_interface_property in_data maxChannel 0 +set_interface_property in_data readyLatency 0 +set_interface_property in_data ENABLED true +set_interface_property in_data EXPORT_OF "" +set_interface_property in_data PORT_NAME_MAP "" +set_interface_property in_data CMSIS_SVD_VARIABLES "" +set_interface_property in_data SVD_ADDRESS_GROUP "" + +add_interface_port in_data in_data data Input 160 +add_interface_port in_data in_data_ready ready Output 1 +add_interface_port in_data in_data_valid valid Input 1 + + +# +# connection point out_token +# +add_interface out_token avalon_streaming start +set_interface_property out_token associatedClock clock_sink +set_interface_property out_token associatedReset reset_sink +set_interface_property out_token dataBitsPerSymbol 8 +set_interface_property out_token errorDescriptor "" +set_interface_property out_token firstSymbolInHighOrderBits true +set_interface_property out_token maxChannel 0 +set_interface_property out_token readyLatency 0 +set_interface_property out_token ENABLED true +set_interface_property out_token EXPORT_OF "" +set_interface_property out_token PORT_NAME_MAP "" +set_interface_property out_token CMSIS_SVD_VARIABLES "" +set_interface_property out_token SVD_ADDRESS_GROUP "" + +add_interface_port out_token out_token data Output 80 +add_interface_port out_token out_token_valid valid Output 1 + + +# +# connection point in_token +# +add_interface in_token avalon_streaming end +set_interface_property in_token associatedClock clock_sink +set_interface_property in_token associatedReset reset_sink +set_interface_property in_token dataBitsPerSymbol 8 +set_interface_property in_token errorDescriptor "" +set_interface_property in_token firstSymbolInHighOrderBits true +set_interface_property in_token maxChannel 0 +set_interface_property in_token readyLatency 0 +set_interface_property in_token ENABLED true +set_interface_property in_token EXPORT_OF "" +set_interface_property in_token PORT_NAME_MAP "" +set_interface_property in_token CMSIS_SVD_VARIABLES "" +set_interface_property in_token SVD_ADDRESS_GROUP "" + +add_interface_port in_token in_token data Input 80 +add_interface_port in_token in_token_valid valid Input 1 + + +# +# connection point mem +# +add_interface mem avalon start +set_interface_property mem addressUnits SYMBOLS +set_interface_property mem associatedClock clock_sink +set_interface_property mem associatedReset reset_sink +set_interface_property mem bitsPerSymbol 8 +set_interface_property mem burstOnBurstBoundariesOnly false +set_interface_property mem burstcountUnits WORDS +set_interface_property mem doStreamReads false +set_interface_property mem doStreamWrites false +set_interface_property mem holdTime 0 +set_interface_property mem linewrapBursts false +set_interface_property mem maximumPendingReadTransactions 0 +set_interface_property mem maximumPendingWriteTransactions 0 +set_interface_property mem readLatency 0 +set_interface_property mem readWaitTime 1 +set_interface_property mem setupTime 0 +set_interface_property mem timingUnits Cycles +set_interface_property mem writeWaitTime 0 +set_interface_property mem ENABLED true +set_interface_property mem EXPORT_OF "" +set_interface_property mem PORT_NAME_MAP "" +set_interface_property mem CMSIS_SVD_VARIABLES "" +set_interface_property mem SVD_ADDRESS_GROUP "" + +add_interface_port mem mem_read read Output 1 +add_interface_port mem mem_write write Output 1 +add_interface_port mem mem_address address Output 32 +add_interface_port mem mem_byteenable byteenable Output 16 +add_interface_port mem mem_readdata readdata Input 128 +add_interface_port mem mem_writedata writedata Output 128 +add_interface_port mem mem_waitrequest waitrequest Input 1 + diff --git a/core_hw.tcl b/core_hw.tcl index 852e6c5..93b6def 100644 --- a/core_hw.tcl +++ b/core_hw.tcl @@ -66,7 +66,7 @@ add_fileset_file writeback.sv SYSTEM_VERILOG PATH rtl/core/control/writeback.sv add_fileset_file ldst.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/ldst.sv add_fileset_file pop.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/pop.sv add_fileset_file sizes.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/sizes.sv -add_fileset_file cache.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache.sv +add_fileset_file cache_ops.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache_ops.sv add_fileset_file cache_lockdown.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache_lockdown.sv add_fileset_file cp15.sv SYSTEM_VERILOG PATH rtl/core/cp15/cp15.sv add_fileset_file cpuid.sv SYSTEM_VERILOG PATH rtl/core/cp15/cpuid.sv diff --git a/platform.qsys b/platform.qsys index 67399ba..d8ed205 100644 --- a/platform.qsys +++ b/platform.qsys @@ -25,6 +25,38 @@ type = "int"; } } + element cache_0 + { + datum _sortIndex + { + value = "20"; + type = "int"; + } + } + element cache_1 + { + datum _sortIndex + { + value = "22"; + type = "int"; + } + } + element cache_2 + { + datum _sortIndex + { + value = "24"; + type = "int"; + } + } + element cache_3 + { + datum _sortIndex + { + value = "26"; + type = "int"; + } + } element clk_0 { datum _sortIndex @@ -41,6 +73,30 @@ type = "int"; } } + element cpu_1 + { + datum _sortIndex + { + value = "21"; + type = "int"; + } + } + element cpu_2 + { + datum _sortIndex + { + value = "23"; + type = "int"; + } + } + element cpu_3 + { + datum _sortIndex + { + value = "25"; + type = "int"; + } + } element hps_0 { datum _sortIndex @@ -73,7 +129,7 @@ type = "int"; } } - element mm_bridge_1 + element mm_bridge { datum _sortIndex { @@ -293,6 +349,18 @@ <parameter name="simDrivenValue" value="0" /> <parameter name="width" value="8" /> </module> + <module name="cache_0" kind="cache" version="1.0" enabled="1"> + <parameter name="TOKEN_AT_RESET" value="0" /> + </module> + <module name="cache_1" kind="cache" version="1.0" enabled="1"> + <parameter name="TOKEN_AT_RESET" value="0" /> + </module> + <module name="cache_2" kind="cache" version="1.0" enabled="1"> + <parameter name="TOKEN_AT_RESET" value="0" /> + </module> + <module name="cache_3" kind="cache" version="1.0" enabled="1"> + <parameter name="TOKEN_AT_RESET" value="1" /> + </module> <module name="clk_0" kind="clock_source" version="20.1" enabled="1"> <parameter name="clockFrequency" value="50000000" /> <parameter name="clockFrequencyKnown" value="true" /> @@ -302,6 +370,15 @@ <module name="cpu_0" kind="core" version="1.0" enabled="1"> <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="1" /> </module> + <module name="cpu_1" kind="core" version="1.0" enabled="0"> + <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="0" /> + </module> + <module name="cpu_2" kind="core" version="1.0" enabled="0"> + <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="0" /> + </module> + <module name="cpu_3" kind="core" version="1.0" enabled="0"> + <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="0" /> + </module> <module name="hps_0" kind="altera_hps" version="20.1" enabled="1"> <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" /> <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" /> @@ -870,13 +947,13 @@ <parameter name="writeIRQThreshold" value="8" /> </module> <module - name="mm_bridge_1" + name="mm_bridge" kind="altera_avalon_mm_bridge" version="20.1" enabled="1"> <parameter name="ADDRESS_UNITS" value="SYMBOLS" /> <parameter name="ADDRESS_WIDTH" value="32" /> - <parameter name="DATA_WIDTH" value="32" /> + <parameter name="DATA_WIDTH" value="128" /> <parameter name="LINEWRAPBURSTS" value="0" /> <parameter name="MAX_BURST_SIZE" value="1" /> <parameter name="MAX_PENDING_RESPONSES" value="4" /> @@ -1260,7 +1337,7 @@ <connection kind="avalon" version="20.1" - start="mm_bridge_1.m0" + start="mm_bridge.m0" end="pixdma.avalon_control_slave"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x30030000" /> @@ -1269,7 +1346,7 @@ <connection kind="avalon" version="20.1" - start="mm_bridge_1.m0" + start="mm_bridge.m0" end="jtag_uart_0.avalon_jtag_slave"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x30000000" /> @@ -1278,7 +1355,7 @@ <connection kind="avalon" version="20.1" - start="mm_bridge_1.m0" + start="mm_bridge.m0" end="pixfmt.avalon_rgb_slave"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x30040000" /> @@ -1287,33 +1364,33 @@ <connection kind="avalon" version="20.1" - start="mm_bridge_1.m0" + start="mm_bridge.m0" end="intc_0.avalon_slave"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x30070000" /> <parameter name="defaultConnection" value="false" /> </connection> - <connection kind="avalon" version="20.1" start="mm_bridge_1.m0" end="buttons.s1"> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="buttons.s1"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x30050000" /> <parameter name="defaultConnection" value="false" /> </connection> - <connection kind="avalon" version="20.1" start="mm_bridge_1.m0" end="pio_0.s1"> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="pio_0.s1"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x30010000" /> <parameter name="defaultConnection" value="false" /> </connection> - <connection kind="avalon" version="20.1" start="mm_bridge_1.m0" end="switches.s1"> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="switches.s1"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x30060000" /> <parameter name="defaultConnection" value="false" /> </connection> - <connection kind="avalon" version="20.1" start="mm_bridge_1.m0" end="timer_0.s1"> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="timer_0.s1"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x30020000" /> <parameter name="defaultConnection" value="false" /> </connection> - <connection kind="avalon" version="20.1" start="mm_bridge_1.m0" end="vram.s1"> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="vram.s1"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x38000000" /> <parameter name="defaultConnection" value="false" /> @@ -1321,26 +1398,42 @@ <connection kind="avalon" version="20.1" - start="mm_bridge_1.m0" + start="mm_bridge.m0" end="address_span_extender_0.windowed_slave"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x0000" /> <parameter name="defaultConnection" value="false" /> </connection> + <connection kind="avalon" version="20.1" start="cpu_0.master" end="cache_0.core"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + </connection> <connection kind="avalon" version="20.1" start="jtag_dbg.master" - end="mm_bridge_1.s0"> + end="mm_bridge.s0"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x0000" /> <parameter name="defaultConnection" value="false" /> </connection> - <connection - kind="avalon" - version="20.1" - start="cpu_0.master" - end="mm_bridge_1.s0"> + <connection kind="avalon" version="20.1" start="cache_0.mem" end="mm_bridge.s0"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="avalon" version="20.1" start="cache_1.mem" end="mm_bridge.s0"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="avalon" version="20.1" start="cache_2.mem" end="mm_bridge.s0"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="avalon" version="20.1" start="cache_3.mem" end="mm_bridge.s0"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x0000" /> <parameter name="defaultConnection" value="false" /> @@ -1361,6 +1454,46 @@ start="pixfmt.avalon_rgb_source" end="pixfifo.avalon_dc_buffer_sink" /> <connection + kind="avalon_streaming" + version="20.1" + start="cache_0.out_data" + end="cache_1.in_data" /> + <connection + kind="avalon_streaming" + version="20.1" + start="cache_3.out_data" + end="cache_0.in_data" /> + <connection + kind="avalon_streaming" + version="20.1" + start="cache_1.out_data" + end="cache_2.in_data" /> + <connection + kind="avalon_streaming" + version="20.1" + start="cache_2.out_data" + end="cache_3.in_data" /> + <connection + kind="avalon_streaming" + version="20.1" + start="cache_0.out_token" + end="cache_1.in_token" /> + <connection + kind="avalon_streaming" + version="20.1" + start="cache_3.out_token" + end="cache_0.in_token" /> + <connection + kind="avalon_streaming" + version="20.1" + start="cache_1.out_token" + end="cache_2.in_token" /> + <connection + kind="avalon_streaming" + version="20.1" + start="cache_2.out_token" + end="cache_3.in_token" /> + <connection kind="clock" version="20.1" start="clk_0.clk" @@ -1396,16 +1529,32 @@ version="20.1" start="pll_0.outclk0" end="hps_0.f2h_sdram0_clock" /> + <connection kind="clock" version="20.1" start="pll_0.outclk1" end="mm_bridge.clk" /> <connection kind="clock" version="20.1" start="pll_0.outclk1" - end="mm_bridge_1.clk" /> + end="cpu_0.clock_sink" /> <connection kind="clock" version="20.1" start="pll_0.outclk1" - end="cpu_0.clock_sink" /> + end="cache_0.clock_sink" /> + <connection + kind="clock" + version="20.1" + start="pll_0.outclk1" + end="cache_1.clock_sink" /> + <connection + kind="clock" + version="20.1" + start="pll_0.outclk1" + end="cache_2.clock_sink" /> + <connection + kind="clock" + version="20.1" + start="pll_0.outclk1" + end="cache_3.clock_sink" /> <connection kind="clock" version="20.1" @@ -1498,7 +1647,7 @@ kind="reset" version="20.1" start="clk_0.clk_reset" - end="mm_bridge_1.reset" /> + end="mm_bridge.reset" /> <connection kind="reset" version="20.1" @@ -1512,6 +1661,26 @@ <connection kind="reset" version="20.1" + start="clk_0.clk_reset" + end="cache_0.reset_sink" /> + <connection + kind="reset" + version="20.1" + start="clk_0.clk_reset" + end="cache_1.reset_sink" /> + <connection + kind="reset" + version="20.1" + start="clk_0.clk_reset" + end="cache_2.reset_sink" /> + <connection + kind="reset" + version="20.1" + start="clk_0.clk_reset" + end="cache_3.reset_sink" /> + <connection + kind="reset" + version="20.1" start="sys_sdram_pll_0.reset_source" end="vram.reset" /> <connection diff --git a/rtl/cache/cache.sv b/rtl/cache/cache.sv index b84f844..e62a326 100644 --- a/rtl/cache/cache.sv +++ b/rtl/cache/cache.sv @@ -3,40 +3,40 @@ module cache #(parameter TOKEN_AT_RESET=0) ( - input logic clk, - rst_n, + input logic clk, + rst_n, - input ptr core_address, - input logic core_read, - core_write, - input word core_writedata, - input word_be core_byteenable, - output logic core_waitrequest, - output word core_readdata, + input ptr core_address, + input logic core_read, + core_write, + input word core_writedata, + input word_be core_byteenable, + output logic core_waitrequest, + output word core_readdata, //TODO - //input /*TODO*/ dbg_address, - input logic dbg_read, - dbg_write, - input word dbg_writedata, - output logic dbg_waitrequest, - output word dbg_readdata, - - input logic mem_waitrequest, - input line mem_readdata, - output word mem_address, - output logic mem_read, - mem_write, - output line mem_writedata, - output line_be mem_byteenable, - - input logic in_data_valid, - input ring_req in_data, - output logic in_data_ready, - - input logic out_data_ready, - output ring_req out_data, - output logic out_data_valid, + /*input TODO/ dbg_address, + input logic dbg_read, + dbg_write, + input word dbg_writedata, + output logic dbg_waitrequest, + output word dbg_readdata,*/ + + input logic mem_waitrequest, + input line mem_readdata, + output word mem_address, + output logic mem_read, + mem_write, + output line mem_writedata, + output line_be mem_byteenable, + + input logic in_data_valid, + input ring_req in_data, + output logic in_data_ready, + + input logic out_data_ready, + output ring_req out_data, + output logic out_data_valid, input ring_token in_token, input logic in_token_valid, @@ -46,7 +46,7 @@ module cache ); //TODO - assign dbg_waitrequest = 1; + //assign dbg_waitrequest = 1; logic write_data, write_state; line data_wr, data_rd; diff --git a/rtl/cache/control.sv b/rtl/cache/cache_control.sv index 73eb644..73eb644 100644 --- a/rtl/cache/control.sv +++ b/rtl/cache/cache_control.sv diff --git a/rtl/cache/defs.sv b/rtl/cache/defs.sv index 6fdb719..bfefb88 100644 --- a/rtl/cache/defs.sv +++ b/rtl/cache/defs.sv @@ -38,6 +38,10 @@ typedef enum logic[1:0] typedef struct packed { +`ifndef VERILATOR + // Error: data width (158) must be a multiple of bitsPerSymbol (8) + logic[1:0] padding; +`endif logic[1:0] ttl; logic read, inval, @@ -59,6 +63,10 @@ typedef struct packed typedef struct packed { +`ifndef VERILATOR + // Error: data width (78) must be a multiple of bitsPerSymbol (8) + logic[1:0] padding; +`endif token_lock e2, e1, e0; } ring_token; diff --git a/rtl/core/cp15/cache.sv b/rtl/core/cp15/cache_ops.sv index cb6d4ad..cb6d4ad 100644 --- a/rtl/core/cp15/cache.sv +++ b/rtl/core/cp15/cache_ops.sv |