diff options
| -rw-r--r-- | rtl/core/mul.sv | 1 | ||||
| -rw-r--r-- | tb/top/test_smp.py | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/rtl/core/mul.sv b/rtl/core/mul.sv index 7c30d0c..19bbb9a 100644 --- a/rtl/core/mul.sv +++ b/rtl/core/mul.sv @@ -31,6 +31,7 @@ module core_mul assign z = q_lo == 0 && (!long_mul || q_hi == 0); //TODO: no está probado cuantos ciclos ocupa esto una vez sintetizado + //TODO: trivio? dsp_mul it ( .clock0(clk), diff --git a/tb/top/test_smp.py b/tb/top/test_smp.py index c70b76b..5960373 100644 --- a/tb/top/test_smp.py +++ b/tb/top/test_smp.py @@ -7,7 +7,7 @@ from tb.models import CorePaceModel, SmpModel @cocotb.test() async def reset(dut): - cocotb.start(Clock(dut.clk, 2).start()) + await cocotb.start(Clock(dut.clk, 2).start()) dut.rst_n.value = 1 await Timer(1) |