diff options
| -rw-r--r-- | cache_hw.tcl | 43 | ||||
| -rw-r--r-- | platform.qsys | 28 | ||||
| -rw-r--r-- | rtl/cache/cache.sv | 18 | ||||
| -rw-r--r-- | rtl/cache/cache_control.sv | 20 | ||||
| -rw-r--r-- | rtl/cache/cache_debug.sv | 71 | ||||
| -rw-r--r-- | rtl/cache/defs.sv | 9 | ||||
| -rw-r--r-- | tb/platform.sv | 96 | ||||
| -rw-r--r-- | tb/top/conspiracion.cpp | 8 |
8 files changed, 274 insertions, 19 deletions
diff --git a/cache_hw.tcl b/cache_hw.tcl index 31aa5af..cedffb4 100644 --- a/cache_hw.tcl +++ b/cache_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 20.1 -# Tue Oct 03 10:41:50 GMT 2023 +# Wed Oct 04 09:06:39 GMT 2023 # DO NOT MODIFY # # cache "8KiB 1-way cache w/ controller" v1.0 -# 2023.10.03.10:41:50 +# 2023.10.04.09:06:39 # # @@ -46,6 +46,7 @@ add_fileset_file offsets.sv SYSTEM_VERILOG PATH rtl/cache/offsets.sv add_fileset_file routing.sv SYSTEM_VERILOG PATH rtl/cache/routing.sv add_fileset_file sram.sv SYSTEM_VERILOG PATH rtl/cache/sram.sv add_fileset_file monitor.sv SYSTEM_VERILOG PATH rtl/cache/monitor.sv +add_fileset_file cache_debug.sv SYSTEM_VERILOG PATH rtl/cache/cache_debug.sv # @@ -257,3 +258,41 @@ add_interface_port mem mem_readdata readdata Input 128 add_interface_port mem mem_writedata writedata Output 128 add_interface_port mem mem_waitrequest waitrequest Input 1 + +# +# connection point dbg +# +add_interface dbg avalon end +set_interface_property dbg addressUnits WORDS +set_interface_property dbg associatedClock clock_sink +set_interface_property dbg associatedReset reset_sink +set_interface_property dbg bitsPerSymbol 8 +set_interface_property dbg burstOnBurstBoundariesOnly false +set_interface_property dbg burstcountUnits WORDS +set_interface_property dbg explicitAddressSpan 0 +set_interface_property dbg holdTime 0 +set_interface_property dbg linewrapBursts false +set_interface_property dbg maximumPendingReadTransactions 0 +set_interface_property dbg maximumPendingWriteTransactions 0 +set_interface_property dbg readLatency 0 +set_interface_property dbg readWaitTime 1 +set_interface_property dbg setupTime 0 +set_interface_property dbg timingUnits Cycles +set_interface_property dbg writeWaitTime 0 +set_interface_property dbg ENABLED true +set_interface_property dbg EXPORT_OF "" +set_interface_property dbg PORT_NAME_MAP "" +set_interface_property dbg CMSIS_SVD_VARIABLES "" +set_interface_property dbg SVD_ADDRESS_GROUP "" + +add_interface_port dbg dbg_read read Input 1 +add_interface_port dbg dbg_write write Input 1 +add_interface_port dbg dbg_address address Input 3 +add_interface_port dbg dbg_readdata readdata Output 32 +add_interface_port dbg dbg_waitrequest waitrequest Output 1 +add_interface_port dbg dbg_writedata writedata Input 32 +set_interface_assignment dbg embeddedsw.configuration.isFlash 0 +set_interface_assignment dbg embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment dbg embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment dbg embeddedsw.configuration.isPrintableDevice 0 + diff --git a/platform.qsys b/platform.qsys index 7190777..4a9fa44 100644 --- a/platform.qsys +++ b/platform.qsys @@ -222,6 +222,14 @@ type = "String"; } } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } element pll_0 { datum _sortIndex @@ -1399,6 +1407,26 @@ <parameter name="baseAddress" value="0x30140000" /> <parameter name="defaultConnection" value="false" /> </connection> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="cache_0.dbg"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x30100000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="cache_1.dbg"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x30110000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="cache_2.dbg"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x30120000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="cache_3.dbg"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x30130000" /> + <parameter name="defaultConnection" value="false" /> + </connection> <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="buttons.s1"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x30050000" /> diff --git a/rtl/cache/cache.sv b/rtl/cache/cache.sv index 1b327b4..6d5a204 100644 --- a/rtl/cache/cache.sv +++ b/rtl/cache/cache.sv @@ -16,13 +16,12 @@ module cache output logic[1:0] core_response, output word core_readdata, - //TODO - /*input TODO/ dbg_address, + input logic[2:0] dbg_address, input logic dbg_read, dbg_write, input word dbg_writedata, output logic dbg_waitrequest, - output word dbg_readdata,*/ + output word dbg_readdata, input logic mem_waitrequest, input line mem_readdata, @@ -47,9 +46,6 @@ module cache output logic out_token_valid ); - //TODO - //assign dbg_waitrequest = 1; - logic write_data, write_state; line data_wr, data_rd; addr_tag tag_wr, tag_rd; @@ -63,7 +59,8 @@ module cache word cache_mem_address; line cache_mem_writedata; - logic cache_core_waitrequest, cache_mem_waitrequest, cache_mem_read, cache_mem_write; + logic cache_core_waitrequest, cache_mem_waitrequest, cache_mem_read, cache_mem_write, + debug_ready; cache_control #(.TOKEN_AT_RESET(TOKEN_AT_RESET)) control ( @@ -105,4 +102,11 @@ module cache .* ); + addr_index debug_index; + + cache_debug debug + ( + .* + ); + endmodule diff --git a/rtl/cache/cache_control.sv b/rtl/cache/cache_control.sv index 090fba4..46d4638 100644 --- a/rtl/cache/cache_control.sv +++ b/rtl/cache/cache_control.sv @@ -51,7 +51,11 @@ module cache_control output word mem_address, output logic mem_read, mem_write, - output line mem_writedata + output line mem_writedata, + + input logic dbg_write, + input addr_index debug_index, + output logic debug_ready ); enum int unsigned @@ -62,8 +66,8 @@ module cache_control REPLY } state, next_state; - logic accept_snoop, end_reply, in_hold_valid, last_hop, lock_line, locked, - may_send, may_send_if_token_held, mem_begin, mem_end, mem_read_end, + logic accept_snoop, debug, end_reply, in_hold_valid, last_hop, lock_line, + locked, may_send, may_send_if_token_held, mem_begin, mem_end, mem_read_end, mem_wait, out_stall, wait_reply, replace, retry, send, send_inval, send_read, snoop_hit, set_reply, unlock_line, writeback; @@ -145,6 +149,9 @@ module cache_control if (accept_snoop) index_rd = in_hold.index; + + if (debug) + index_rd = debug_index; end CORE: begin @@ -321,6 +328,7 @@ module cache_control end always_comb begin + debug = 0; next_state = ACCEPT; unique case (state) @@ -329,6 +337,8 @@ module cache_control next_state = SNOOP; else if (in_hold_valid && last_hop && in_hold.read) next_state = REPLY; + else if (dbg_write && !debug_ready) + debug = 1; else if ((core_read || core_write) && !wait_reply && (!locked || may_send)) next_state = CORE; @@ -356,6 +366,8 @@ module cache_control mem_read <= 0; mem_write <= 0; + + debug_ready <= 0; end else begin out_token.e0.tag <= core_tag; out_token.e0.index <= core_index; @@ -391,6 +403,8 @@ module cache_control mem_read <= !writeback; mem_write <= writeback; end + + debug_ready <= debug; end always_ff @(posedge clk) begin diff --git a/rtl/cache/cache_debug.sv b/rtl/cache/cache_debug.sv new file mode 100644 index 0000000..14b73e5 --- /dev/null +++ b/rtl/cache/cache_debug.sv @@ -0,0 +1,71 @@ +`include "cache/defs.sv" + +module cache_debug +( + input logic clk, + rst_n, + + input logic[2:0] dbg_address, + input logic dbg_read, + input word dbg_writedata, + output logic dbg_waitrequest, + output word dbg_readdata, + + input logic debug_ready, + input addr_tag tag_rd, + input line data_rd, + input line_state state_rd, + output addr_index debug_index +); + + struct packed + { + logic[2:0] mbz_0; + addr_tag tag; + addr_index index; + line_state state; + logic cached, + mbz_1; + } status; + + line line_dump; + word word_dump, word_3, word_2, word_1, word_0; + addr_bits debug_addr_bits; + + logic cached; + addr_tag tag; + addr_index index; + line_state state; + + assign debug_index = debug_addr_bits.index; + assign dbg_readdata = dbg_address[2] ? word_dump : status; + assign dbg_waitrequest = !debug_ready && !dbg_read; + + assign status.tag = tag; + assign status.index = index; + assign status.state = state; + assign status.mbz_0 = 3'b000; + assign status.mbz_1 = 0; + assign status.cached = cached; + assign debug_addr_bits = dbg_writedata; + + assign {word_3, word_2, word_1, word_0} = line_dump; + + always_comb + unique case (dbg_address[1:0]) + 2'b00: word_dump = word_0; + 2'b01: word_dump = word_1; + 2'b10: word_dump = word_2; + 2'b11: word_dump = word_3; + endcase + + always @(posedge clk) + if (debug_ready) begin + tag <= tag_rd; + index <= debug_addr_bits.index; + state <= state_rd; + cached <= !(|debug_addr_bits.io); + line_dump <= data_rd; + end + +endmodule diff --git a/rtl/cache/defs.sv b/rtl/cache/defs.sv index e21e587..0546c4d 100644 --- a/rtl/cache/defs.sv +++ b/rtl/cache/defs.sv @@ -28,6 +28,15 @@ typedef logic[15:0] addr_tag; typedef logic[2:0] addr_io_region; typedef logic[26:0] addr_cacheable; +typedef struct packed +{ + addr_io_region io; + addr_tag tag; + addr_index index; + addr_offset offset; + addr_mbz mbz; +} addr_bits; + typedef enum logic[1:0] { INVALID, diff --git a/tb/platform.sv b/tb/platform.sv index fddf6e8..bbf1088 100644 --- a/tb/platform.sv +++ b/tb/platform.sv @@ -65,13 +65,19 @@ module platform logic mem_0_waitrequest, mem_1_waitrequest, mem_2_waitrequest, mem_3_waitrequest; logic[15:0] mem_0_byteenable, mem_1_byteenable, mem_2_byteenable, mem_3_byteenable; - logic[31:0] cpu_0_address, cpu_1_address, cpu_2_address, cpu_3_address; - logic cpu_0_read, cpu_1_read, cpu_2_read, cpu_3_read; - logic cpu_0_write, cpu_1_write, cpu_2_write, cpu_3_write; - logic cpu_0_lock, cpu_1_lock, cpu_2_lock, cpu_3_lock; - logic[31:0] cpu_0_readdata, cpu_1_readdata, cpu_2_readdata, cpu_3_readdata; - logic[31:0] cpu_0_writedata, cpu_1_writedata, cpu_2_writedata, cpu_3_writedata; - logic cpu_0_waitrequest, cpu_1_waitrequest, cpu_2_waitrequest, cpu_3_waitrequest; + logic[31:0] cpu_0_address, cpu_1_address, cpu_2_address, cpu_3_address, + dbg_0_address, dbg_1_address, dbg_2_address, dbg_3_address; + logic cpu_0_read, cpu_1_read, cpu_2_read, cpu_3_read, + dbg_0_read, dbg_1_read, dbg_2_read, dbg_3_read, + cpu_0_write, cpu_1_write, cpu_2_write, cpu_3_write, + dbg_0_write, dbg_1_write, dbg_2_write, dbg_3_write, + cpu_0_lock, cpu_1_lock, cpu_2_lock, cpu_3_lock; + logic[31:0] cpu_0_readdata, cpu_1_readdata, cpu_2_readdata, cpu_3_readdata, + dbg_0_readdata, dbg_1_readdata, dbg_2_readdata, dbg_3_readdata; + logic[31:0] cpu_0_writedata, cpu_1_writedata, cpu_2_writedata, cpu_3_writedata, + dbg_0_writedata, dbg_1_writedata, dbg_2_writedata, dbg_3_writedata; + logic cpu_0_waitrequest, cpu_1_waitrequest, cpu_2_waitrequest, cpu_3_waitrequest, + dbg_0_waitrequest, dbg_1_waitrequest, dbg_2_waitrequest, dbg_3_waitrequest; logic[1:0] cpu_0_response, cpu_1_response, cpu_2_response, cpu_3_response; logic[3:0] cpu_0_byteenable, cpu_1_byteenable, cpu_2_byteenable, cpu_3_byteenable; @@ -196,6 +202,25 @@ module platform .out_token(token_0), .out_token_valid(token_valid_0), + .dbg_read(dbg_0_read), + .dbg_write(dbg_0_write), + .dbg_address(dbg_0_address[2:0]), + .dbg_readdata(dbg_0_readdata), + .dbg_writedata(dbg_0_writedata), + .dbg_waitrequest(dbg_0_waitrequest), + + .* + ); + + sim_slave smp_dbg_0 + ( + .read(dbg_0_read), + .write(dbg_0_write), + .address(dbg_0_address), + .readdata(dbg_0_readdata), + .writedata(dbg_0_writedata), + .waitrequest(dbg_0_waitrequest), + .* ); @@ -233,6 +258,25 @@ module platform .out_token(token_1), .out_token_valid(token_valid_1), + .dbg_read(dbg_1_read), + .dbg_write(dbg_1_write), + .dbg_address(dbg_1_address[2:0]), + .dbg_readdata(dbg_1_readdata), + .dbg_writedata(dbg_1_writedata), + .dbg_waitrequest(dbg_1_waitrequest), + + .* + ); + + sim_slave smp_dbg_1 + ( + .read(dbg_1_read), + .write(dbg_1_write), + .address(dbg_1_address), + .readdata(dbg_1_readdata), + .writedata(dbg_1_writedata), + .waitrequest(dbg_1_waitrequest), + .* ); @@ -270,6 +314,25 @@ module platform .out_token(token_2), .out_token_valid(token_valid_2), + .dbg_read(dbg_2_read), + .dbg_write(dbg_2_write), + .dbg_address(dbg_2_address[2:0]), + .dbg_readdata(dbg_2_readdata), + .dbg_writedata(dbg_2_writedata), + .dbg_waitrequest(dbg_2_waitrequest), + + .* + ); + + sim_slave smp_dbg_2 + ( + .read(dbg_2_read), + .write(dbg_2_write), + .address(dbg_2_address), + .readdata(dbg_2_readdata), + .writedata(dbg_2_writedata), + .waitrequest(dbg_2_waitrequest), + .* ); @@ -307,6 +370,25 @@ module platform .out_token(token_3), .out_token_valid(token_valid_3), + .dbg_read(dbg_3_read), + .dbg_write(dbg_3_write), + .dbg_address(dbg_3_address[2:0]), + .dbg_readdata(dbg_3_readdata), + .dbg_writedata(dbg_3_writedata), + .dbg_waitrequest(dbg_3_waitrequest), + + .* + ); + + sim_slave smp_dbg_3 + ( + .read(dbg_3_read), + .write(dbg_3_write), + .address(dbg_3_address), + .readdata(dbg_3_readdata), + .writedata(dbg_3_writedata), + .waitrequest(dbg_3_waitrequest), + .* ); diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp index 26ea1f0..0bb2f11 100644 --- a/tb/top/conspiracion.cpp +++ b/tb/top/conspiracion.cpp @@ -333,6 +333,10 @@ int main(int argc, char **argv) *plat.vga, 0x3800'0000, 25'175'000, 50'000'000 ); + sim_slave dbg_0(*plat.smp_dbg_0, 0x3010'0000, 8); + sim_slave dbg_1(*plat.smp_dbg_1, 0x3011'0000, 8); + sim_slave dbg_2(*plat.smp_dbg_2, 0x3012'0000, 8); + sim_slave dbg_3(*plat.smp_dbg_3, 0x3013'0000, 8); sim_slave smp_ctrl(*plat.smp_sim, 0x3014'0000, 4); interconnect<Vconspiracion_platform> avl(plat); @@ -350,6 +354,10 @@ int main(int argc, char **argv) avl.attach(hps_ddr3); avl.attach(timer); avl.attach(ttyJ0); + avl.attach(dbg_0); + avl.attach(dbg_1); + avl.attach(dbg_2); + avl.attach(dbg_3); avl.attach(smp_ctrl); avl.attach_intc(intc); |