diff options
| -rw-r--r-- | conspiracion.qsf | 20 | ||||
| -rw-r--r-- | rtl/core/cycles.sv | 1 | ||||
| -rw-r--r-- | rtl/core/decode/decode.sv | 2 | ||||
| -rw-r--r-- | rtl/core/regs/file.sv | 15 |
4 files changed, 31 insertions, 7 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf index 4242e25..c81ea0a 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -213,13 +213,31 @@ set_location_assignment PIN_AF14 -to clk_clk set_global_assignment -name SEARCH_PATH rtl -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/conds.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/decode.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/shifter.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/and.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/orr.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/xor.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/add.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/alu.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/psr.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/file.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/regs.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/map.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/uarch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/isa.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cycles.sv + set_global_assignment -name QSYS_FILE platform.qsys set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/conspiracion.sv set_global_assignment -name QIP_FILE platform/synthesis/platform.qip set_global_assignment -name SDC_FILE conspiracion.sdc + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv index d52c0b0..c5ad62f 100644 --- a/rtl/core/cycles.sv +++ b/rtl/core/cycles.sv @@ -39,7 +39,6 @@ module core_cycles always_ff @(posedge clk) begin cycle <= next_cycle; - stall <= next_cycle != EXECUTE; flags <= next_flags; if(next_cycle == EXECUTE) begin diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv index 57744e1..508467d 100644 --- a/rtl/core/decode/decode.sv +++ b/rtl/core/decode/decode.sv @@ -59,7 +59,7 @@ module core_decode rd = 4'bxxxx; data_op = 4'bxxxx; - priority case(insn `FIELD_OP) inside + priority casez(insn `FIELD_OP) `GROUP_B: begin branch = 1; if(branch_link) begin diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv index 1b10682..e2bcc09 100644 --- a/rtl/core/regs/file.sv +++ b/rtl/core/regs/file.sv @@ -13,12 +13,19 @@ module core_reg_file // Ver comentario en uarch.sv word file[30]; + word q, wr_value_hold; + logic overwrite_hold; - always @(posedge clk) - if(wr_enable) + assign rd_value = overwrite_hold ? wr_value_hold : q; + + always @(posedge clk) begin + if(wr_enable) begin file[rd_index] <= wr_value; + wr_value_hold <= wr_value; + end - always @(posedge clk) - rd_value <= wr_enable & (rd_index == wr_index) ? wr_value : file[rd_index]; + q <= file[rd_index]; + overwrite_hold <= wr_enable & (rd_index == wr_index); + end endmodule |