diff options
Diffstat (limited to '')
| -rw-r--r-- | ip/ip_fp_add.cmp | 7 | ||||
| -rw-r--r-- | ip/ip_fp_add.qip | 18 | ||||
| -rw-r--r-- | ip/ip_fp_add.v | 18 | ||||
| -rw-r--r-- | ip/ip_fp_add/ip_fp_add_0002.vhd | 1905 | ||||
| -rw-r--r-- | ip/ip_fp_add_sim/aldec/rivierapro_setup.tcl | 2 | ||||
| -rwxr-xr-x | ip/ip_fp_add_sim/cadence/ncsim_setup.sh | 4 | ||||
| -rw-r--r-- | ip/ip_fp_add_sim/ip_fp_add.vo | 5128 | ||||
| -rw-r--r-- | ip/ip_fp_add_sim/mentor/msim_setup.tcl | 2 | ||||
| -rwxr-xr-x | ip/ip_fp_add_sim/synopsys/vcs/vcs_setup.sh | 4 | ||||
| -rwxr-xr-x | ip/ip_fp_add_sim/synopsys/vcsmx/vcsmx_setup.sh | 4 | ||||
| -rw-r--r-- | ip/ip_fp_mul.cmp | 7 | ||||
| -rw-r--r-- | ip/ip_fp_mul.qip | 24 | ||||
| -rw-r--r-- | ip/ip_fp_mul.v | 20 | ||||
| -rw-r--r-- | ip/ip_fp_mul/ip_fp_mul_0002.vhd | 634 | ||||
| -rw-r--r-- | ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl | 2 | ||||
| -rwxr-xr-x | ip/ip_fp_mul_sim/cadence/ncsim_setup.sh | 4 | ||||
| -rw-r--r-- | ip/ip_fp_mul_sim/ip_fp_mul.vo | 1792 | ||||
| -rw-r--r-- | ip/ip_fp_mul_sim/mentor/msim_setup.tcl | 2 | ||||
| -rwxr-xr-x | ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh | 4 | ||||
| -rwxr-xr-x | ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh | 4 | ||||
| -rw-r--r-- | rtl/gfx/fp_add.sv | 1 | ||||
| -rw-r--r-- | rtl/gfx/fp_mul.sv | 1 | ||||
| -rw-r--r-- | rtl/gfx/gfx.sv | 9 | ||||
| -rw-r--r-- | rtl/gfx/gfx_defs.sv | 14 |
24 files changed, 2498 insertions, 7112 deletions
diff --git a/ip/ip_fp_add.cmp b/ip/ip_fp_add.cmp index b662f1d..7881cfc 100644 --- a/ip/ip_fp_add.cmp +++ b/ip/ip_fp_add.cmp @@ -2,9 +2,10 @@ port ( clk : in std_logic := 'X'; -- clk areset : in std_logic := 'X'; -- reset - a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a - b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b - q : out std_logic_vector(31 downto 0) -- q + en : in std_logic_vector(0 downto 0) := (others => 'X'); -- en + a : in std_logic_vector(15 downto 0) := (others => 'X'); -- a + b : in std_logic_vector(15 downto 0) := (others => 'X'); -- b + q : out std_logic_vector(15 downto 0) -- q ); end component ip_fp_add; diff --git a/ip/ip_fp_add.qip b/ip/ip_fp_add.qip index 41a30c8..925ef31 100644 --- a/ip/ip_fp_add.qip +++ b/ip/ip_fp_add.qip @@ -29,20 +29,20 @@ set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COM set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "Q09NUEFSRV9mdW5jdGlvbg==::TUlO::TmFtZQ==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "Uk9PVFNfZnVuY3Rpb24=::U1FSVA==::TmFtZQ==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZGZ1bmN0aW9u::QURE::ZGVyaXZlZGZ1bmN0aW9u" -set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfZm9ybWF0::c2luZ2xl::Rm9ybWF0" -set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfZXhw::OA==::RXhwb25lbnQ=" -set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfZXhwX2Rlcml2ZWQ=::OA==::ZnBfZXhwX2Rlcml2ZWQ=" -set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MjM=::TWFudGlzc2E=" -set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MjM=::ZnBfbWFuX2Rlcml2ZWQ=" +set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfZm9ybWF0::Y3VzdG9t::Rm9ybWF0" +set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfZXhw::NQ==::RXhwb25lbnQ=" +set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfZXhwX2Rlcml2ZWQ=::NQ==::ZnBfZXhwX2Rlcml2ZWQ=" +set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MTA=::TWFudGlzc2E=" +set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MTA=::ZnBfbWFuX2Rlcml2ZWQ=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZXhwb25lbnRfd2lkdGg=::MjM=::RXhwb25lbnQgV2lkdGg=" -set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MjAw::VGFyZ2V0" +set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MTAw::VGFyZ2V0" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::Mg==::VGFyZ2V0" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "cGVyZm9ybWFuY2VfZ29hbA==::ZnJlcXVlbmN5::R29hbA==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZQ==::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyBhd2F5IGZyb20gemVybw==::TW9kZQ==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZV9kZXJpdmVk::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyB0byBldmVu::TW9kZQ==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "dXNlX3JvdW5kaW5nX21vZGU=::dHJ1ZQ==::dXNlX3JvdW5kaW5nX21vZGU=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZmFpdGhmdWxfcm91bmRpbmc=::dHJ1ZQ==::UmVsYXggcm91bmRpbmcgdG8gcm91bmQgdXAgb3IgZG93biB0byByZWR1Y2UgcmVzb3VyY2UgdXNhZ2U=" -set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "Z2VuX2VuYWJsZQ==::ZmFsc2U=::R2VuZXJhdGUgYW4gZW5hYmxlIHBvcnQ=" +set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "Z2VuX2VuYWJsZQ==::dHJ1ZQ==::R2VuZXJhdGUgYW4gZW5hYmxlIHBvcnQ=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZGl2aWRlX3R5cGU=::MA==::TWV0aG9k" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "c2VsZWN0X3NpZ25hbF9lbmFibGU=::ZmFsc2U=::VXNlIFNlbGVjdCBTaWduYWw=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "c2NhbGVfYnlfcGk=::ZmFsc2U=::UmVwcmVzZW50IGFuZ2xlIGFzIG11bHRpcGxlIG9mIFBp" @@ -53,7 +53,7 @@ set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COM set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnhwdF9mcmFjdGlvbg==::MA==::RnJhY3Rpb24=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnhwdF9zaWdu::MQ==::U2lnbg==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MA==::ZnJlcXVlbmN5X2ZlZWRiYWNr" -set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::MTM=::bGF0ZW5jeV9mZWVkYmFjaw==" +set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::NA==::bGF0ZW5jeV9mZWVkYmFjaw==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "Zm9yY2VfZWxhYm9yYXRl::MA==::Zm9yY2VfZWxhYm9yYXRl" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2Zvcm1hdA==::c2luZ2xl::T3V0cHV0IEZvcm1hdA==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cA==::OA==::T3V0cHV0IEV4cG9uZW50" @@ -69,7 +69,7 @@ set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COM set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "bWFudWFsX2RzcF9wbGFubmluZw==::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "Zm9yY2VSZWdpc3RlcnM=::MTExMQ==::Zm9yY2VSZWdpc3RlcnM=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "UkVTX0RTUF9wYXJhbQ==::MA==::TXVsdGlwbGllcw==" -set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::ODQ5::TFVUcw==" +set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::MzI1::TFVUcw==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "UkVTX01CSVRfcGFyYW0=::MA==::TWVtb3J5IEJpdHM=" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "UkVTX01CTE9DS19wYXJhbQ==::MA==::TWVtb3J5IEJsb2Nrcw==" set_global_assignment -entity "ip_fp_add_0002" -library "ip_fp_add" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==" diff --git a/ip/ip_fp_add.v b/ip/ip_fp_add.v index d004c28..456dcf7 100644 --- a/ip/ip_fp_add.v +++ b/ip/ip_fp_add.v @@ -8,14 +8,16 @@ module ip_fp_add ( input wire clk, // clk.clk input wire areset, // areset.reset - input wire [31:0] a, // a.a - input wire [31:0] b, // b.b - output wire [31:0] q // q.q + input wire [0:0] en, // en.en + input wire [15:0] a, // a.a + input wire [15:0] b, // b.b + output wire [15:0] q // q.q ); ip_fp_add_0002 ip_fp_add_inst ( .clk (clk), // clk.clk .areset (areset), // areset.reset + .en (en), // en.en .a (a), // a.a .b (b), // b.b .q (q) // q.q @@ -57,16 +59,16 @@ endmodule // Retrieval info: <generic name="TRIG_function" value="SIN" /> // Retrieval info: <generic name="COMPARE_function" value="MIN" /> // Retrieval info: <generic name="ROOTS_function" value="SQRT" /> -// Retrieval info: <generic name="fp_format" value="single" /> -// Retrieval info: <generic name="fp_exp" value="8" /> -// Retrieval info: <generic name="fp_man" value="23" /> +// Retrieval info: <generic name="fp_format" value="custom" /> +// Retrieval info: <generic name="fp_exp" value="5" /> +// Retrieval info: <generic name="fp_man" value="10" /> // Retrieval info: <generic name="exponent_width" value="23" /> -// Retrieval info: <generic name="frequency_target" value="200" /> +// Retrieval info: <generic name="frequency_target" value="100" /> // Retrieval info: <generic name="latency_target" value="2" /> // Retrieval info: <generic name="performance_goal" value="frequency" /> // Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" /> // Retrieval info: <generic name="faithful_rounding" value="true" /> -// Retrieval info: <generic name="gen_enable" value="false" /> +// Retrieval info: <generic name="gen_enable" value="true" /> // Retrieval info: <generic name="divide_type" value="0" /> // Retrieval info: <generic name="select_signal_enable" value="false" /> // Retrieval info: <generic name="scale_by_pi" value="false" /> diff --git a/ip/ip_fp_add/ip_fp_add_0002.vhd b/ip/ip_fp_add/ip_fp_add_0002.vhd index 04c71b5..f44760e 100644 --- a/ip/ip_fp_add/ip_fp_add_0002.vhd +++ b/ip/ip_fp_add/ip_fp_add_0002.vhd @@ -16,7 +16,7 @@ -- --------------------------------------------------------------------------- -- VHDL created from ip_fp_add_0002 --- VHDL created on Fri Oct 20 22:45:49 2023 +-- VHDL created on Sat Oct 21 14:33:41 2023 library IEEE; @@ -35,9 +35,10 @@ USE lpm.lpm_components.all; entity ip_fp_add_0002 is port ( - a : in std_logic_vector(31 downto 0); -- float32_m23 - b : in std_logic_vector(31 downto 0); -- float32_m23 - q : out std_logic_vector(31 downto 0); -- float32_m23 + a : in std_logic_vector(15 downto 0); -- float16_m10 + b : in std_logic_vector(15 downto 0); -- float16_m10 + en : in std_logic_vector(0 downto 0); -- ufix1 + q : out std_logic_vector(15 downto 0); -- float16_m10 clk : in std_logic; areset : in std_logic ); @@ -50,112 +51,103 @@ architecture normal of ip_fp_add_0002 is signal GND_q : STD_LOGIC_VECTOR (0 downto 0); signal VCC_q : STD_LOGIC_VECTOR (0 downto 0); - signal expFracX_uid6_fpAddTest_b : STD_LOGIC_VECTOR (30 downto 0); - signal expFracY_uid7_fpAddTest_b : STD_LOGIC_VECTOR (30 downto 0); - signal xGTEy_uid8_fpAddTest_a : STD_LOGIC_VECTOR (32 downto 0); - signal xGTEy_uid8_fpAddTest_b : STD_LOGIC_VECTOR (32 downto 0); - signal xGTEy_uid8_fpAddTest_o : STD_LOGIC_VECTOR (32 downto 0); + signal expFracX_uid6_fpAddTest_b : STD_LOGIC_VECTOR (14 downto 0); + signal expFracY_uid7_fpAddTest_b : STD_LOGIC_VECTOR (14 downto 0); + signal xGTEy_uid8_fpAddTest_a : STD_LOGIC_VECTOR (16 downto 0); + signal xGTEy_uid8_fpAddTest_b : STD_LOGIC_VECTOR (16 downto 0); + signal xGTEy_uid8_fpAddTest_o : STD_LOGIC_VECTOR (16 downto 0); signal xGTEy_uid8_fpAddTest_n : STD_LOGIC_VECTOR (0 downto 0); - signal fracY_uid9_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0); - signal expY_uid10_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0); + signal fracY_uid9_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0); + signal expY_uid10_fpAddTest_b : STD_LOGIC_VECTOR (4 downto 0); signal sigY_uid11_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0); - signal ypn_uid12_fpAddTest_q : STD_LOGIC_VECTOR (31 downto 0); + signal ypn_uid12_fpAddTest_q : STD_LOGIC_VECTOR (15 downto 0); signal aSig_uid16_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); - signal aSig_uid16_fpAddTest_q : STD_LOGIC_VECTOR (31 downto 0); + signal aSig_uid16_fpAddTest_q : STD_LOGIC_VECTOR (15 downto 0); signal bSig_uid17_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); - signal bSig_uid17_fpAddTest_q : STD_LOGIC_VECTOR (31 downto 0); - signal cstAllOWE_uid18_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0); - signal cstZeroWF_uid19_fpAddTest_q : STD_LOGIC_VECTOR (22 downto 0); - signal cstAllZWE_uid20_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0); - signal exp_aSig_uid21_fpAddTest_in : STD_LOGIC_VECTOR (30 downto 0); - signal exp_aSig_uid21_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0); - signal frac_aSig_uid22_fpAddTest_in : STD_LOGIC_VECTOR (22 downto 0); - signal frac_aSig_uid22_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0); - signal excZ_aSig_uid16_uid23_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); + signal bSig_uid17_fpAddTest_q : STD_LOGIC_VECTOR (15 downto 0); + signal cstAllOWE_uid18_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0); + signal cstZeroWF_uid19_fpAddTest_q : STD_LOGIC_VECTOR (9 downto 0); + signal cstAllZWE_uid20_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0); + signal exp_aSig_uid21_fpAddTest_in : STD_LOGIC_VECTOR (14 downto 0); + signal exp_aSig_uid21_fpAddTest_b : STD_LOGIC_VECTOR (4 downto 0); + signal frac_aSig_uid22_fpAddTest_in : STD_LOGIC_VECTOR (9 downto 0); + signal frac_aSig_uid22_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0); signal excZ_aSig_uid16_uid23_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal expXIsMax_uid24_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal expXIsMax_uid24_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsZero_uid25_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsZero_uid25_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsNotZero_uid26_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal excI_aSig_uid27_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excI_aSig_uid27_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excN_aSig_uid28_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excN_aSig_uid28_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal invExpXIsMax_uid29_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal InvExpXIsZero_uid30_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal excR_aSig_uid31_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excR_aSig_uid31_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal exp_bSig_uid35_fpAddTest_in : STD_LOGIC_VECTOR (30 downto 0); - signal exp_bSig_uid35_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0); - signal frac_bSig_uid36_fpAddTest_in : STD_LOGIC_VECTOR (22 downto 0); - signal frac_bSig_uid36_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0); - signal excZ_bSig_uid17_uid37_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); + signal exp_bSig_uid35_fpAddTest_in : STD_LOGIC_VECTOR (14 downto 0); + signal exp_bSig_uid35_fpAddTest_b : STD_LOGIC_VECTOR (4 downto 0); + signal frac_bSig_uid36_fpAddTest_in : STD_LOGIC_VECTOR (9 downto 0); + signal frac_bSig_uid36_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0); signal excZ_bSig_uid17_uid37_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal expXIsMax_uid38_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal expXIsMax_uid38_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsZero_uid39_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsZero_uid39_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsNotZero_uid40_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal excI_bSig_uid41_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excI_bSig_uid41_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excN_bSig_uid42_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excN_bSig_uid42_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal invExpXIsMax_uid43_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal InvExpXIsZero_uid44_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal excR_bSig_uid45_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excR_bSig_uid45_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal sigA_uid50_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0); signal sigB_uid51_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0); + signal effSub_uid52_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal effSub_uid52_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracBz_uid56_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); - signal fracBz_uid56_fpAddTest_q : STD_LOGIC_VECTOR (22 downto 0); - signal oFracB_uid59_fpAddTest_q : STD_LOGIC_VECTOR (23 downto 0); - signal expAmExpB_uid60_fpAddTest_a : STD_LOGIC_VECTOR (8 downto 0); - signal expAmExpB_uid60_fpAddTest_b : STD_LOGIC_VECTOR (8 downto 0); - signal expAmExpB_uid60_fpAddTest_o : STD_LOGIC_VECTOR (8 downto 0); - signal expAmExpB_uid60_fpAddTest_q : STD_LOGIC_VECTOR (8 downto 0); - signal oFracA_uid64_fpAddTest_q : STD_LOGIC_VECTOR (23 downto 0); - signal oFracAE_uid65_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal oFracBR_uid67_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal oFracBREX_uid68_fpAddTest_b : STD_LOGIC_VECTOR (26 downto 0); - signal oFracBREX_uid68_fpAddTest_qi : STD_LOGIC_VECTOR (26 downto 0); - signal oFracBREX_uid68_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal oFracBREXC2_uid69_fpAddTest_a : STD_LOGIC_VECTOR (27 downto 0); - signal oFracBREXC2_uid69_fpAddTest_b : STD_LOGIC_VECTOR (27 downto 0); - signal oFracBREXC2_uid69_fpAddTest_o : STD_LOGIC_VECTOR (27 downto 0); - signal oFracBREXC2_uid69_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0); - signal oFracBREXC2_uid70_fpAddTest_in : STD_LOGIC_VECTOR (26 downto 0); - signal oFracBREXC2_uid70_fpAddTest_b : STD_LOGIC_VECTOR (26 downto 0); - signal fracAddResult_uid72_fpAddTest_a : STD_LOGIC_VECTOR (27 downto 0); - signal fracAddResult_uid72_fpAddTest_b : STD_LOGIC_VECTOR (27 downto 0); - signal fracAddResult_uid72_fpAddTest_o : STD_LOGIC_VECTOR (27 downto 0); - signal fracAddResult_uid72_fpAddTest_q : STD_LOGIC_VECTOR (27 downto 0); - signal fracAddResultNoSignExt_uid73_fpAddTest_in : STD_LOGIC_VECTOR (26 downto 0); - signal fracAddResultNoSignExt_uid73_fpAddTest_b : STD_LOGIC_VECTOR (26 downto 0); - signal cAmA_uid76_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0); - signal aMinusA_uid77_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); + signal fracBz_uid56_fpAddTest_q : STD_LOGIC_VECTOR (9 downto 0); + signal oFracB_uid59_fpAddTest_q : STD_LOGIC_VECTOR (10 downto 0); + signal expAmExpB_uid60_fpAddTest_a : STD_LOGIC_VECTOR (5 downto 0); + signal expAmExpB_uid60_fpAddTest_b : STD_LOGIC_VECTOR (5 downto 0); + signal expAmExpB_uid60_fpAddTest_o : STD_LOGIC_VECTOR (5 downto 0); + signal expAmExpB_uid60_fpAddTest_q : STD_LOGIC_VECTOR (5 downto 0); + signal oFracA_uid64_fpAddTest_q : STD_LOGIC_VECTOR (10 downto 0); + signal oFracAE_uid65_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal oFracBR_uid67_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal oFracBREX_uid68_fpAddTest_b : STD_LOGIC_VECTOR (13 downto 0); + signal oFracBREX_uid68_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal oFracBREXC2_uid69_fpAddTest_a : STD_LOGIC_VECTOR (14 downto 0); + signal oFracBREXC2_uid69_fpAddTest_b : STD_LOGIC_VECTOR (14 downto 0); + signal oFracBREXC2_uid69_fpAddTest_o : STD_LOGIC_VECTOR (14 downto 0); + signal oFracBREXC2_uid69_fpAddTest_q : STD_LOGIC_VECTOR (14 downto 0); + signal oFracBREXC2_uid70_fpAddTest_in : STD_LOGIC_VECTOR (13 downto 0); + signal oFracBREXC2_uid70_fpAddTest_b : STD_LOGIC_VECTOR (13 downto 0); + signal fracAddResult_uid72_fpAddTest_a : STD_LOGIC_VECTOR (14 downto 0); + signal fracAddResult_uid72_fpAddTest_b : STD_LOGIC_VECTOR (14 downto 0); + signal fracAddResult_uid72_fpAddTest_o : STD_LOGIC_VECTOR (14 downto 0); + signal fracAddResult_uid72_fpAddTest_q : STD_LOGIC_VECTOR (14 downto 0); + signal fracAddResultNoSignExt_uid73_fpAddTest_in : STD_LOGIC_VECTOR (13 downto 0); + signal fracAddResultNoSignExt_uid73_fpAddTest_b : STD_LOGIC_VECTOR (13 downto 0); + signal cAmA_uid76_fpAddTest_q : STD_LOGIC_VECTOR (3 downto 0); signal aMinusA_uid77_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal expInc_uid78_fpAddTest_a : STD_LOGIC_VECTOR (8 downto 0); - signal expInc_uid78_fpAddTest_b : STD_LOGIC_VECTOR (8 downto 0); - signal expInc_uid78_fpAddTest_o : STD_LOGIC_VECTOR (8 downto 0); - signal expInc_uid78_fpAddTest_q : STD_LOGIC_VECTOR (8 downto 0); - signal expPostNorm_uid79_fpAddTest_a : STD_LOGIC_VECTOR (9 downto 0); - signal expPostNorm_uid79_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0); - signal expPostNorm_uid79_fpAddTest_o : STD_LOGIC_VECTOR (9 downto 0); - signal expPostNorm_uid79_fpAddTest_q : STD_LOGIC_VECTOR (9 downto 0); - signal fracPostNormRndRange_uid80_fpAddTest_in : STD_LOGIC_VECTOR (25 downto 0); - signal fracPostNormRndRange_uid80_fpAddTest_b : STD_LOGIC_VECTOR (23 downto 0); - signal expFracR_uid81_fpAddTest_q : STD_LOGIC_VECTOR (33 downto 0); - signal wEP2AllOwE_uid82_fpAddTest_q : STD_LOGIC_VECTOR (9 downto 0); - signal rndExp_uid83_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0); - signal rOvf_uid84_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); + signal expInc_uid78_fpAddTest_a : STD_LOGIC_VECTOR (5 downto 0); + signal expInc_uid78_fpAddTest_b : STD_LOGIC_VECTOR (5 downto 0); + signal expInc_uid78_fpAddTest_o : STD_LOGIC_VECTOR (5 downto 0); + signal expInc_uid78_fpAddTest_q : STD_LOGIC_VECTOR (5 downto 0); + signal expPostNorm_uid79_fpAddTest_a : STD_LOGIC_VECTOR (6 downto 0); + signal expPostNorm_uid79_fpAddTest_b : STD_LOGIC_VECTOR (6 downto 0); + signal expPostNorm_uid79_fpAddTest_o : STD_LOGIC_VECTOR (6 downto 0); + signal expPostNorm_uid79_fpAddTest_q : STD_LOGIC_VECTOR (6 downto 0); + signal fracPostNormRndRange_uid80_fpAddTest_in : STD_LOGIC_VECTOR (12 downto 0); + signal fracPostNormRndRange_uid80_fpAddTest_b : STD_LOGIC_VECTOR (10 downto 0); + signal expFracR_uid81_fpAddTest_q : STD_LOGIC_VECTOR (17 downto 0); + signal wEP2AllOwE_uid82_fpAddTest_q : STD_LOGIC_VECTOR (6 downto 0); + signal rndExp_uid83_fpAddTest_b : STD_LOGIC_VECTOR (6 downto 0); signal rOvf_uid84_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal rUdf_uid85_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0); - signal fracRPreExc_uid86_fpAddTest_in : STD_LOGIC_VECTOR (23 downto 0); - signal fracRPreExc_uid86_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0); - signal expRPreExc_uid87_fpAddTest_in : STD_LOGIC_VECTOR (31 downto 0); - signal expRPreExc_uid87_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0); + signal fracRPreExc_uid86_fpAddTest_in : STD_LOGIC_VECTOR (10 downto 0); + signal fracRPreExc_uid86_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0); + signal expRPreExc_uid87_fpAddTest_in : STD_LOGIC_VECTOR (15 downto 0); + signal expRPreExc_uid87_fpAddTest_b : STD_LOGIC_VECTOR (4 downto 0); signal regInputs_uid88_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excRZeroVInC_uid89_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0); signal excRZero_uid90_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); @@ -178,785 +170,498 @@ architecture normal of ip_fp_add_0002 is signal signRInfRZRReg_uid107_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal signRInfRZRReg_uid107_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal invExcRNaN_uid108_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal signRPostExc_uid109_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal signRPostExc_uid109_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal oneFracRPostExc2_uid110_fpAddTest_q : STD_LOGIC_VECTOR (22 downto 0); + signal oneFracRPostExc2_uid110_fpAddTest_q : STD_LOGIC_VECTOR (9 downto 0); signal fracRPostExc_uid113_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0); - signal fracRPostExc_uid113_fpAddTest_q : STD_LOGIC_VECTOR (22 downto 0); + signal fracRPostExc_uid113_fpAddTest_q : STD_LOGIC_VECTOR (9 downto 0); signal expRPostExc_uid117_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0); - signal expRPostExc_uid117_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0); - signal R_uid118_fpAddTest_q : STD_LOGIC_VECTOR (31 downto 0); - signal zs_uid120_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (15 downto 0); - signal rVStage_uid121_lzCountVal_uid74_fpAddTest_b : STD_LOGIC_VECTOR (15 downto 0); + signal expRPostExc_uid117_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0); + signal R_uid118_fpAddTest_q : STD_LOGIC_VECTOR (15 downto 0); + signal zs_uid120_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0); + signal rVStage_uid121_lzCountVal_uid74_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0); signal vCount_uid122_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal mO_uid123_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0); - signal vStage_uid124_lzCountVal_uid74_fpAddTest_in : STD_LOGIC_VECTOR (10 downto 0); - signal vStage_uid124_lzCountVal_uid74_fpAddTest_b : STD_LOGIC_VECTOR (10 downto 0); - signal cStage_uid125_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (15 downto 0); + signal mO_uid123_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (1 downto 0); + signal vStage_uid124_lzCountVal_uid74_fpAddTest_in : STD_LOGIC_VECTOR (5 downto 0); + signal vStage_uid124_lzCountVal_uid74_fpAddTest_b : STD_LOGIC_VECTOR (5 downto 0); + signal cStage_uid125_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0); signal vStagei_uid127_lzCountVal_uid74_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); - signal vStagei_uid127_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (15 downto 0); + signal vStagei_uid127_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0); + signal zs_uid128_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (3 downto 0); + signal vCount_uid130_lzCountVal_uid74_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal vCount_uid130_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal vStagei_uid133_lzCountVal_uid74_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); - signal vStagei_uid133_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (7 downto 0); - signal zs_uid134_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (3 downto 0); + signal vStagei_uid133_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (3 downto 0); + signal zs_uid134_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (1 downto 0); signal vCount_uid136_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); signal vStagei_uid139_lzCountVal_uid74_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); - signal vStagei_uid139_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (3 downto 0); - signal zs_uid140_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (1 downto 0); - signal vCount_uid142_lzCountVal_uid74_fpAddTest_qi : STD_LOGIC_VECTOR (0 downto 0); + signal vStagei_uid139_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (1 downto 0); + signal rVStage_uid141_lzCountVal_uid74_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0); signal vCount_uid142_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal vStagei_uid145_lzCountVal_uid74_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); - signal vStagei_uid145_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (1 downto 0); - signal rVStage_uid147_lzCountVal_uid74_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0); - signal vCount_uid148_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal r_uid149_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (4 downto 0); - signal xMSB_uid151_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0); - signal shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_a : STD_LOGIC_VECTOR (10 downto 0); - signal shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (10 downto 0); - signal shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_o : STD_LOGIC_VECTOR (10 downto 0); - signal shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_n : STD_LOGIC_VECTOR (0 downto 0); - signal seMsb_to8_uid155_in : STD_LOGIC_VECTOR (7 downto 0); - signal seMsb_to8_uid155_b : STD_LOGIC_VECTOR (7 downto 0); - signal rightShiftStage0Idx1Rng8_uid156_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (18 downto 0); - signal rightShiftStage0Idx1_uid157_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal seMsb_to16_uid158_in : STD_LOGIC_VECTOR (15 downto 0); - signal seMsb_to16_uid158_b : STD_LOGIC_VECTOR (15 downto 0); - signal rightShiftStage0Idx2Rng16_uid159_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (10 downto 0); - signal rightShiftStage0Idx2_uid160_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal seMsb_to24_uid161_in : STD_LOGIC_VECTOR (23 downto 0); - signal seMsb_to24_uid161_b : STD_LOGIC_VECTOR (23 downto 0); - signal rightShiftStage0Idx3Rng24_uid162_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (2 downto 0); - signal rightShiftStage0Idx3_uid163_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0); - signal rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal seMsb_to2_uid166_in : STD_LOGIC_VECTOR (1 downto 0); - signal seMsb_to2_uid166_b : STD_LOGIC_VECTOR (1 downto 0); - signal rightShiftStage1Idx1Rng2_uid167_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (24 downto 0); - signal rightShiftStage1Idx1_uid168_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal seMsb_to4_uid169_in : STD_LOGIC_VECTOR (3 downto 0); - signal seMsb_to4_uid169_b : STD_LOGIC_VECTOR (3 downto 0); - signal rightShiftStage1Idx2Rng4_uid170_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0); - signal rightShiftStage1Idx2_uid171_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal seMsb_to6_uid172_in : STD_LOGIC_VECTOR (5 downto 0); - signal seMsb_to6_uid172_b : STD_LOGIC_VECTOR (5 downto 0); - signal rightShiftStage1Idx3Rng6_uid173_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (20 downto 0); - signal rightShiftStage1Idx3_uid174_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0); - signal rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal rightShiftStage2Idx1Rng1_uid177_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (25 downto 0); - signal rightShiftStage2Idx1_uid178_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal rightShiftStage2_uid180_alignmentShifter_uid71_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); - signal rightShiftStage2_uid180_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal shiftOutConstant_to27_uid181_in : STD_LOGIC_VECTOR (26 downto 0); - signal shiftOutConstant_to27_uid181_b : STD_LOGIC_VECTOR (26 downto 0); - signal r_uid183_alignmentShifter_uid71_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); - signal r_uid183_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal leftShiftStage0Idx1Rng8_uid188_fracPostNorm_uid75_fpAddTest_in : STD_LOGIC_VECTOR (18 downto 0); - signal leftShiftStage0Idx1Rng8_uid188_fracPostNorm_uid75_fpAddTest_b : STD_LOGIC_VECTOR (18 downto 0); - signal leftShiftStage0Idx1_uid189_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal leftShiftStage0Idx2_uid192_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal leftShiftStage0Idx3Pad24_uid193_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (23 downto 0); - signal leftShiftStage0Idx3Rng24_uid194_fracPostNorm_uid75_fpAddTest_in : STD_LOGIC_VECTOR (2 downto 0); - signal leftShiftStage0Idx3Rng24_uid194_fracPostNorm_uid75_fpAddTest_b : STD_LOGIC_VECTOR (2 downto 0); - signal leftShiftStage0Idx3_uid195_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0); - signal leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal leftShiftStage1Idx1Rng2_uid199_fracPostNorm_uid75_fpAddTest_in : STD_LOGIC_VECTOR (24 downto 0); - signal leftShiftStage1Idx1Rng2_uid199_fracPostNorm_uid75_fpAddTest_b : STD_LOGIC_VECTOR (24 downto 0); - signal leftShiftStage1Idx1_uid200_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal leftShiftStage1Idx2Rng4_uid202_fracPostNorm_uid75_fpAddTest_in : STD_LOGIC_VECTOR (22 downto 0); - signal leftShiftStage1Idx2Rng4_uid202_fracPostNorm_uid75_fpAddTest_b : STD_LOGIC_VECTOR (22 downto 0); - signal leftShiftStage1Idx2_uid203_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal leftShiftStage1Idx3Pad6_uid204_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (5 downto 0); - signal leftShiftStage1Idx3Rng6_uid205_fracPostNorm_uid75_fpAddTest_in : STD_LOGIC_VECTOR (20 downto 0); - signal leftShiftStage1Idx3Rng6_uid205_fracPostNorm_uid75_fpAddTest_b : STD_LOGIC_VECTOR (20 downto 0); - signal leftShiftStage1Idx3_uid206_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0); - signal leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal leftShiftStage2Idx1Rng1_uid210_fracPostNorm_uid75_fpAddTest_in : STD_LOGIC_VECTOR (25 downto 0); - signal leftShiftStage2Idx1Rng1_uid210_fracPostNorm_uid75_fpAddTest_b : STD_LOGIC_VECTOR (25 downto 0); - signal leftShiftStage2Idx1_uid211_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal leftShiftStage2_uid213_fracPostNorm_uid75_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); - signal leftShiftStage2_uid213_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (26 downto 0); - signal rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_in : STD_LOGIC_VECTOR (4 downto 0); - signal rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0); - signal rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0); - signal rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_d : STD_LOGIC_VECTOR (0 downto 0); - signal rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b : STD_LOGIC_VECTOR (7 downto 0); - signal rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c : STD_LOGIC_VECTOR (7 downto 0); - signal rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b : STD_LOGIC_VECTOR (3 downto 0); - signal rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c : STD_LOGIC_VECTOR (3 downto 0); - signal rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0); - signal rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0); - signal leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0); - signal leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0); - signal leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_d : STD_LOGIC_VECTOR (0 downto 0); - signal redist0_leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_d_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist1_rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q : STD_LOGIC_VECTOR (1 downto 0); - signal redist2_rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q : STD_LOGIC_VECTOR (1 downto 0); - signal redist3_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_b_2_q : STD_LOGIC_VECTOR (1 downto 0); - signal redist4_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_c_2_q : STD_LOGIC_VECTOR (1 downto 0); - signal redist5_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_d_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist6_shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_n_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist7_xMSB_uid151_alignmentShifter_uid71_fpAddTest_b_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist8_vCount_uid136_lzCountVal_uid74_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist9_vCount_uid130_lzCountVal_uid74_fpAddTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist10_vStage_uid124_lzCountVal_uid74_fpAddTest_b_3_q : STD_LOGIC_VECTOR (10 downto 0); - signal redist11_vCount_uid122_lzCountVal_uid74_fpAddTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist12_regInputs_uid88_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist13_expRPreExc_uid87_fpAddTest_b_2_q : STD_LOGIC_VECTOR (7 downto 0); - signal redist14_fracRPreExc_uid86_fpAddTest_b_2_q : STD_LOGIC_VECTOR (22 downto 0); - signal redist15_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q : STD_LOGIC_VECTOR (26 downto 0); - signal redist16_fracAddResultNoSignExt_uid73_fpAddTest_b_4_q : STD_LOGIC_VECTOR (26 downto 0); - signal redist17_oFracBREXC2_uid70_fpAddTest_b_1_q : STD_LOGIC_VECTOR (26 downto 0); - signal redist18_effSub_uid52_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist19_effSub_uid52_fpAddTest_q_10_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist20_sigB_uid51_fpAddTest_b_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist21_sigB_uid51_fpAddTest_b_10_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist22_sigA_uid50_fpAddTest_b_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist23_sigA_uid50_fpAddTest_b_10_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist24_InvExpXIsZero_uid44_fpAddTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist25_excN_bSig_uid42_fpAddTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist26_excI_bSig_uid41_fpAddTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist27_fracXIsZero_uid39_fpAddTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist28_expXIsMax_uid38_fpAddTest_q_9_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist29_excZ_bSig_uid17_uid37_fpAddTest_q_10_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist30_frac_bSig_uid36_fpAddTest_b_1_q : STD_LOGIC_VECTOR (22 downto 0); - signal redist31_excN_aSig_uid28_fpAddTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist32_excI_aSig_uid27_fpAddTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist33_fracXIsZero_uid25_fpAddTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist34_excZ_aSig_uid16_uid23_fpAddTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist37_xIn_a_1_q : STD_LOGIC_VECTOR (31 downto 0); - signal redist38_xIn_b_1_q : STD_LOGIC_VECTOR (31 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_outputreg_q : STD_LOGIC_VECTOR (22 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_mem_reset0 : std_logic; - signal redist35_frac_aSig_uid22_fpAddTest_b_5_mem_ia : STD_LOGIC_VECTOR (22 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_mem_aa : STD_LOGIC_VECTOR (1 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_mem_ab : STD_LOGIC_VECTOR (1 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_mem_iq : STD_LOGIC_VECTOR (22 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_mem_q : STD_LOGIC_VECTOR (22 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_q : STD_LOGIC_VECTOR (1 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_i : UNSIGNED (1 downto 0); - attribute preserve : boolean; - attribute preserve of redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_i : signal is true; - signal redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_eq : std_logic; - attribute preserve of redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_eq : signal is true; - signal redist35_frac_aSig_uid22_fpAddTest_b_5_wraddr_q : STD_LOGIC_VECTOR (1 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_mem_last_q : STD_LOGIC_VECTOR (1 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_cmp_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_cmpReg_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_notEnable_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_nor_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist35_frac_aSig_uid22_fpAddTest_b_5_sticky_ena_q : STD_LOGIC_VECTOR (0 downto 0); - attribute dont_merge : boolean; - attribute dont_merge of redist35_frac_aSig_uid22_fpAddTest_b_5_sticky_ena_q : signal is true; - signal redist35_frac_aSig_uid22_fpAddTest_b_5_enaAnd_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_outputreg_q : STD_LOGIC_VECTOR (7 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_mem_reset0 : std_logic; - signal redist36_exp_aSig_uid21_fpAddTest_b_8_mem_ia : STD_LOGIC_VECTOR (7 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_mem_aa : STD_LOGIC_VECTOR (2 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_mem_ab : STD_LOGIC_VECTOR (2 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_mem_iq : STD_LOGIC_VECTOR (7 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_mem_q : STD_LOGIC_VECTOR (7 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_q : STD_LOGIC_VECTOR (2 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_i : UNSIGNED (2 downto 0); - attribute preserve of redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_i : signal is true; - signal redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_eq : std_logic; - attribute preserve of redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_eq : signal is true; - signal redist36_exp_aSig_uid21_fpAddTest_b_8_wraddr_q : STD_LOGIC_VECTOR (2 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_mem_last_q : STD_LOGIC_VECTOR (3 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_cmp_b : STD_LOGIC_VECTOR (3 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_cmp_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_cmpReg_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_notEnable_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_nor_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist36_exp_aSig_uid21_fpAddTest_b_8_sticky_ena_q : STD_LOGIC_VECTOR (0 downto 0); - attribute dont_merge of redist36_exp_aSig_uid21_fpAddTest_b_8_sticky_ena_q : signal is true; - signal redist36_exp_aSig_uid21_fpAddTest_b_8_enaAnd_q : STD_LOGIC_VECTOR (0 downto 0); + signal r_uid143_lzCountVal_uid74_fpAddTest_q : STD_LOGIC_VECTOR (3 downto 0); + signal xMSB_uid145_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (0 downto 0); + signal shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_a : STD_LOGIC_VECTOR (7 downto 0); + signal shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (7 downto 0); + signal shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_o : STD_LOGIC_VECTOR (7 downto 0); + signal shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_n : STD_LOGIC_VECTOR (0 downto 0); + signal seMsb_to4_uid149_in : STD_LOGIC_VECTOR (3 downto 0); + signal seMsb_to4_uid149_b : STD_LOGIC_VECTOR (3 downto 0); + signal rightShiftStage0Idx1Rng4_uid150_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0); + signal rightShiftStage0Idx1_uid151_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal seMsb_to8_uid152_in : STD_LOGIC_VECTOR (7 downto 0); + signal seMsb_to8_uid152_b : STD_LOGIC_VECTOR (7 downto 0); + signal rightShiftStage0Idx2Rng8_uid153_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (5 downto 0); + signal rightShiftStage0Idx2_uid154_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal seMsb_to12_uid155_in : STD_LOGIC_VECTOR (11 downto 0); + signal seMsb_to12_uid155_b : STD_LOGIC_VECTOR (11 downto 0); + signal rightShiftStage0Idx3Rng12_uid156_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (1 downto 0); + signal rightShiftStage0Idx3_uid157_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0); + signal rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal rightShiftStage1Idx1Rng1_uid160_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (12 downto 0); + signal rightShiftStage1Idx1_uid161_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal seMsb_to2_uid162_in : STD_LOGIC_VECTOR (1 downto 0); + signal seMsb_to2_uid162_b : STD_LOGIC_VECTOR (1 downto 0); + signal rightShiftStage1Idx2Rng2_uid163_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (11 downto 0); + signal rightShiftStage1Idx2_uid164_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal seMsb_to3_uid165_in : STD_LOGIC_VECTOR (2 downto 0); + signal seMsb_to3_uid165_b : STD_LOGIC_VECTOR (2 downto 0); + signal rightShiftStage1Idx3Rng3_uid166_alignmentShifter_uid71_fpAddTest_b : STD_LOGIC_VECTOR (10 downto 0); + signal rightShiftStage1Idx3_uid167_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0); + signal rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal shiftOutConstant_to14_uid170_in : STD_LOGIC_VECTOR (13 downto 0); + signal shiftOutConstant_to14_uid170_b : STD_LOGIC_VECTOR (13 downto 0); + signal r_uid172_alignmentShifter_uid71_fpAddTest_s : STD_LOGIC_VECTOR (0 downto 0); + signal r_uid172_alignmentShifter_uid71_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest_in : STD_LOGIC_VECTOR (9 downto 0); + signal leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest_b : STD_LOGIC_VECTOR (9 downto 0); + signal leftShiftStage0Idx1_uid178_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal leftShiftStage0Idx2_uid181_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal leftShiftStage0Idx3Pad12_uid182_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (11 downto 0); + signal leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest_in : STD_LOGIC_VECTOR (1 downto 0); + signal leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest_b : STD_LOGIC_VECTOR (1 downto 0); + signal leftShiftStage0Idx3_uid184_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0); + signal leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest_in : STD_LOGIC_VECTOR (12 downto 0); + signal leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest_b : STD_LOGIC_VECTOR (12 downto 0); + signal leftShiftStage1Idx1_uid189_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest_in : STD_LOGIC_VECTOR (11 downto 0); + signal leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest_b : STD_LOGIC_VECTOR (11 downto 0); + signal leftShiftStage1Idx2_uid192_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal leftShiftStage1Idx3Pad3_uid193_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (2 downto 0); + signal leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest_in : STD_LOGIC_VECTOR (10 downto 0); + signal leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest_b : STD_LOGIC_VECTOR (10 downto 0); + signal leftShiftStage1Idx3_uid195_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_s : STD_LOGIC_VECTOR (1 downto 0); + signal leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_q : STD_LOGIC_VECTOR (13 downto 0); + signal rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_in : STD_LOGIC_VECTOR (3 downto 0); + signal rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0); + signal rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0); + signal rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b : STD_LOGIC_VECTOR (3 downto 0); + signal rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c : STD_LOGIC_VECTOR (3 downto 0); + signal rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0); + signal rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0); + signal leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0); + signal leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0); + signal redist0_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q : STD_LOGIC_VECTOR (3 downto 0); + signal redist1_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q : STD_LOGIC_VECTOR (3 downto 0); + signal redist2_vStage_uid124_lzCountVal_uid74_fpAddTest_b_1_q : STD_LOGIC_VECTOR (5 downto 0); + signal redist3_vCount_uid122_lzCountVal_uid74_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist4_regInputs_uid88_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist5_expFracR_uid81_fpAddTest_q_1_q : STD_LOGIC_VECTOR (17 downto 0); + signal redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q : STD_LOGIC_VECTOR (13 downto 0); + signal redist7_effSub_uid52_fpAddTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist8_sigB_uid51_fpAddTest_b_3_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist9_sigA_uid50_fpAddTest_b_3_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist10_InvExpXIsZero_uid44_fpAddTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist11_excI_bSig_uid41_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist12_fracXIsZero_uid39_fpAddTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist13_expXIsMax_uid38_fpAddTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist14_excZ_bSig_uid17_uid37_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist16_exp_bSig_uid35_fpAddTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); + signal redist17_excI_aSig_uid27_fpAddTest_q_1_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist18_frac_aSig_uid22_fpAddTest_b_2_q : STD_LOGIC_VECTOR (9 downto 0); + signal redist19_exp_aSig_uid21_fpAddTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); + signal redist20_exp_aSig_uid21_fpAddTest_b_3_q : STD_LOGIC_VECTOR (4 downto 0); begin -- cAmA_uid76_fpAddTest(CONSTANT,75) - cAmA_uid76_fpAddTest_q <= "11011"; + cAmA_uid76_fpAddTest_q <= "1110"; -- zs_uid120_lzCountVal_uid74_fpAddTest(CONSTANT,119) - zs_uid120_lzCountVal_uid74_fpAddTest_q <= "0000000000000000"; + zs_uid120_lzCountVal_uid74_fpAddTest_q <= "00000000"; - -- redist38_xIn_b_1(DELAY,257) - redist38_xIn_b_1 : dspba_delay - GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => b, xout => redist38_xIn_b_1_q, clk => clk, aclr => areset ); + -- sigY_uid11_fpAddTest(BITSELECT,10)@0 + sigY_uid11_fpAddTest_b <= STD_LOGIC_VECTOR(b(15 downto 15)); - -- sigY_uid11_fpAddTest(BITSELECT,10)@1 - sigY_uid11_fpAddTest_b <= STD_LOGIC_VECTOR(redist38_xIn_b_1_q(31 downto 31)); + -- expY_uid10_fpAddTest(BITSELECT,9)@0 + expY_uid10_fpAddTest_b <= b(14 downto 10); - -- expY_uid10_fpAddTest(BITSELECT,9)@1 - expY_uid10_fpAddTest_b <= redist38_xIn_b_1_q(30 downto 23); + -- fracY_uid9_fpAddTest(BITSELECT,8)@0 + fracY_uid9_fpAddTest_b <= b(9 downto 0); - -- fracY_uid9_fpAddTest(BITSELECT,8)@1 - fracY_uid9_fpAddTest_b <= redist38_xIn_b_1_q(22 downto 0); - - -- ypn_uid12_fpAddTest(BITJOIN,11)@1 + -- ypn_uid12_fpAddTest(BITJOIN,11)@0 ypn_uid12_fpAddTest_q <= sigY_uid11_fpAddTest_b & expY_uid10_fpAddTest_b & fracY_uid9_fpAddTest_b; - -- redist37_xIn_a_1(DELAY,256) - redist37_xIn_a_1 : dspba_delay - GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => a, xout => redist37_xIn_a_1_q, clk => clk, aclr => areset ); - -- GND(CONSTANT,0) GND_q <= "0"; -- expFracY_uid7_fpAddTest(BITSELECT,6)@0 - expFracY_uid7_fpAddTest_b <= b(30 downto 0); + expFracY_uid7_fpAddTest_b <= b(14 downto 0); -- expFracX_uid6_fpAddTest(BITSELECT,5)@0 - expFracX_uid6_fpAddTest_b <= a(30 downto 0); + expFracX_uid6_fpAddTest_b <= a(14 downto 0); - -- xGTEy_uid8_fpAddTest(COMPARE,7)@0 + 1 + -- xGTEy_uid8_fpAddTest(COMPARE,7)@0 xGTEy_uid8_fpAddTest_a <= STD_LOGIC_VECTOR("00" & expFracX_uid6_fpAddTest_b); xGTEy_uid8_fpAddTest_b <= STD_LOGIC_VECTOR("00" & expFracY_uid7_fpAddTest_b); - xGTEy_uid8_fpAddTest_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - xGTEy_uid8_fpAddTest_o <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - xGTEy_uid8_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xGTEy_uid8_fpAddTest_a) - UNSIGNED(xGTEy_uid8_fpAddTest_b)); - END IF; - END PROCESS; - xGTEy_uid8_fpAddTest_n(0) <= not (xGTEy_uid8_fpAddTest_o(32)); + xGTEy_uid8_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xGTEy_uid8_fpAddTest_a) - UNSIGNED(xGTEy_uid8_fpAddTest_b)); + xGTEy_uid8_fpAddTest_n(0) <= not (xGTEy_uid8_fpAddTest_o(16)); - -- bSig_uid17_fpAddTest(MUX,16)@1 + -- bSig_uid17_fpAddTest(MUX,16)@0 bSig_uid17_fpAddTest_s <= xGTEy_uid8_fpAddTest_n; - bSig_uid17_fpAddTest_combproc: PROCESS (bSig_uid17_fpAddTest_s, redist37_xIn_a_1_q, ypn_uid12_fpAddTest_q) + bSig_uid17_fpAddTest_combproc: PROCESS (bSig_uid17_fpAddTest_s, en, a, ypn_uid12_fpAddTest_q) BEGIN CASE (bSig_uid17_fpAddTest_s) IS - WHEN "0" => bSig_uid17_fpAddTest_q <= redist37_xIn_a_1_q; + WHEN "0" => bSig_uid17_fpAddTest_q <= a; WHEN "1" => bSig_uid17_fpAddTest_q <= ypn_uid12_fpAddTest_q; WHEN OTHERS => bSig_uid17_fpAddTest_q <= (others => '0'); END CASE; END PROCESS; - -- sigB_uid51_fpAddTest(BITSELECT,50)@1 - sigB_uid51_fpAddTest_b <= STD_LOGIC_VECTOR(bSig_uid17_fpAddTest_q(31 downto 31)); + -- sigB_uid51_fpAddTest(BITSELECT,50)@0 + sigB_uid51_fpAddTest_b <= STD_LOGIC_VECTOR(bSig_uid17_fpAddTest_q(15 downto 15)); - -- redist20_sigB_uid51_fpAddTest_b_1(DELAY,239) - redist20_sigB_uid51_fpAddTest_b_1 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => sigB_uid51_fpAddTest_b, xout => redist20_sigB_uid51_fpAddTest_b_1_q, clk => clk, aclr => areset ); - - -- aSig_uid16_fpAddTest(MUX,15)@1 + -- aSig_uid16_fpAddTest(MUX,15)@0 aSig_uid16_fpAddTest_s <= xGTEy_uid8_fpAddTest_n; - aSig_uid16_fpAddTest_combproc: PROCESS (aSig_uid16_fpAddTest_s, ypn_uid12_fpAddTest_q, redist37_xIn_a_1_q) + aSig_uid16_fpAddTest_combproc: PROCESS (aSig_uid16_fpAddTest_s, en, ypn_uid12_fpAddTest_q, a) BEGIN CASE (aSig_uid16_fpAddTest_s) IS WHEN "0" => aSig_uid16_fpAddTest_q <= ypn_uid12_fpAddTest_q; - WHEN "1" => aSig_uid16_fpAddTest_q <= redist37_xIn_a_1_q; + WHEN "1" => aSig_uid16_fpAddTest_q <= a; WHEN OTHERS => aSig_uid16_fpAddTest_q <= (others => '0'); END CASE; END PROCESS; - -- sigA_uid50_fpAddTest(BITSELECT,49)@1 - sigA_uid50_fpAddTest_b <= STD_LOGIC_VECTOR(aSig_uid16_fpAddTest_q(31 downto 31)); - - -- redist22_sigA_uid50_fpAddTest_b_1(DELAY,241) - redist22_sigA_uid50_fpAddTest_b_1 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => sigA_uid50_fpAddTest_b, xout => redist22_sigA_uid50_fpAddTest_b_1_q, clk => clk, aclr => areset ); - - -- effSub_uid52_fpAddTest(LOGICAL,51)@2 - effSub_uid52_fpAddTest_q <= redist22_sigA_uid50_fpAddTest_b_1_q xor redist20_sigB_uid51_fpAddTest_b_1_q; + -- sigA_uid50_fpAddTest(BITSELECT,49)@0 + sigA_uid50_fpAddTest_b <= STD_LOGIC_VECTOR(aSig_uid16_fpAddTest_q(15 downto 15)); - -- redist18_effSub_uid52_fpAddTest_q_1(DELAY,237) - redist18_effSub_uid52_fpAddTest_q_1 : dspba_delay + -- effSub_uid52_fpAddTest(LOGICAL,51)@0 + 1 + effSub_uid52_fpAddTest_qi <= sigA_uid50_fpAddTest_b xor sigB_uid51_fpAddTest_b; + effSub_uid52_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => effSub_uid52_fpAddTest_q, xout => redist18_effSub_uid52_fpAddTest_q_1_q, clk => clk, aclr => areset ); + PORT MAP ( xin => effSub_uid52_fpAddTest_qi, xout => effSub_uid52_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); -- cstAllZWE_uid20_fpAddTest(CONSTANT,19) - cstAllZWE_uid20_fpAddTest_q <= "00000000"; + cstAllZWE_uid20_fpAddTest_q <= "00000"; + + -- exp_bSig_uid35_fpAddTest(BITSELECT,34)@0 + exp_bSig_uid35_fpAddTest_in <= bSig_uid17_fpAddTest_q(14 downto 0); + exp_bSig_uid35_fpAddTest_b <= exp_bSig_uid35_fpAddTest_in(14 downto 10); - -- exp_bSig_uid35_fpAddTest(BITSELECT,34)@1 - exp_bSig_uid35_fpAddTest_in <= bSig_uid17_fpAddTest_q(30 downto 0); - exp_bSig_uid35_fpAddTest_b <= exp_bSig_uid35_fpAddTest_in(30 downto 23); + -- excZ_bSig_uid17_uid37_fpAddTest(LOGICAL,36)@0 + excZ_bSig_uid17_uid37_fpAddTest_q <= "1" WHEN exp_bSig_uid35_fpAddTest_b = cstAllZWE_uid20_fpAddTest_q ELSE "0"; - -- excZ_bSig_uid17_uid37_fpAddTest(LOGICAL,36)@1 + 1 - excZ_bSig_uid17_uid37_fpAddTest_qi <= "1" WHEN exp_bSig_uid35_fpAddTest_b = cstAllZWE_uid20_fpAddTest_q ELSE "0"; - excZ_bSig_uid17_uid37_fpAddTest_delay : dspba_delay + -- redist14_excZ_bSig_uid17_uid37_fpAddTest_q_1(DELAY,216) + redist14_excZ_bSig_uid17_uid37_fpAddTest_q_1 : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excZ_bSig_uid17_uid37_fpAddTest_qi, xout => excZ_bSig_uid17_uid37_fpAddTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => excZ_bSig_uid17_uid37_fpAddTest_q, xout => redist14_excZ_bSig_uid17_uid37_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); - -- InvExpXIsZero_uid44_fpAddTest(LOGICAL,43)@2 - InvExpXIsZero_uid44_fpAddTest_q <= not (excZ_bSig_uid17_uid37_fpAddTest_q); + -- InvExpXIsZero_uid44_fpAddTest(LOGICAL,43)@1 + InvExpXIsZero_uid44_fpAddTest_q <= not (redist14_excZ_bSig_uid17_uid37_fpAddTest_q_1_q); -- cstZeroWF_uid19_fpAddTest(CONSTANT,18) - cstZeroWF_uid19_fpAddTest_q <= "00000000000000000000000"; + cstZeroWF_uid19_fpAddTest_q <= "0000000000"; - -- frac_bSig_uid36_fpAddTest(BITSELECT,35)@1 - frac_bSig_uid36_fpAddTest_in <= bSig_uid17_fpAddTest_q(22 downto 0); - frac_bSig_uid36_fpAddTest_b <= frac_bSig_uid36_fpAddTest_in(22 downto 0); + -- frac_bSig_uid36_fpAddTest(BITSELECT,35)@0 + frac_bSig_uid36_fpAddTest_in <= bSig_uid17_fpAddTest_q(9 downto 0); + frac_bSig_uid36_fpAddTest_b <= frac_bSig_uid36_fpAddTest_in(9 downto 0); - -- redist30_frac_bSig_uid36_fpAddTest_b_1(DELAY,249) - redist30_frac_bSig_uid36_fpAddTest_b_1 : dspba_delay - GENERIC MAP ( width => 23, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => frac_bSig_uid36_fpAddTest_b, xout => redist30_frac_bSig_uid36_fpAddTest_b_1_q, clk => clk, aclr => areset ); - - -- fracBz_uid56_fpAddTest(MUX,55)@2 + -- fracBz_uid56_fpAddTest(MUX,55)@0 + 1 fracBz_uid56_fpAddTest_s <= excZ_bSig_uid17_uid37_fpAddTest_q; - fracBz_uid56_fpAddTest_combproc: PROCESS (fracBz_uid56_fpAddTest_s, redist30_frac_bSig_uid36_fpAddTest_b_1_q, cstZeroWF_uid19_fpAddTest_q) + fracBz_uid56_fpAddTest_clkproc: PROCESS (clk, areset) BEGIN - CASE (fracBz_uid56_fpAddTest_s) IS - WHEN "0" => fracBz_uid56_fpAddTest_q <= redist30_frac_bSig_uid36_fpAddTest_b_1_q; - WHEN "1" => fracBz_uid56_fpAddTest_q <= cstZeroWF_uid19_fpAddTest_q; - WHEN OTHERS => fracBz_uid56_fpAddTest_q <= (others => '0'); - END CASE; + IF (areset = '1') THEN + fracBz_uid56_fpAddTest_q <= (others => '0'); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (en = "1") THEN + CASE (fracBz_uid56_fpAddTest_s) IS + WHEN "0" => fracBz_uid56_fpAddTest_q <= frac_bSig_uid36_fpAddTest_b; + WHEN "1" => fracBz_uid56_fpAddTest_q <= cstZeroWF_uid19_fpAddTest_q; + WHEN OTHERS => fracBz_uid56_fpAddTest_q <= (others => '0'); + END CASE; + END IF; + END IF; END PROCESS; - -- oFracB_uid59_fpAddTest(BITJOIN,58)@2 + -- oFracB_uid59_fpAddTest(BITJOIN,58)@1 oFracB_uid59_fpAddTest_q <= InvExpXIsZero_uid44_fpAddTest_q & fracBz_uid56_fpAddTest_q; - -- oFracBR_uid67_fpAddTest(BITJOIN,66)@2 + -- oFracBR_uid67_fpAddTest(BITJOIN,66)@1 oFracBR_uid67_fpAddTest_q <= GND_q & oFracB_uid59_fpAddTest_q & GND_q & GND_q; - -- oFracBREX_uid68_fpAddTest(LOGICAL,67)@2 + 1 - oFracBREX_uid68_fpAddTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((26 downto 1 => effSub_uid52_fpAddTest_q(0)) & effSub_uid52_fpAddTest_q)); - oFracBREX_uid68_fpAddTest_qi <= oFracBR_uid67_fpAddTest_q xor oFracBREX_uid68_fpAddTest_b; - oFracBREX_uid68_fpAddTest_delay : dspba_delay - GENERIC MAP ( width => 27, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => oFracBREX_uid68_fpAddTest_qi, xout => oFracBREX_uid68_fpAddTest_q, clk => clk, aclr => areset ); + -- oFracBREX_uid68_fpAddTest(LOGICAL,67)@1 + oFracBREX_uid68_fpAddTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 1 => effSub_uid52_fpAddTest_q(0)) & effSub_uid52_fpAddTest_q)); + oFracBREX_uid68_fpAddTest_q <= oFracBR_uid67_fpAddTest_q xor oFracBREX_uid68_fpAddTest_b; - -- oFracBREXC2_uid69_fpAddTest(ADD,68)@3 + -- oFracBREXC2_uid69_fpAddTest(ADD,68)@1 oFracBREXC2_uid69_fpAddTest_a <= STD_LOGIC_VECTOR("0" & oFracBREX_uid68_fpAddTest_q); - oFracBREXC2_uid69_fpAddTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000" & redist18_effSub_uid52_fpAddTest_q_1_q); + oFracBREXC2_uid69_fpAddTest_b <= STD_LOGIC_VECTOR("00000000000000" & effSub_uid52_fpAddTest_q); oFracBREXC2_uid69_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oFracBREXC2_uid69_fpAddTest_a) + UNSIGNED(oFracBREXC2_uid69_fpAddTest_b)); - oFracBREXC2_uid69_fpAddTest_q <= oFracBREXC2_uid69_fpAddTest_o(27 downto 0); - - -- oFracBREXC2_uid70_fpAddTest(BITSELECT,69)@3 - oFracBREXC2_uid70_fpAddTest_in <= STD_LOGIC_VECTOR(oFracBREXC2_uid69_fpAddTest_q(26 downto 0)); - oFracBREXC2_uid70_fpAddTest_b <= STD_LOGIC_VECTOR(oFracBREXC2_uid70_fpAddTest_in(26 downto 0)); - - -- redist17_oFracBREXC2_uid70_fpAddTest_b_1(DELAY,236) - redist17_oFracBREXC2_uid70_fpAddTest_b_1 : dspba_delay - GENERIC MAP ( width => 27, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => oFracBREXC2_uid70_fpAddTest_b, xout => redist17_oFracBREXC2_uid70_fpAddTest_b_1_q, clk => clk, aclr => areset ); - - -- xMSB_uid151_alignmentShifter_uid71_fpAddTest(BITSELECT,150)@4 - xMSB_uid151_alignmentShifter_uid71_fpAddTest_b <= STD_LOGIC_VECTOR(redist17_oFracBREXC2_uid70_fpAddTest_b_1_q(26 downto 26)); - - -- redist7_xMSB_uid151_alignmentShifter_uid71_fpAddTest_b_1(DELAY,226) - redist7_xMSB_uid151_alignmentShifter_uid71_fpAddTest_b_1 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => xMSB_uid151_alignmentShifter_uid71_fpAddTest_b, xout => redist7_xMSB_uid151_alignmentShifter_uid71_fpAddTest_b_1_q, clk => clk, aclr => areset ); - - -- shiftOutConstant_to27_uid181(BITSELECT,180)@5 - shiftOutConstant_to27_uid181_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((26 downto 1 => redist7_xMSB_uid151_alignmentShifter_uid71_fpAddTest_b_1_q(0)) & redist7_xMSB_uid151_alignmentShifter_uid71_fpAddTest_b_1_q)); - shiftOutConstant_to27_uid181_b <= STD_LOGIC_VECTOR(shiftOutConstant_to27_uid181_in(26 downto 0)); + oFracBREXC2_uid69_fpAddTest_q <= oFracBREXC2_uid69_fpAddTest_o(14 downto 0); - -- rightShiftStage2Idx1Rng1_uid177_alignmentShifter_uid71_fpAddTest(BITSELECT,176)@4 - rightShiftStage2Idx1Rng1_uid177_alignmentShifter_uid71_fpAddTest_b <= rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_q(26 downto 1); + -- oFracBREXC2_uid70_fpAddTest(BITSELECT,69)@1 + oFracBREXC2_uid70_fpAddTest_in <= STD_LOGIC_VECTOR(oFracBREXC2_uid69_fpAddTest_q(13 downto 0)); + oFracBREXC2_uid70_fpAddTest_b <= STD_LOGIC_VECTOR(oFracBREXC2_uid70_fpAddTest_in(13 downto 0)); - -- rightShiftStage2Idx1_uid178_alignmentShifter_uid71_fpAddTest(BITJOIN,177)@4 - rightShiftStage2Idx1_uid178_alignmentShifter_uid71_fpAddTest_q <= xMSB_uid151_alignmentShifter_uid71_fpAddTest_b & rightShiftStage2Idx1Rng1_uid177_alignmentShifter_uid71_fpAddTest_b; + -- xMSB_uid145_alignmentShifter_uid71_fpAddTest(BITSELECT,144)@1 + xMSB_uid145_alignmentShifter_uid71_fpAddTest_b <= STD_LOGIC_VECTOR(oFracBREXC2_uid70_fpAddTest_b(13 downto 13)); - -- seMsb_to6_uid172(BITSELECT,171)@4 - seMsb_to6_uid172_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((5 downto 1 => xMSB_uid151_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid151_alignmentShifter_uid71_fpAddTest_b)); - seMsb_to6_uid172_b <= STD_LOGIC_VECTOR(seMsb_to6_uid172_in(5 downto 0)); + -- shiftOutConstant_to14_uid170(BITSELECT,169)@1 + shiftOutConstant_to14_uid170_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 1 => xMSB_uid145_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid145_alignmentShifter_uid71_fpAddTest_b)); + shiftOutConstant_to14_uid170_b <= STD_LOGIC_VECTOR(shiftOutConstant_to14_uid170_in(13 downto 0)); - -- rightShiftStage1Idx3Rng6_uid173_alignmentShifter_uid71_fpAddTest(BITSELECT,172)@4 - rightShiftStage1Idx3Rng6_uid173_alignmentShifter_uid71_fpAddTest_b <= rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_q(26 downto 6); + -- seMsb_to3_uid165(BITSELECT,164)@1 + seMsb_to3_uid165_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((2 downto 1 => xMSB_uid145_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid145_alignmentShifter_uid71_fpAddTest_b)); + seMsb_to3_uid165_b <= STD_LOGIC_VECTOR(seMsb_to3_uid165_in(2 downto 0)); - -- rightShiftStage1Idx3_uid174_alignmentShifter_uid71_fpAddTest(BITJOIN,173)@4 - rightShiftStage1Idx3_uid174_alignmentShifter_uid71_fpAddTest_q <= seMsb_to6_uid172_b & rightShiftStage1Idx3Rng6_uid173_alignmentShifter_uid71_fpAddTest_b; + -- rightShiftStage1Idx3Rng3_uid166_alignmentShifter_uid71_fpAddTest(BITSELECT,165)@1 + rightShiftStage1Idx3Rng3_uid166_alignmentShifter_uid71_fpAddTest_b <= rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q(13 downto 3); - -- seMsb_to4_uid169(BITSELECT,168)@4 - seMsb_to4_uid169_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((3 downto 1 => xMSB_uid151_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid151_alignmentShifter_uid71_fpAddTest_b)); - seMsb_to4_uid169_b <= STD_LOGIC_VECTOR(seMsb_to4_uid169_in(3 downto 0)); + -- rightShiftStage1Idx3_uid167_alignmentShifter_uid71_fpAddTest(BITJOIN,166)@1 + rightShiftStage1Idx3_uid167_alignmentShifter_uid71_fpAddTest_q <= seMsb_to3_uid165_b & rightShiftStage1Idx3Rng3_uid166_alignmentShifter_uid71_fpAddTest_b; - -- rightShiftStage1Idx2Rng4_uid170_alignmentShifter_uid71_fpAddTest(BITSELECT,169)@4 - rightShiftStage1Idx2Rng4_uid170_alignmentShifter_uid71_fpAddTest_b <= rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_q(26 downto 4); + -- seMsb_to2_uid162(BITSELECT,161)@1 + seMsb_to2_uid162_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((1 downto 1 => xMSB_uid145_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid145_alignmentShifter_uid71_fpAddTest_b)); + seMsb_to2_uid162_b <= STD_LOGIC_VECTOR(seMsb_to2_uid162_in(1 downto 0)); - -- rightShiftStage1Idx2_uid171_alignmentShifter_uid71_fpAddTest(BITJOIN,170)@4 - rightShiftStage1Idx2_uid171_alignmentShifter_uid71_fpAddTest_q <= seMsb_to4_uid169_b & rightShiftStage1Idx2Rng4_uid170_alignmentShifter_uid71_fpAddTest_b; + -- rightShiftStage1Idx2Rng2_uid163_alignmentShifter_uid71_fpAddTest(BITSELECT,162)@1 + rightShiftStage1Idx2Rng2_uid163_alignmentShifter_uid71_fpAddTest_b <= rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q(13 downto 2); - -- seMsb_to2_uid166(BITSELECT,165)@4 - seMsb_to2_uid166_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((1 downto 1 => xMSB_uid151_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid151_alignmentShifter_uid71_fpAddTest_b)); - seMsb_to2_uid166_b <= STD_LOGIC_VECTOR(seMsb_to2_uid166_in(1 downto 0)); + -- rightShiftStage1Idx2_uid164_alignmentShifter_uid71_fpAddTest(BITJOIN,163)@1 + rightShiftStage1Idx2_uid164_alignmentShifter_uid71_fpAddTest_q <= seMsb_to2_uid162_b & rightShiftStage1Idx2Rng2_uid163_alignmentShifter_uid71_fpAddTest_b; - -- rightShiftStage1Idx1Rng2_uid167_alignmentShifter_uid71_fpAddTest(BITSELECT,166)@4 - rightShiftStage1Idx1Rng2_uid167_alignmentShifter_uid71_fpAddTest_b <= rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_q(26 downto 2); + -- rightShiftStage1Idx1Rng1_uid160_alignmentShifter_uid71_fpAddTest(BITSELECT,159)@1 + rightShiftStage1Idx1Rng1_uid160_alignmentShifter_uid71_fpAddTest_b <= rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q(13 downto 1); - -- rightShiftStage1Idx1_uid168_alignmentShifter_uid71_fpAddTest(BITJOIN,167)@4 - rightShiftStage1Idx1_uid168_alignmentShifter_uid71_fpAddTest_q <= seMsb_to2_uid166_b & rightShiftStage1Idx1Rng2_uid167_alignmentShifter_uid71_fpAddTest_b; + -- rightShiftStage1Idx1_uid161_alignmentShifter_uid71_fpAddTest(BITJOIN,160)@1 + rightShiftStage1Idx1_uid161_alignmentShifter_uid71_fpAddTest_q <= xMSB_uid145_alignmentShifter_uid71_fpAddTest_b & rightShiftStage1Idx1Rng1_uid160_alignmentShifter_uid71_fpAddTest_b; - -- seMsb_to24_uid161(BITSELECT,160)@4 - seMsb_to24_uid161_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((23 downto 1 => xMSB_uid151_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid151_alignmentShifter_uid71_fpAddTest_b)); - seMsb_to24_uid161_b <= STD_LOGIC_VECTOR(seMsb_to24_uid161_in(23 downto 0)); + -- seMsb_to12_uid155(BITSELECT,154)@1 + seMsb_to12_uid155_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((11 downto 1 => xMSB_uid145_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid145_alignmentShifter_uid71_fpAddTest_b)); + seMsb_to12_uid155_b <= STD_LOGIC_VECTOR(seMsb_to12_uid155_in(11 downto 0)); - -- rightShiftStage0Idx3Rng24_uid162_alignmentShifter_uid71_fpAddTest(BITSELECT,161)@4 - rightShiftStage0Idx3Rng24_uid162_alignmentShifter_uid71_fpAddTest_b <= redist17_oFracBREXC2_uid70_fpAddTest_b_1_q(26 downto 24); + -- rightShiftStage0Idx3Rng12_uid156_alignmentShifter_uid71_fpAddTest(BITSELECT,155)@1 + rightShiftStage0Idx3Rng12_uid156_alignmentShifter_uid71_fpAddTest_b <= oFracBREXC2_uid70_fpAddTest_b(13 downto 12); - -- rightShiftStage0Idx3_uid163_alignmentShifter_uid71_fpAddTest(BITJOIN,162)@4 - rightShiftStage0Idx3_uid163_alignmentShifter_uid71_fpAddTest_q <= seMsb_to24_uid161_b & rightShiftStage0Idx3Rng24_uid162_alignmentShifter_uid71_fpAddTest_b; + -- rightShiftStage0Idx3_uid157_alignmentShifter_uid71_fpAddTest(BITJOIN,156)@1 + rightShiftStage0Idx3_uid157_alignmentShifter_uid71_fpAddTest_q <= seMsb_to12_uid155_b & rightShiftStage0Idx3Rng12_uid156_alignmentShifter_uid71_fpAddTest_b; - -- seMsb_to16_uid158(BITSELECT,157)@4 - seMsb_to16_uid158_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((15 downto 1 => xMSB_uid151_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid151_alignmentShifter_uid71_fpAddTest_b)); - seMsb_to16_uid158_b <= STD_LOGIC_VECTOR(seMsb_to16_uid158_in(15 downto 0)); + -- seMsb_to8_uid152(BITSELECT,151)@1 + seMsb_to8_uid152_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((7 downto 1 => xMSB_uid145_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid145_alignmentShifter_uid71_fpAddTest_b)); + seMsb_to8_uid152_b <= STD_LOGIC_VECTOR(seMsb_to8_uid152_in(7 downto 0)); - -- rightShiftStage0Idx2Rng16_uid159_alignmentShifter_uid71_fpAddTest(BITSELECT,158)@4 - rightShiftStage0Idx2Rng16_uid159_alignmentShifter_uid71_fpAddTest_b <= redist17_oFracBREXC2_uid70_fpAddTest_b_1_q(26 downto 16); + -- rightShiftStage0Idx2Rng8_uid153_alignmentShifter_uid71_fpAddTest(BITSELECT,152)@1 + rightShiftStage0Idx2Rng8_uid153_alignmentShifter_uid71_fpAddTest_b <= oFracBREXC2_uid70_fpAddTest_b(13 downto 8); - -- rightShiftStage0Idx2_uid160_alignmentShifter_uid71_fpAddTest(BITJOIN,159)@4 - rightShiftStage0Idx2_uid160_alignmentShifter_uid71_fpAddTest_q <= seMsb_to16_uid158_b & rightShiftStage0Idx2Rng16_uid159_alignmentShifter_uid71_fpAddTest_b; + -- rightShiftStage0Idx2_uid154_alignmentShifter_uid71_fpAddTest(BITJOIN,153)@1 + rightShiftStage0Idx2_uid154_alignmentShifter_uid71_fpAddTest_q <= seMsb_to8_uid152_b & rightShiftStage0Idx2Rng8_uid153_alignmentShifter_uid71_fpAddTest_b; - -- seMsb_to8_uid155(BITSELECT,154)@4 - seMsb_to8_uid155_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((7 downto 1 => xMSB_uid151_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid151_alignmentShifter_uid71_fpAddTest_b)); - seMsb_to8_uid155_b <= STD_LOGIC_VECTOR(seMsb_to8_uid155_in(7 downto 0)); + -- seMsb_to4_uid149(BITSELECT,148)@1 + seMsb_to4_uid149_in <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((3 downto 1 => xMSB_uid145_alignmentShifter_uid71_fpAddTest_b(0)) & xMSB_uid145_alignmentShifter_uid71_fpAddTest_b)); + seMsb_to4_uid149_b <= STD_LOGIC_VECTOR(seMsb_to4_uid149_in(3 downto 0)); - -- rightShiftStage0Idx1Rng8_uid156_alignmentShifter_uid71_fpAddTest(BITSELECT,155)@4 - rightShiftStage0Idx1Rng8_uid156_alignmentShifter_uid71_fpAddTest_b <= redist17_oFracBREXC2_uid70_fpAddTest_b_1_q(26 downto 8); + -- rightShiftStage0Idx1Rng4_uid150_alignmentShifter_uid71_fpAddTest(BITSELECT,149)@1 + rightShiftStage0Idx1Rng4_uid150_alignmentShifter_uid71_fpAddTest_b <= oFracBREXC2_uid70_fpAddTest_b(13 downto 4); - -- rightShiftStage0Idx1_uid157_alignmentShifter_uid71_fpAddTest(BITJOIN,156)@4 - rightShiftStage0Idx1_uid157_alignmentShifter_uid71_fpAddTest_q <= seMsb_to8_uid155_b & rightShiftStage0Idx1Rng8_uid156_alignmentShifter_uid71_fpAddTest_b; + -- rightShiftStage0Idx1_uid151_alignmentShifter_uid71_fpAddTest(BITJOIN,150)@1 + rightShiftStage0Idx1_uid151_alignmentShifter_uid71_fpAddTest_q <= seMsb_to4_uid149_b & rightShiftStage0Idx1Rng4_uid150_alignmentShifter_uid71_fpAddTest_b; - -- exp_aSig_uid21_fpAddTest(BITSELECT,20)@1 - exp_aSig_uid21_fpAddTest_in <= aSig_uid16_fpAddTest_q(30 downto 0); - exp_aSig_uid21_fpAddTest_b <= exp_aSig_uid21_fpAddTest_in(30 downto 23); - - -- expAmExpB_uid60_fpAddTest(SUB,59)@1 + 1 - expAmExpB_uid60_fpAddTest_a <= STD_LOGIC_VECTOR("0" & exp_aSig_uid21_fpAddTest_b); - expAmExpB_uid60_fpAddTest_b <= STD_LOGIC_VECTOR("0" & exp_bSig_uid35_fpAddTest_b); - expAmExpB_uid60_fpAddTest_clkproc: PROCESS (clk, areset) + -- rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest(MUX,158)@1 + rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_s <= rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_b; + rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_combproc: PROCESS (rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_s, en, oFracBREXC2_uid70_fpAddTest_b, rightShiftStage0Idx1_uid151_alignmentShifter_uid71_fpAddTest_q, rightShiftStage0Idx2_uid154_alignmentShifter_uid71_fpAddTest_q, rightShiftStage0Idx3_uid157_alignmentShifter_uid71_fpAddTest_q) BEGIN - IF (areset = '1') THEN - expAmExpB_uid60_fpAddTest_o <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - expAmExpB_uid60_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expAmExpB_uid60_fpAddTest_a) - UNSIGNED(expAmExpB_uid60_fpAddTest_b)); - END IF; - END PROCESS; - expAmExpB_uid60_fpAddTest_q <= expAmExpB_uid60_fpAddTest_o(8 downto 0); - - -- rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select(BITSELECT,214)@2 - rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_in <= expAmExpB_uid60_fpAddTest_q(4 downto 0); - rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_b <= rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_in(4 downto 3); - rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_c <= rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_in(2 downto 1); - rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_d <= rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_in(0 downto 0); - - -- redist3_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_b_2(DELAY,222) - redist3_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_b_2 : dspba_delay - GENERIC MAP ( width => 2, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_b, xout => redist3_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_b_2_q, clk => clk, aclr => areset ); - - -- rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest(MUX,164)@4 - rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_s <= redist3_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_b_2_q; - rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_combproc: PROCESS (rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_s, redist17_oFracBREXC2_uid70_fpAddTest_b_1_q, rightShiftStage0Idx1_uid157_alignmentShifter_uid71_fpAddTest_q, rightShiftStage0Idx2_uid160_alignmentShifter_uid71_fpAddTest_q, rightShiftStage0Idx3_uid163_alignmentShifter_uid71_fpAddTest_q) - BEGIN - CASE (rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_s) IS - WHEN "00" => rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_q <= redist17_oFracBREXC2_uid70_fpAddTest_b_1_q; - WHEN "01" => rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage0Idx1_uid157_alignmentShifter_uid71_fpAddTest_q; - WHEN "10" => rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage0Idx2_uid160_alignmentShifter_uid71_fpAddTest_q; - WHEN "11" => rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage0Idx3_uid163_alignmentShifter_uid71_fpAddTest_q; - WHEN OTHERS => rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_q <= (others => '0'); + CASE (rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_s) IS + WHEN "00" => rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q <= oFracBREXC2_uid70_fpAddTest_b; + WHEN "01" => rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage0Idx1_uid151_alignmentShifter_uid71_fpAddTest_q; + WHEN "10" => rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage0Idx2_uid154_alignmentShifter_uid71_fpAddTest_q; + WHEN "11" => rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage0Idx3_uid157_alignmentShifter_uid71_fpAddTest_q; + WHEN OTHERS => rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q <= (others => '0'); END CASE; END PROCESS; - -- redist4_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_c_2(DELAY,223) - redist4_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_c_2 : dspba_delay - GENERIC MAP ( width => 2, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_c, xout => redist4_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_c_2_q, clk => clk, aclr => areset ); - - -- rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest(MUX,175)@4 - rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_s <= redist4_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_c_2_q; - rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_combproc: PROCESS (rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_s, rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_q, rightShiftStage1Idx1_uid168_alignmentShifter_uid71_fpAddTest_q, rightShiftStage1Idx2_uid171_alignmentShifter_uid71_fpAddTest_q, rightShiftStage1Idx3_uid174_alignmentShifter_uid71_fpAddTest_q) + -- redist16_exp_bSig_uid35_fpAddTest_b_1(DELAY,218) + redist16_exp_bSig_uid35_fpAddTest_b_1 : dspba_delay + GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => exp_bSig_uid35_fpAddTest_b, xout => redist16_exp_bSig_uid35_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + + -- exp_aSig_uid21_fpAddTest(BITSELECT,20)@0 + exp_aSig_uid21_fpAddTest_in <= aSig_uid16_fpAddTest_q(14 downto 0); + exp_aSig_uid21_fpAddTest_b <= exp_aSig_uid21_fpAddTest_in(14 downto 10); + + -- redist19_exp_aSig_uid21_fpAddTest_b_1(DELAY,221) + redist19_exp_aSig_uid21_fpAddTest_b_1 : dspba_delay + GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => exp_aSig_uid21_fpAddTest_b, xout => redist19_exp_aSig_uid21_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + + -- expAmExpB_uid60_fpAddTest(SUB,59)@1 + expAmExpB_uid60_fpAddTest_a <= STD_LOGIC_VECTOR("0" & redist19_exp_aSig_uid21_fpAddTest_b_1_q); + expAmExpB_uid60_fpAddTest_b <= STD_LOGIC_VECTOR("0" & redist16_exp_bSig_uid35_fpAddTest_b_1_q); + expAmExpB_uid60_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expAmExpB_uid60_fpAddTest_a) - UNSIGNED(expAmExpB_uid60_fpAddTest_b)); + expAmExpB_uid60_fpAddTest_q <= expAmExpB_uid60_fpAddTest_o(5 downto 0); + + -- rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select(BITSELECT,198)@1 + rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_in <= expAmExpB_uid60_fpAddTest_q(3 downto 0); + rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_b <= rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_in(3 downto 2); + rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_c <= rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_in(1 downto 0); + + -- rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest(MUX,168)@1 + rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_s <= rightShiftStageSel3Dto2_uid158_alignmentShifter_uid71_fpAddTest_merged_bit_select_c; + rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_combproc: PROCESS (rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_s, en, rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q, rightShiftStage1Idx1_uid161_alignmentShifter_uid71_fpAddTest_q, rightShiftStage1Idx2_uid164_alignmentShifter_uid71_fpAddTest_q, rightShiftStage1Idx3_uid167_alignmentShifter_uid71_fpAddTest_q) BEGIN - CASE (rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_s) IS - WHEN "00" => rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage0_uid165_alignmentShifter_uid71_fpAddTest_q; - WHEN "01" => rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage1Idx1_uid168_alignmentShifter_uid71_fpAddTest_q; - WHEN "10" => rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage1Idx2_uid171_alignmentShifter_uid71_fpAddTest_q; - WHEN "11" => rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage1Idx3_uid174_alignmentShifter_uid71_fpAddTest_q; - WHEN OTHERS => rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_q <= (others => '0'); + CASE (rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_s) IS + WHEN "00" => rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage0_uid159_alignmentShifter_uid71_fpAddTest_q; + WHEN "01" => rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage1Idx1_uid161_alignmentShifter_uid71_fpAddTest_q; + WHEN "10" => rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage1Idx2_uid164_alignmentShifter_uid71_fpAddTest_q; + WHEN "11" => rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage1Idx3_uid167_alignmentShifter_uid71_fpAddTest_q; + WHEN OTHERS => rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_q <= (others => '0'); END CASE; END PROCESS; - -- redist5_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_d_2(DELAY,224) - redist5_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_d_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_d, xout => redist5_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_d_2_q, clk => clk, aclr => areset ); + -- shiftedOut_uid148_alignmentShifter_uid71_fpAddTest(COMPARE,147)@1 + shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_a <= STD_LOGIC_VECTOR("00" & expAmExpB_uid60_fpAddTest_q); + shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_b <= STD_LOGIC_VECTOR("0000" & cAmA_uid76_fpAddTest_q); + shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_a) - UNSIGNED(shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_b)); + shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_n(0) <= not (shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_o(7)); - -- rightShiftStage2_uid180_alignmentShifter_uid71_fpAddTest(MUX,179)@4 + 1 - rightShiftStage2_uid180_alignmentShifter_uid71_fpAddTest_s <= redist5_rightShiftStageSel4Dto3_uid164_alignmentShifter_uid71_fpAddTest_merged_bit_select_d_2_q; - rightShiftStage2_uid180_alignmentShifter_uid71_fpAddTest_clkproc: PROCESS (clk, areset) + -- r_uid172_alignmentShifter_uid71_fpAddTest(MUX,171)@1 + 1 + r_uid172_alignmentShifter_uid71_fpAddTest_s <= shiftedOut_uid148_alignmentShifter_uid71_fpAddTest_n; + r_uid172_alignmentShifter_uid71_fpAddTest_clkproc: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN - rightShiftStage2_uid180_alignmentShifter_uid71_fpAddTest_q <= (others => '0'); + r_uid172_alignmentShifter_uid71_fpAddTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN - CASE (rightShiftStage2_uid180_alignmentShifter_uid71_fpAddTest_s) IS - WHEN "0" => rightShiftStage2_uid180_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage1_uid176_alignmentShifter_uid71_fpAddTest_q; - WHEN "1" => rightShiftStage2_uid180_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage2Idx1_uid178_alignmentShifter_uid71_fpAddTest_q; - WHEN OTHERS => rightShiftStage2_uid180_alignmentShifter_uid71_fpAddTest_q <= (others => '0'); - END CASE; - END IF; - END PROCESS; - - -- shiftedOut_uid154_alignmentShifter_uid71_fpAddTest(COMPARE,153)@2 + 1 - shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_a <= STD_LOGIC_VECTOR("00" & expAmExpB_uid60_fpAddTest_q); - shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_b <= STD_LOGIC_VECTOR("000000" & cAmA_uid76_fpAddTest_q); - shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_o <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_a) - UNSIGNED(shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_b)); - END IF; - END PROCESS; - shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_n(0) <= not (shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_o(10)); - - -- redist6_shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_n_3(DELAY,225) - redist6_shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_n_3 : dspba_delay - GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_n, xout => redist6_shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_n_3_q, clk => clk, aclr => areset ); - - -- r_uid183_alignmentShifter_uid71_fpAddTest(MUX,182)@5 + 1 - r_uid183_alignmentShifter_uid71_fpAddTest_s <= redist6_shiftedOut_uid154_alignmentShifter_uid71_fpAddTest_n_3_q; - r_uid183_alignmentShifter_uid71_fpAddTest_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - r_uid183_alignmentShifter_uid71_fpAddTest_q <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - CASE (r_uid183_alignmentShifter_uid71_fpAddTest_s) IS - WHEN "0" => r_uid183_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage2_uid180_alignmentShifter_uid71_fpAddTest_q; - WHEN "1" => r_uid183_alignmentShifter_uid71_fpAddTest_q <= shiftOutConstant_to27_uid181_b; - WHEN OTHERS => r_uid183_alignmentShifter_uid71_fpAddTest_q <= (others => '0'); - END CASE; - END IF; - END PROCESS; - - -- redist35_frac_aSig_uid22_fpAddTest_b_5_notEnable(LOGICAL,265) - redist35_frac_aSig_uid22_fpAddTest_b_5_notEnable_q <= STD_LOGIC_VECTOR(not (VCC_q)); - - -- redist35_frac_aSig_uid22_fpAddTest_b_5_nor(LOGICAL,266) - redist35_frac_aSig_uid22_fpAddTest_b_5_nor_q <= not (redist35_frac_aSig_uid22_fpAddTest_b_5_notEnable_q or redist35_frac_aSig_uid22_fpAddTest_b_5_sticky_ena_q); - - -- redist35_frac_aSig_uid22_fpAddTest_b_5_mem_last(CONSTANT,262) - redist35_frac_aSig_uid22_fpAddTest_b_5_mem_last_q <= "01"; - - -- redist35_frac_aSig_uid22_fpAddTest_b_5_cmp(LOGICAL,263) - redist35_frac_aSig_uid22_fpAddTest_b_5_cmp_q <= "1" WHEN redist35_frac_aSig_uid22_fpAddTest_b_5_mem_last_q = redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_q ELSE "0"; - - -- redist35_frac_aSig_uid22_fpAddTest_b_5_cmpReg(REG,264) - redist35_frac_aSig_uid22_fpAddTest_b_5_cmpReg_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - redist35_frac_aSig_uid22_fpAddTest_b_5_cmpReg_q <= "0"; - ELSIF (clk'EVENT AND clk = '1') THEN - redist35_frac_aSig_uid22_fpAddTest_b_5_cmpReg_q <= STD_LOGIC_VECTOR(redist35_frac_aSig_uid22_fpAddTest_b_5_cmp_q); - END IF; - END PROCESS; - - -- redist35_frac_aSig_uid22_fpAddTest_b_5_sticky_ena(REG,267) - redist35_frac_aSig_uid22_fpAddTest_b_5_sticky_ena_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - redist35_frac_aSig_uid22_fpAddTest_b_5_sticky_ena_q <= "0"; - ELSIF (clk'EVENT AND clk = '1') THEN - IF (redist35_frac_aSig_uid22_fpAddTest_b_5_nor_q = "1") THEN - redist35_frac_aSig_uid22_fpAddTest_b_5_sticky_ena_q <= STD_LOGIC_VECTOR(redist35_frac_aSig_uid22_fpAddTest_b_5_cmpReg_q); + IF (en = "1") THEN + CASE (r_uid172_alignmentShifter_uid71_fpAddTest_s) IS + WHEN "0" => r_uid172_alignmentShifter_uid71_fpAddTest_q <= rightShiftStage1_uid169_alignmentShifter_uid71_fpAddTest_q; + WHEN "1" => r_uid172_alignmentShifter_uid71_fpAddTest_q <= shiftOutConstant_to14_uid170_b; + WHEN OTHERS => r_uid172_alignmentShifter_uid71_fpAddTest_q <= (others => '0'); + END CASE; END IF; END IF; END PROCESS; - -- redist35_frac_aSig_uid22_fpAddTest_b_5_enaAnd(LOGICAL,268) - redist35_frac_aSig_uid22_fpAddTest_b_5_enaAnd_q <= redist35_frac_aSig_uid22_fpAddTest_b_5_sticky_ena_q and VCC_q; - - -- redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt(COUNTER,260) - -- low=0, high=2, step=1, init=0 - redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_i <= TO_UNSIGNED(0, 2); - redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_eq <= '0'; - ELSIF (clk'EVENT AND clk = '1') THEN - IF (redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_i = TO_UNSIGNED(1, 2)) THEN - redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_eq <= '1'; - ELSE - redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_eq <= '0'; - END IF; - IF (redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_eq = '1') THEN - redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_i <= redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_i + 2; - ELSE - redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_i <= redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_i + 1; - END IF; - END IF; - END PROCESS; - redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_i, 2))); - - -- frac_aSig_uid22_fpAddTest(BITSELECT,21)@1 - frac_aSig_uid22_fpAddTest_in <= aSig_uid16_fpAddTest_q(22 downto 0); - frac_aSig_uid22_fpAddTest_b <= frac_aSig_uid22_fpAddTest_in(22 downto 0); - - -- redist35_frac_aSig_uid22_fpAddTest_b_5_wraddr(REG,261) - redist35_frac_aSig_uid22_fpAddTest_b_5_wraddr_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - redist35_frac_aSig_uid22_fpAddTest_b_5_wraddr_q <= "10"; - ELSIF (clk'EVENT AND clk = '1') THEN - redist35_frac_aSig_uid22_fpAddTest_b_5_wraddr_q <= STD_LOGIC_VECTOR(redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_q); - END IF; - END PROCESS; + -- VCC(CONSTANT,1) + VCC_q <= "1"; - -- redist35_frac_aSig_uid22_fpAddTest_b_5_mem(DUALMEM,259) - redist35_frac_aSig_uid22_fpAddTest_b_5_mem_ia <= STD_LOGIC_VECTOR(frac_aSig_uid22_fpAddTest_b); - redist35_frac_aSig_uid22_fpAddTest_b_5_mem_aa <= redist35_frac_aSig_uid22_fpAddTest_b_5_wraddr_q; - redist35_frac_aSig_uid22_fpAddTest_b_5_mem_ab <= redist35_frac_aSig_uid22_fpAddTest_b_5_rdcnt_q; - redist35_frac_aSig_uid22_fpAddTest_b_5_mem_reset0 <= areset; - redist35_frac_aSig_uid22_fpAddTest_b_5_mem_dmem : altera_syncram - GENERIC MAP ( - ram_block_type => "MLAB", - operation_mode => "DUAL_PORT", - width_a => 23, - widthad_a => 2, - numwords_a => 3, - width_b => 23, - widthad_b => 2, - numwords_b => 3, - lpm_type => "altera_syncram", - width_byteena_a => 1, - address_reg_b => "CLOCK0", - indata_reg_b => "CLOCK0", - rdcontrol_reg_b => "CLOCK0", - byteena_reg_b => "CLOCK0", - outdata_reg_b => "CLOCK1", - outdata_aclr_b => "CLEAR1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_b => "NORMAL", - read_during_write_mode_mixed_ports => "DONT_CARE", - power_up_uninitialized => "TRUE", - intended_device_family => "Cyclone V" - ) - PORT MAP ( - clocken1 => redist35_frac_aSig_uid22_fpAddTest_b_5_enaAnd_q(0), - clocken0 => VCC_q(0), - clock0 => clk, - aclr1 => redist35_frac_aSig_uid22_fpAddTest_b_5_mem_reset0, - clock1 => clk, - address_a => redist35_frac_aSig_uid22_fpAddTest_b_5_mem_aa, - data_a => redist35_frac_aSig_uid22_fpAddTest_b_5_mem_ia, - wren_a => VCC_q(0), - address_b => redist35_frac_aSig_uid22_fpAddTest_b_5_mem_ab, - q_b => redist35_frac_aSig_uid22_fpAddTest_b_5_mem_iq - ); - redist35_frac_aSig_uid22_fpAddTest_b_5_mem_q <= redist35_frac_aSig_uid22_fpAddTest_b_5_mem_iq(22 downto 0); + -- frac_aSig_uid22_fpAddTest(BITSELECT,21)@0 + frac_aSig_uid22_fpAddTest_in <= aSig_uid16_fpAddTest_q(9 downto 0); + frac_aSig_uid22_fpAddTest_b <= frac_aSig_uid22_fpAddTest_in(9 downto 0); - -- redist35_frac_aSig_uid22_fpAddTest_b_5_outputreg(DELAY,258) - redist35_frac_aSig_uid22_fpAddTest_b_5_outputreg : dspba_delay - GENERIC MAP ( width => 23, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => redist35_frac_aSig_uid22_fpAddTest_b_5_mem_q, xout => redist35_frac_aSig_uid22_fpAddTest_b_5_outputreg_q, clk => clk, aclr => areset ); + -- redist18_frac_aSig_uid22_fpAddTest_b_2(DELAY,220) + redist18_frac_aSig_uid22_fpAddTest_b_2 : dspba_delay + GENERIC MAP ( width => 10, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => frac_aSig_uid22_fpAddTest_b, xout => redist18_frac_aSig_uid22_fpAddTest_b_2_q, ena => en(0), clk => clk, aclr => areset ); - -- oFracA_uid64_fpAddTest(BITJOIN,63)@6 - oFracA_uid64_fpAddTest_q <= VCC_q & redist35_frac_aSig_uid22_fpAddTest_b_5_outputreg_q; + -- oFracA_uid64_fpAddTest(BITJOIN,63)@2 + oFracA_uid64_fpAddTest_q <= VCC_q & redist18_frac_aSig_uid22_fpAddTest_b_2_q; - -- oFracAE_uid65_fpAddTest(BITJOIN,64)@6 + -- oFracAE_uid65_fpAddTest(BITJOIN,64)@2 oFracAE_uid65_fpAddTest_q <= GND_q & oFracA_uid64_fpAddTest_q & GND_q & GND_q; - -- fracAddResult_uid72_fpAddTest(ADD,71)@6 - fracAddResult_uid72_fpAddTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((27 downto 27 => oFracAE_uid65_fpAddTest_q(26)) & oFracAE_uid65_fpAddTest_q)); - fracAddResult_uid72_fpAddTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((27 downto 27 => r_uid183_alignmentShifter_uid71_fpAddTest_q(26)) & r_uid183_alignmentShifter_uid71_fpAddTest_q)); + -- fracAddResult_uid72_fpAddTest(ADD,71)@2 + fracAddResult_uid72_fpAddTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((14 downto 14 => oFracAE_uid65_fpAddTest_q(13)) & oFracAE_uid65_fpAddTest_q)); + fracAddResult_uid72_fpAddTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((14 downto 14 => r_uid172_alignmentShifter_uid71_fpAddTest_q(13)) & r_uid172_alignmentShifter_uid71_fpAddTest_q)); fracAddResult_uid72_fpAddTest_o <= STD_LOGIC_VECTOR(SIGNED(fracAddResult_uid72_fpAddTest_a) + SIGNED(fracAddResult_uid72_fpAddTest_b)); - fracAddResult_uid72_fpAddTest_q <= fracAddResult_uid72_fpAddTest_o(27 downto 0); + fracAddResult_uid72_fpAddTest_q <= fracAddResult_uid72_fpAddTest_o(14 downto 0); - -- fracAddResultNoSignExt_uid73_fpAddTest(BITSELECT,72)@6 - fracAddResultNoSignExt_uid73_fpAddTest_in <= fracAddResult_uid72_fpAddTest_q(26 downto 0); - fracAddResultNoSignExt_uid73_fpAddTest_b <= fracAddResultNoSignExt_uid73_fpAddTest_in(26 downto 0); + -- fracAddResultNoSignExt_uid73_fpAddTest(BITSELECT,72)@2 + fracAddResultNoSignExt_uid73_fpAddTest_in <= fracAddResult_uid72_fpAddTest_q(13 downto 0); + fracAddResultNoSignExt_uid73_fpAddTest_b <= fracAddResultNoSignExt_uid73_fpAddTest_in(13 downto 0); - -- redist15_fracAddResultNoSignExt_uid73_fpAddTest_b_1(DELAY,234) - redist15_fracAddResultNoSignExt_uid73_fpAddTest_b_1 : dspba_delay - GENERIC MAP ( width => 27, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracAddResultNoSignExt_uid73_fpAddTest_b, xout => redist15_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q, clk => clk, aclr => areset ); + -- rVStage_uid121_lzCountVal_uid74_fpAddTest(BITSELECT,120)@2 + rVStage_uid121_lzCountVal_uid74_fpAddTest_b <= fracAddResultNoSignExt_uid73_fpAddTest_b(13 downto 6); - -- rVStage_uid121_lzCountVal_uid74_fpAddTest(BITSELECT,120)@7 - rVStage_uid121_lzCountVal_uid74_fpAddTest_b <= redist15_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q(26 downto 11); - - -- vCount_uid122_lzCountVal_uid74_fpAddTest(LOGICAL,121)@7 + -- vCount_uid122_lzCountVal_uid74_fpAddTest(LOGICAL,121)@2 vCount_uid122_lzCountVal_uid74_fpAddTest_q <= "1" WHEN rVStage_uid121_lzCountVal_uid74_fpAddTest_b = zs_uid120_lzCountVal_uid74_fpAddTest_q ELSE "0"; - -- redist11_vCount_uid122_lzCountVal_uid74_fpAddTest_q_3(DELAY,230) - redist11_vCount_uid122_lzCountVal_uid74_fpAddTest_q_3 : dspba_delay - GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) - PORT MAP ( xin => vCount_uid122_lzCountVal_uid74_fpAddTest_q, xout => redist11_vCount_uid122_lzCountVal_uid74_fpAddTest_q_3_q, clk => clk, aclr => areset ); + -- redist3_vCount_uid122_lzCountVal_uid74_fpAddTest_q_1(DELAY,205) + redist3_vCount_uid122_lzCountVal_uid74_fpAddTest_q_1 : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => vCount_uid122_lzCountVal_uid74_fpAddTest_q, xout => redist3_vCount_uid122_lzCountVal_uid74_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); - -- vStage_uid124_lzCountVal_uid74_fpAddTest(BITSELECT,123)@7 - vStage_uid124_lzCountVal_uid74_fpAddTest_in <= redist15_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q(10 downto 0); - vStage_uid124_lzCountVal_uid74_fpAddTest_b <= vStage_uid124_lzCountVal_uid74_fpAddTest_in(10 downto 0); + -- zs_uid128_lzCountVal_uid74_fpAddTest(CONSTANT,127) + zs_uid128_lzCountVal_uid74_fpAddTest_q <= "0000"; + + -- vStage_uid124_lzCountVal_uid74_fpAddTest(BITSELECT,123)@2 + vStage_uid124_lzCountVal_uid74_fpAddTest_in <= fracAddResultNoSignExt_uid73_fpAddTest_b(5 downto 0); + vStage_uid124_lzCountVal_uid74_fpAddTest_b <= vStage_uid124_lzCountVal_uid74_fpAddTest_in(5 downto 0); -- mO_uid123_lzCountVal_uid74_fpAddTest(CONSTANT,122) - mO_uid123_lzCountVal_uid74_fpAddTest_q <= "11111"; + mO_uid123_lzCountVal_uid74_fpAddTest_q <= "11"; - -- cStage_uid125_lzCountVal_uid74_fpAddTest(BITJOIN,124)@7 + -- cStage_uid125_lzCountVal_uid74_fpAddTest(BITJOIN,124)@2 cStage_uid125_lzCountVal_uid74_fpAddTest_q <= vStage_uid124_lzCountVal_uid74_fpAddTest_b & mO_uid123_lzCountVal_uid74_fpAddTest_q; - -- vStagei_uid127_lzCountVal_uid74_fpAddTest(MUX,126)@7 + 1 + -- vStagei_uid127_lzCountVal_uid74_fpAddTest(MUX,126)@2 vStagei_uid127_lzCountVal_uid74_fpAddTest_s <= vCount_uid122_lzCountVal_uid74_fpAddTest_q; - vStagei_uid127_lzCountVal_uid74_fpAddTest_clkproc: PROCESS (clk, areset) + vStagei_uid127_lzCountVal_uid74_fpAddTest_combproc: PROCESS (vStagei_uid127_lzCountVal_uid74_fpAddTest_s, en, rVStage_uid121_lzCountVal_uid74_fpAddTest_b, cStage_uid125_lzCountVal_uid74_fpAddTest_q) BEGIN - IF (areset = '1') THEN - vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - CASE (vStagei_uid127_lzCountVal_uid74_fpAddTest_s) IS - WHEN "0" => vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= rVStage_uid121_lzCountVal_uid74_fpAddTest_b; - WHEN "1" => vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= cStage_uid125_lzCountVal_uid74_fpAddTest_q; - WHEN OTHERS => vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= (others => '0'); - END CASE; - END IF; + CASE (vStagei_uid127_lzCountVal_uid74_fpAddTest_s) IS + WHEN "0" => vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= rVStage_uid121_lzCountVal_uid74_fpAddTest_b; + WHEN "1" => vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= cStage_uid125_lzCountVal_uid74_fpAddTest_q; + WHEN OTHERS => vStagei_uid127_lzCountVal_uid74_fpAddTest_q <= (others => '0'); + END CASE; END PROCESS; - -- rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select(BITSELECT,215)@8 - rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b <= vStagei_uid127_lzCountVal_uid74_fpAddTest_q(15 downto 8); - rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c <= vStagei_uid127_lzCountVal_uid74_fpAddTest_q(7 downto 0); - - -- vCount_uid130_lzCountVal_uid74_fpAddTest(LOGICAL,129)@8 - vCount_uid130_lzCountVal_uid74_fpAddTest_q <= "1" WHEN rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b = cstAllZWE_uid20_fpAddTest_q ELSE "0"; + -- rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select(BITSELECT,199)@2 + rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b <= vStagei_uid127_lzCountVal_uid74_fpAddTest_q(7 downto 4); + rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c <= vStagei_uid127_lzCountVal_uid74_fpAddTest_q(3 downto 0); - -- redist9_vCount_uid130_lzCountVal_uid74_fpAddTest_q_2(DELAY,228) - redist9_vCount_uid130_lzCountVal_uid74_fpAddTest_q_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => vCount_uid130_lzCountVal_uid74_fpAddTest_q, xout => redist9_vCount_uid130_lzCountVal_uid74_fpAddTest_q_2_q, clk => clk, aclr => areset ); + -- vCount_uid130_lzCountVal_uid74_fpAddTest(LOGICAL,129)@2 + 1 + vCount_uid130_lzCountVal_uid74_fpAddTest_qi <= "1" WHEN rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b = zs_uid128_lzCountVal_uid74_fpAddTest_q ELSE "0"; + vCount_uid130_lzCountVal_uid74_fpAddTest_delay : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => vCount_uid130_lzCountVal_uid74_fpAddTest_qi, xout => vCount_uid130_lzCountVal_uid74_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); -- zs_uid134_lzCountVal_uid74_fpAddTest(CONSTANT,133) - zs_uid134_lzCountVal_uid74_fpAddTest_q <= "0000"; + zs_uid134_lzCountVal_uid74_fpAddTest_q <= "00"; + + -- redist1_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1(DELAY,203) + redist1_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1 : dspba_delay + GENERIC MAP ( width => 4, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c, xout => redist1_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q, ena => en(0), clk => clk, aclr => areset ); - -- vStagei_uid133_lzCountVal_uid74_fpAddTest(MUX,132)@8 + 1 + -- redist0_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1(DELAY,202) + redist0_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1 : dspba_delay + GENERIC MAP ( width => 4, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b, xout => redist0_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q, ena => en(0), clk => clk, aclr => areset ); + + -- vStagei_uid133_lzCountVal_uid74_fpAddTest(MUX,132)@3 vStagei_uid133_lzCountVal_uid74_fpAddTest_s <= vCount_uid130_lzCountVal_uid74_fpAddTest_q; - vStagei_uid133_lzCountVal_uid74_fpAddTest_clkproc: PROCESS (clk, areset) + vStagei_uid133_lzCountVal_uid74_fpAddTest_combproc: PROCESS (vStagei_uid133_lzCountVal_uid74_fpAddTest_s, en, redist0_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q, redist1_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q) BEGIN - IF (areset = '1') THEN - vStagei_uid133_lzCountVal_uid74_fpAddTest_q <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - CASE (vStagei_uid133_lzCountVal_uid74_fpAddTest_s) IS - WHEN "0" => vStagei_uid133_lzCountVal_uid74_fpAddTest_q <= rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b; - WHEN "1" => vStagei_uid133_lzCountVal_uid74_fpAddTest_q <= rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c; - WHEN OTHERS => vStagei_uid133_lzCountVal_uid74_fpAddTest_q <= (others => '0'); - END CASE; - END IF; + CASE (vStagei_uid133_lzCountVal_uid74_fpAddTest_s) IS + WHEN "0" => vStagei_uid133_lzCountVal_uid74_fpAddTest_q <= redist0_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q; + WHEN "1" => vStagei_uid133_lzCountVal_uid74_fpAddTest_q <= redist1_rVStage_uid129_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q; + WHEN OTHERS => vStagei_uid133_lzCountVal_uid74_fpAddTest_q <= (others => '0'); + END CASE; END PROCESS; - -- rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select(BITSELECT,216)@9 - rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b <= vStagei_uid133_lzCountVal_uid74_fpAddTest_q(7 downto 4); - rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c <= vStagei_uid133_lzCountVal_uid74_fpAddTest_q(3 downto 0); + -- rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select(BITSELECT,200)@3 + rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b <= vStagei_uid133_lzCountVal_uid74_fpAddTest_q(3 downto 2); + rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c <= vStagei_uid133_lzCountVal_uid74_fpAddTest_q(1 downto 0); - -- vCount_uid136_lzCountVal_uid74_fpAddTest(LOGICAL,135)@9 + -- vCount_uid136_lzCountVal_uid74_fpAddTest(LOGICAL,135)@3 vCount_uid136_lzCountVal_uid74_fpAddTest_q <= "1" WHEN rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b = zs_uid134_lzCountVal_uid74_fpAddTest_q ELSE "0"; - -- redist8_vCount_uid136_lzCountVal_uid74_fpAddTest_q_1(DELAY,227) - redist8_vCount_uid136_lzCountVal_uid74_fpAddTest_q_1 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => vCount_uid136_lzCountVal_uid74_fpAddTest_q, xout => redist8_vCount_uid136_lzCountVal_uid74_fpAddTest_q_1_q, clk => clk, aclr => areset ); - - -- zs_uid140_lzCountVal_uid74_fpAddTest(CONSTANT,139) - zs_uid140_lzCountVal_uid74_fpAddTest_q <= "00"; - - -- vStagei_uid139_lzCountVal_uid74_fpAddTest(MUX,138)@9 + -- vStagei_uid139_lzCountVal_uid74_fpAddTest(MUX,138)@3 vStagei_uid139_lzCountVal_uid74_fpAddTest_s <= vCount_uid136_lzCountVal_uid74_fpAddTest_q; - vStagei_uid139_lzCountVal_uid74_fpAddTest_combproc: PROCESS (vStagei_uid139_lzCountVal_uid74_fpAddTest_s, rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b, rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c) + vStagei_uid139_lzCountVal_uid74_fpAddTest_combproc: PROCESS (vStagei_uid139_lzCountVal_uid74_fpAddTest_s, en, rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b, rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_c) BEGIN CASE (vStagei_uid139_lzCountVal_uid74_fpAddTest_s) IS WHEN "0" => vStagei_uid139_lzCountVal_uid74_fpAddTest_q <= rVStage_uid135_lzCountVal_uid74_fpAddTest_merged_bit_select_b; @@ -965,552 +670,315 @@ begin END CASE; END PROCESS; - -- rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select(BITSELECT,217)@9 - rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_b <= vStagei_uid139_lzCountVal_uid74_fpAddTest_q(3 downto 2); - rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_c <= vStagei_uid139_lzCountVal_uid74_fpAddTest_q(1 downto 0); - - -- vCount_uid142_lzCountVal_uid74_fpAddTest(LOGICAL,141)@9 + 1 - vCount_uid142_lzCountVal_uid74_fpAddTest_qi <= "1" WHEN rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_b = zs_uid140_lzCountVal_uid74_fpAddTest_q ELSE "0"; - vCount_uid142_lzCountVal_uid74_fpAddTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => vCount_uid142_lzCountVal_uid74_fpAddTest_qi, xout => vCount_uid142_lzCountVal_uid74_fpAddTest_q, clk => clk, aclr => areset ); + -- rVStage_uid141_lzCountVal_uid74_fpAddTest(BITSELECT,140)@3 + rVStage_uid141_lzCountVal_uid74_fpAddTest_b <= vStagei_uid139_lzCountVal_uid74_fpAddTest_q(1 downto 1); - -- redist2_rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1(DELAY,221) - redist2_rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1 : dspba_delay - GENERIC MAP ( width => 2, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_c, xout => redist2_rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q, clk => clk, aclr => areset ); + -- vCount_uid142_lzCountVal_uid74_fpAddTest(LOGICAL,141)@3 + vCount_uid142_lzCountVal_uid74_fpAddTest_q <= "1" WHEN rVStage_uid141_lzCountVal_uid74_fpAddTest_b = GND_q ELSE "0"; - -- redist1_rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1(DELAY,220) - redist1_rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1 : dspba_delay - GENERIC MAP ( width => 2, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_b, xout => redist1_rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q, clk => clk, aclr => areset ); + -- r_uid143_lzCountVal_uid74_fpAddTest(BITJOIN,142)@3 + r_uid143_lzCountVal_uid74_fpAddTest_q <= redist3_vCount_uid122_lzCountVal_uid74_fpAddTest_q_1_q & vCount_uid130_lzCountVal_uid74_fpAddTest_q & vCount_uid136_lzCountVal_uid74_fpAddTest_q & vCount_uid142_lzCountVal_uid74_fpAddTest_q; - -- vStagei_uid145_lzCountVal_uid74_fpAddTest(MUX,144)@10 - vStagei_uid145_lzCountVal_uid74_fpAddTest_s <= vCount_uid142_lzCountVal_uid74_fpAddTest_q; - vStagei_uid145_lzCountVal_uid74_fpAddTest_combproc: PROCESS (vStagei_uid145_lzCountVal_uid74_fpAddTest_s, redist1_rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q, redist2_rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q) - BEGIN - CASE (vStagei_uid145_lzCountVal_uid74_fpAddTest_s) IS - WHEN "0" => vStagei_uid145_lzCountVal_uid74_fpAddTest_q <= redist1_rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_b_1_q; - WHEN "1" => vStagei_uid145_lzCountVal_uid74_fpAddTest_q <= redist2_rVStage_uid141_lzCountVal_uid74_fpAddTest_merged_bit_select_c_1_q; - WHEN OTHERS => vStagei_uid145_lzCountVal_uid74_fpAddTest_q <= (others => '0'); - END CASE; - END PROCESS; + -- aMinusA_uid77_fpAddTest(LOGICAL,76)@3 + aMinusA_uid77_fpAddTest_q <= "1" WHEN r_uid143_lzCountVal_uid74_fpAddTest_q = cAmA_uid76_fpAddTest_q ELSE "0"; - -- rVStage_uid147_lzCountVal_uid74_fpAddTest(BITSELECT,146)@10 - rVStage_uid147_lzCountVal_uid74_fpAddTest_b <= vStagei_uid145_lzCountVal_uid74_fpAddTest_q(1 downto 1); - - -- vCount_uid148_lzCountVal_uid74_fpAddTest(LOGICAL,147)@10 - vCount_uid148_lzCountVal_uid74_fpAddTest_q <= "1" WHEN rVStage_uid147_lzCountVal_uid74_fpAddTest_b = GND_q ELSE "0"; - - -- r_uid149_lzCountVal_uid74_fpAddTest(BITJOIN,148)@10 - r_uid149_lzCountVal_uid74_fpAddTest_q <= redist11_vCount_uid122_lzCountVal_uid74_fpAddTest_q_3_q & redist9_vCount_uid130_lzCountVal_uid74_fpAddTest_q_2_q & redist8_vCount_uid136_lzCountVal_uid74_fpAddTest_q_1_q & vCount_uid142_lzCountVal_uid74_fpAddTest_q & vCount_uid148_lzCountVal_uid74_fpAddTest_q; - - -- aMinusA_uid77_fpAddTest(LOGICAL,76)@10 + 1 - aMinusA_uid77_fpAddTest_qi <= "1" WHEN r_uid149_lzCountVal_uid74_fpAddTest_q = cAmA_uid76_fpAddTest_q ELSE "0"; - aMinusA_uid77_fpAddTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => aMinusA_uid77_fpAddTest_qi, xout => aMinusA_uid77_fpAddTest_q, clk => clk, aclr => areset ); - - -- invAMinusA_uid99_fpAddTest(LOGICAL,98)@11 + -- invAMinusA_uid99_fpAddTest(LOGICAL,98)@3 invAMinusA_uid99_fpAddTest_q <= not (aMinusA_uid77_fpAddTest_q); - -- redist23_sigA_uid50_fpAddTest_b_10(DELAY,242) - redist23_sigA_uid50_fpAddTest_b_10 : dspba_delay - GENERIC MAP ( width => 1, depth => 9, reset_kind => "ASYNC" ) - PORT MAP ( xin => redist22_sigA_uid50_fpAddTest_b_1_q, xout => redist23_sigA_uid50_fpAddTest_b_10_q, clk => clk, aclr => areset ); + -- redist9_sigA_uid50_fpAddTest_b_3(DELAY,211) + redist9_sigA_uid50_fpAddTest_b_3 : dspba_delay + GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) + PORT MAP ( xin => sigA_uid50_fpAddTest_b, xout => redist9_sigA_uid50_fpAddTest_b_3_q, ena => en(0), clk => clk, aclr => areset ); -- cstAllOWE_uid18_fpAddTest(CONSTANT,17) - cstAllOWE_uid18_fpAddTest_q <= "11111111"; + cstAllOWE_uid18_fpAddTest_q <= "11111"; -- expXIsMax_uid38_fpAddTest(LOGICAL,37)@1 + 1 - expXIsMax_uid38_fpAddTest_qi <= "1" WHEN exp_bSig_uid35_fpAddTest_b = cstAllOWE_uid18_fpAddTest_q ELSE "0"; + expXIsMax_uid38_fpAddTest_qi <= "1" WHEN redist16_exp_bSig_uid35_fpAddTest_b_1_q = cstAllOWE_uid18_fpAddTest_q ELSE "0"; expXIsMax_uid38_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expXIsMax_uid38_fpAddTest_qi, xout => expXIsMax_uid38_fpAddTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => expXIsMax_uid38_fpAddTest_qi, xout => expXIsMax_uid38_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist28_expXIsMax_uid38_fpAddTest_q_9(DELAY,247) - redist28_expXIsMax_uid38_fpAddTest_q_9 : dspba_delay - GENERIC MAP ( width => 1, depth => 8, reset_kind => "ASYNC" ) - PORT MAP ( xin => expXIsMax_uid38_fpAddTest_q, xout => redist28_expXIsMax_uid38_fpAddTest_q_9_q, clk => clk, aclr => areset ); - - -- invExpXIsMax_uid43_fpAddTest(LOGICAL,42)@10 - invExpXIsMax_uid43_fpAddTest_q <= not (redist28_expXIsMax_uid38_fpAddTest_q_9_q); - - -- redist24_InvExpXIsZero_uid44_fpAddTest_q_8(DELAY,243) - redist24_InvExpXIsZero_uid44_fpAddTest_q_8 : dspba_delay - GENERIC MAP ( width => 1, depth => 8, reset_kind => "ASYNC" ) - PORT MAP ( xin => InvExpXIsZero_uid44_fpAddTest_q, xout => redist24_InvExpXIsZero_uid44_fpAddTest_q_8_q, clk => clk, aclr => areset ); - - -- excR_bSig_uid45_fpAddTest(LOGICAL,44)@10 + 1 - excR_bSig_uid45_fpAddTest_qi <= redist24_InvExpXIsZero_uid44_fpAddTest_q_8_q and invExpXIsMax_uid43_fpAddTest_q; - excR_bSig_uid45_fpAddTest_delay : dspba_delay + -- redist13_expXIsMax_uid38_fpAddTest_q_2(DELAY,215) + redist13_expXIsMax_uid38_fpAddTest_q_2 : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excR_bSig_uid45_fpAddTest_qi, xout => excR_bSig_uid45_fpAddTest_q, clk => clk, aclr => areset ); - - -- redist36_exp_aSig_uid21_fpAddTest_b_8_notEnable(LOGICAL,276) - redist36_exp_aSig_uid21_fpAddTest_b_8_notEnable_q <= STD_LOGIC_VECTOR(not (VCC_q)); - - -- redist36_exp_aSig_uid21_fpAddTest_b_8_nor(LOGICAL,277) - redist36_exp_aSig_uid21_fpAddTest_b_8_nor_q <= not (redist36_exp_aSig_uid21_fpAddTest_b_8_notEnable_q or redist36_exp_aSig_uid21_fpAddTest_b_8_sticky_ena_q); - - -- redist36_exp_aSig_uid21_fpAddTest_b_8_mem_last(CONSTANT,273) - redist36_exp_aSig_uid21_fpAddTest_b_8_mem_last_q <= "0100"; - - -- redist36_exp_aSig_uid21_fpAddTest_b_8_cmp(LOGICAL,274) - redist36_exp_aSig_uid21_fpAddTest_b_8_cmp_b <= STD_LOGIC_VECTOR("0" & redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_q); - redist36_exp_aSig_uid21_fpAddTest_b_8_cmp_q <= "1" WHEN redist36_exp_aSig_uid21_fpAddTest_b_8_mem_last_q = redist36_exp_aSig_uid21_fpAddTest_b_8_cmp_b ELSE "0"; - - -- redist36_exp_aSig_uid21_fpAddTest_b_8_cmpReg(REG,275) - redist36_exp_aSig_uid21_fpAddTest_b_8_cmpReg_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - redist36_exp_aSig_uid21_fpAddTest_b_8_cmpReg_q <= "0"; - ELSIF (clk'EVENT AND clk = '1') THEN - redist36_exp_aSig_uid21_fpAddTest_b_8_cmpReg_q <= STD_LOGIC_VECTOR(redist36_exp_aSig_uid21_fpAddTest_b_8_cmp_q); - END IF; - END PROCESS; + PORT MAP ( xin => expXIsMax_uid38_fpAddTest_q, xout => redist13_expXIsMax_uid38_fpAddTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); - -- redist36_exp_aSig_uid21_fpAddTest_b_8_sticky_ena(REG,278) - redist36_exp_aSig_uid21_fpAddTest_b_8_sticky_ena_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - redist36_exp_aSig_uid21_fpAddTest_b_8_sticky_ena_q <= "0"; - ELSIF (clk'EVENT AND clk = '1') THEN - IF (redist36_exp_aSig_uid21_fpAddTest_b_8_nor_q = "1") THEN - redist36_exp_aSig_uid21_fpAddTest_b_8_sticky_ena_q <= STD_LOGIC_VECTOR(redist36_exp_aSig_uid21_fpAddTest_b_8_cmpReg_q); - END IF; - END IF; - END PROCESS; + -- invExpXIsMax_uid43_fpAddTest(LOGICAL,42)@3 + invExpXIsMax_uid43_fpAddTest_q <= not (redist13_expXIsMax_uid38_fpAddTest_q_2_q); - -- redist36_exp_aSig_uid21_fpAddTest_b_8_enaAnd(LOGICAL,279) - redist36_exp_aSig_uid21_fpAddTest_b_8_enaAnd_q <= redist36_exp_aSig_uid21_fpAddTest_b_8_sticky_ena_q and VCC_q; - - -- redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt(COUNTER,271) - -- low=0, high=5, step=1, init=0 - redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_i <= TO_UNSIGNED(0, 3); - redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_eq <= '0'; - ELSIF (clk'EVENT AND clk = '1') THEN - IF (redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_i = TO_UNSIGNED(4, 3)) THEN - redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_eq <= '1'; - ELSE - redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_eq <= '0'; - END IF; - IF (redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_eq = '1') THEN - redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_i <= redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_i + 3; - ELSE - redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_i <= redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_i + 1; - END IF; - END IF; - END PROCESS; - redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_i, 3))); - - -- redist36_exp_aSig_uid21_fpAddTest_b_8_wraddr(REG,272) - redist36_exp_aSig_uid21_fpAddTest_b_8_wraddr_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - redist36_exp_aSig_uid21_fpAddTest_b_8_wraddr_q <= "101"; - ELSIF (clk'EVENT AND clk = '1') THEN - redist36_exp_aSig_uid21_fpAddTest_b_8_wraddr_q <= STD_LOGIC_VECTOR(redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_q); - END IF; - END PROCESS; + -- redist10_InvExpXIsZero_uid44_fpAddTest_q_2(DELAY,212) + redist10_InvExpXIsZero_uid44_fpAddTest_q_2 : dspba_delay + GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => InvExpXIsZero_uid44_fpAddTest_q, xout => redist10_InvExpXIsZero_uid44_fpAddTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); - -- redist36_exp_aSig_uid21_fpAddTest_b_8_mem(DUALMEM,270) - redist36_exp_aSig_uid21_fpAddTest_b_8_mem_ia <= STD_LOGIC_VECTOR(exp_aSig_uid21_fpAddTest_b); - redist36_exp_aSig_uid21_fpAddTest_b_8_mem_aa <= redist36_exp_aSig_uid21_fpAddTest_b_8_wraddr_q; - redist36_exp_aSig_uid21_fpAddTest_b_8_mem_ab <= redist36_exp_aSig_uid21_fpAddTest_b_8_rdcnt_q; - redist36_exp_aSig_uid21_fpAddTest_b_8_mem_reset0 <= areset; - redist36_exp_aSig_uid21_fpAddTest_b_8_mem_dmem : altera_syncram - GENERIC MAP ( - ram_block_type => "MLAB", - operation_mode => "DUAL_PORT", - width_a => 8, - widthad_a => 3, - numwords_a => 6, - width_b => 8, - widthad_b => 3, - numwords_b => 6, - lpm_type => "altera_syncram", - width_byteena_a => 1, - address_reg_b => "CLOCK0", - indata_reg_b => "CLOCK0", - rdcontrol_reg_b => "CLOCK0", - byteena_reg_b => "CLOCK0", - outdata_reg_b => "CLOCK1", - outdata_aclr_b => "CLEAR1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_b => "NORMAL", - read_during_write_mode_mixed_ports => "DONT_CARE", - power_up_uninitialized => "TRUE", - intended_device_family => "Cyclone V" - ) - PORT MAP ( - clocken1 => redist36_exp_aSig_uid21_fpAddTest_b_8_enaAnd_q(0), - clocken0 => VCC_q(0), - clock0 => clk, - aclr1 => redist36_exp_aSig_uid21_fpAddTest_b_8_mem_reset0, - clock1 => clk, - address_a => redist36_exp_aSig_uid21_fpAddTest_b_8_mem_aa, - data_a => redist36_exp_aSig_uid21_fpAddTest_b_8_mem_ia, - wren_a => VCC_q(0), - address_b => redist36_exp_aSig_uid21_fpAddTest_b_8_mem_ab, - q_b => redist36_exp_aSig_uid21_fpAddTest_b_8_mem_iq - ); - redist36_exp_aSig_uid21_fpAddTest_b_8_mem_q <= redist36_exp_aSig_uid21_fpAddTest_b_8_mem_iq(7 downto 0); + -- excR_bSig_uid45_fpAddTest(LOGICAL,44)@3 + excR_bSig_uid45_fpAddTest_q <= redist10_InvExpXIsZero_uid44_fpAddTest_q_2_q and invExpXIsMax_uid43_fpAddTest_q; - -- redist36_exp_aSig_uid21_fpAddTest_b_8_outputreg(DELAY,269) - redist36_exp_aSig_uid21_fpAddTest_b_8_outputreg : dspba_delay - GENERIC MAP ( width => 8, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => redist36_exp_aSig_uid21_fpAddTest_b_8_mem_q, xout => redist36_exp_aSig_uid21_fpAddTest_b_8_outputreg_q, clk => clk, aclr => areset ); + -- redist20_exp_aSig_uid21_fpAddTest_b_3(DELAY,222) + redist20_exp_aSig_uid21_fpAddTest_b_3 : dspba_delay + GENERIC MAP ( width => 5, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => redist19_exp_aSig_uid21_fpAddTest_b_1_q, xout => redist20_exp_aSig_uid21_fpAddTest_b_3_q, ena => en(0), clk => clk, aclr => areset ); - -- expXIsMax_uid24_fpAddTest(LOGICAL,23)@9 + 1 - expXIsMax_uid24_fpAddTest_qi <= "1" WHEN redist36_exp_aSig_uid21_fpAddTest_b_8_outputreg_q = cstAllOWE_uid18_fpAddTest_q ELSE "0"; - expXIsMax_uid24_fpAddTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expXIsMax_uid24_fpAddTest_qi, xout => expXIsMax_uid24_fpAddTest_q, clk => clk, aclr => areset ); + -- expXIsMax_uid24_fpAddTest(LOGICAL,23)@3 + expXIsMax_uid24_fpAddTest_q <= "1" WHEN redist20_exp_aSig_uid21_fpAddTest_b_3_q = cstAllOWE_uid18_fpAddTest_q ELSE "0"; - -- invExpXIsMax_uid29_fpAddTest(LOGICAL,28)@10 + -- invExpXIsMax_uid29_fpAddTest(LOGICAL,28)@3 invExpXIsMax_uid29_fpAddTest_q <= not (expXIsMax_uid24_fpAddTest_q); - -- excZ_aSig_uid16_uid23_fpAddTest(LOGICAL,22)@9 + 1 - excZ_aSig_uid16_uid23_fpAddTest_qi <= "1" WHEN redist36_exp_aSig_uid21_fpAddTest_b_8_outputreg_q = cstAllZWE_uid20_fpAddTest_q ELSE "0"; - excZ_aSig_uid16_uid23_fpAddTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excZ_aSig_uid16_uid23_fpAddTest_qi, xout => excZ_aSig_uid16_uid23_fpAddTest_q, clk => clk, aclr => areset ); + -- excZ_aSig_uid16_uid23_fpAddTest(LOGICAL,22)@3 + excZ_aSig_uid16_uid23_fpAddTest_q <= "1" WHEN redist20_exp_aSig_uid21_fpAddTest_b_3_q = cstAllZWE_uid20_fpAddTest_q ELSE "0"; - -- InvExpXIsZero_uid30_fpAddTest(LOGICAL,29)@10 + -- InvExpXIsZero_uid30_fpAddTest(LOGICAL,29)@3 InvExpXIsZero_uid30_fpAddTest_q <= not (excZ_aSig_uid16_uid23_fpAddTest_q); - -- excR_aSig_uid31_fpAddTest(LOGICAL,30)@10 + 1 - excR_aSig_uid31_fpAddTest_qi <= InvExpXIsZero_uid30_fpAddTest_q and invExpXIsMax_uid29_fpAddTest_q; - excR_aSig_uid31_fpAddTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excR_aSig_uid31_fpAddTest_qi, xout => excR_aSig_uid31_fpAddTest_q, clk => clk, aclr => areset ); - - -- signRReg_uid100_fpAddTest(LOGICAL,99)@11 - signRReg_uid100_fpAddTest_q <= excR_aSig_uid31_fpAddTest_q and excR_bSig_uid45_fpAddTest_q and redist23_sigA_uid50_fpAddTest_b_10_q and invAMinusA_uid99_fpAddTest_q; + -- excR_aSig_uid31_fpAddTest(LOGICAL,30)@3 + excR_aSig_uid31_fpAddTest_q <= InvExpXIsZero_uid30_fpAddTest_q and invExpXIsMax_uid29_fpAddTest_q; - -- redist21_sigB_uid51_fpAddTest_b_10(DELAY,240) - redist21_sigB_uid51_fpAddTest_b_10 : dspba_delay - GENERIC MAP ( width => 1, depth => 9, reset_kind => "ASYNC" ) - PORT MAP ( xin => redist20_sigB_uid51_fpAddTest_b_1_q, xout => redist21_sigB_uid51_fpAddTest_b_10_q, clk => clk, aclr => areset ); + -- signRReg_uid100_fpAddTest(LOGICAL,99)@3 + signRReg_uid100_fpAddTest_q <= excR_aSig_uid31_fpAddTest_q and excR_bSig_uid45_fpAddTest_q and redist9_sigA_uid50_fpAddTest_b_3_q and invAMinusA_uid99_fpAddTest_q; - -- redist29_excZ_bSig_uid17_uid37_fpAddTest_q_10(DELAY,248) - redist29_excZ_bSig_uid17_uid37_fpAddTest_q_10 : dspba_delay - GENERIC MAP ( width => 1, depth => 9, reset_kind => "ASYNC" ) - PORT MAP ( xin => excZ_bSig_uid17_uid37_fpAddTest_q, xout => redist29_excZ_bSig_uid17_uid37_fpAddTest_q_10_q, clk => clk, aclr => areset ); + -- redist8_sigB_uid51_fpAddTest_b_3(DELAY,210) + redist8_sigB_uid51_fpAddTest_b_3 : dspba_delay + GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) + PORT MAP ( xin => sigB_uid51_fpAddTest_b, xout => redist8_sigB_uid51_fpAddTest_b_3_q, ena => en(0), clk => clk, aclr => areset ); - -- redist34_excZ_aSig_uid16_uid23_fpAddTest_q_2(DELAY,253) - redist34_excZ_aSig_uid16_uid23_fpAddTest_q_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excZ_aSig_uid16_uid23_fpAddTest_q, xout => redist34_excZ_aSig_uid16_uid23_fpAddTest_q_2_q, clk => clk, aclr => areset ); + -- redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3(DELAY,217) + redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3 : dspba_delay + GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => redist14_excZ_bSig_uid17_uid37_fpAddTest_q_1_q, xout => redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); - -- excAZBZSigASigB_uid104_fpAddTest(LOGICAL,103)@11 - excAZBZSigASigB_uid104_fpAddTest_q <= redist34_excZ_aSig_uid16_uid23_fpAddTest_q_2_q and redist29_excZ_bSig_uid17_uid37_fpAddTest_q_10_q and redist23_sigA_uid50_fpAddTest_b_10_q and redist21_sigB_uid51_fpAddTest_b_10_q; + -- excAZBZSigASigB_uid104_fpAddTest(LOGICAL,103)@3 + excAZBZSigASigB_uid104_fpAddTest_q <= excZ_aSig_uid16_uid23_fpAddTest_q and redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3_q and redist9_sigA_uid50_fpAddTest_b_3_q and redist8_sigB_uid51_fpAddTest_b_3_q; - -- excBZARSigA_uid105_fpAddTest(LOGICAL,104)@11 - excBZARSigA_uid105_fpAddTest_q <= redist29_excZ_bSig_uid17_uid37_fpAddTest_q_10_q and excR_aSig_uid31_fpAddTest_q and redist23_sigA_uid50_fpAddTest_b_10_q; + -- excBZARSigA_uid105_fpAddTest(LOGICAL,104)@3 + excBZARSigA_uid105_fpAddTest_q <= redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3_q and excR_aSig_uid31_fpAddTest_q and redist9_sigA_uid50_fpAddTest_b_3_q; - -- signRZero_uid106_fpAddTest(LOGICAL,105)@11 + -- signRZero_uid106_fpAddTest(LOGICAL,105)@3 signRZero_uid106_fpAddTest_q <= excBZARSigA_uid105_fpAddTest_q or excAZBZSigASigB_uid104_fpAddTest_q; - -- fracXIsZero_uid39_fpAddTest(LOGICAL,38)@2 + 1 - fracXIsZero_uid39_fpAddTest_qi <= "1" WHEN cstZeroWF_uid19_fpAddTest_q = redist30_frac_bSig_uid36_fpAddTest_b_1_q ELSE "0"; + -- fracXIsZero_uid39_fpAddTest(LOGICAL,38)@0 + 1 + fracXIsZero_uid39_fpAddTest_qi <= "1" WHEN cstZeroWF_uid19_fpAddTest_q = frac_bSig_uid36_fpAddTest_b ELSE "0"; fracXIsZero_uid39_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsZero_uid39_fpAddTest_qi, xout => fracXIsZero_uid39_fpAddTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => fracXIsZero_uid39_fpAddTest_qi, xout => fracXIsZero_uid39_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist27_fracXIsZero_uid39_fpAddTest_q_8(DELAY,246) - redist27_fracXIsZero_uid39_fpAddTest_q_8 : dspba_delay - GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsZero_uid39_fpAddTest_q, xout => redist27_fracXIsZero_uid39_fpAddTest_q_8_q, clk => clk, aclr => areset ); + -- redist12_fracXIsZero_uid39_fpAddTest_q_3(DELAY,214) + redist12_fracXIsZero_uid39_fpAddTest_q_3 : dspba_delay + GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => fracXIsZero_uid39_fpAddTest_q, xout => redist12_fracXIsZero_uid39_fpAddTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); - -- excI_bSig_uid41_fpAddTest(LOGICAL,40)@10 + 1 - excI_bSig_uid41_fpAddTest_qi <= redist28_expXIsMax_uid38_fpAddTest_q_9_q and redist27_fracXIsZero_uid39_fpAddTest_q_8_q; - excI_bSig_uid41_fpAddTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excI_bSig_uid41_fpAddTest_qi, xout => excI_bSig_uid41_fpAddTest_q, clk => clk, aclr => areset ); + -- excI_bSig_uid41_fpAddTest(LOGICAL,40)@3 + excI_bSig_uid41_fpAddTest_q <= redist13_expXIsMax_uid38_fpAddTest_q_2_q and redist12_fracXIsZero_uid39_fpAddTest_q_3_q; - -- sigBBInf_uid101_fpAddTest(LOGICAL,100)@11 - sigBBInf_uid101_fpAddTest_q <= redist21_sigB_uid51_fpAddTest_b_10_q and excI_bSig_uid41_fpAddTest_q; + -- sigBBInf_uid101_fpAddTest(LOGICAL,100)@3 + sigBBInf_uid101_fpAddTest_q <= redist8_sigB_uid51_fpAddTest_b_3_q and excI_bSig_uid41_fpAddTest_q; - -- fracXIsZero_uid25_fpAddTest(LOGICAL,24)@6 + 1 - fracXIsZero_uid25_fpAddTest_qi <= "1" WHEN cstZeroWF_uid19_fpAddTest_q = redist35_frac_aSig_uid22_fpAddTest_b_5_outputreg_q ELSE "0"; + -- fracXIsZero_uid25_fpAddTest(LOGICAL,24)@2 + 1 + fracXIsZero_uid25_fpAddTest_qi <= "1" WHEN cstZeroWF_uid19_fpAddTest_q = redist18_frac_aSig_uid22_fpAddTest_b_2_q ELSE "0"; fracXIsZero_uid25_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsZero_uid25_fpAddTest_qi, xout => fracXIsZero_uid25_fpAddTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => fracXIsZero_uid25_fpAddTest_qi, xout => fracXIsZero_uid25_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist33_fracXIsZero_uid25_fpAddTest_q_4(DELAY,252) - redist33_fracXIsZero_uid25_fpAddTest_q_4 : dspba_delay - GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsZero_uid25_fpAddTest_q, xout => redist33_fracXIsZero_uid25_fpAddTest_q_4_q, clk => clk, aclr => areset ); - - -- excI_aSig_uid27_fpAddTest(LOGICAL,26)@10 + 1 - excI_aSig_uid27_fpAddTest_qi <= expXIsMax_uid24_fpAddTest_q and redist33_fracXIsZero_uid25_fpAddTest_q_4_q; - excI_aSig_uid27_fpAddTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excI_aSig_uid27_fpAddTest_qi, xout => excI_aSig_uid27_fpAddTest_q, clk => clk, aclr => areset ); + -- excI_aSig_uid27_fpAddTest(LOGICAL,26)@3 + excI_aSig_uid27_fpAddTest_q <= expXIsMax_uid24_fpAddTest_q and fracXIsZero_uid25_fpAddTest_q; - -- sigAAInf_uid102_fpAddTest(LOGICAL,101)@11 - sigAAInf_uid102_fpAddTest_q <= redist23_sigA_uid50_fpAddTest_b_10_q and excI_aSig_uid27_fpAddTest_q; + -- sigAAInf_uid102_fpAddTest(LOGICAL,101)@3 + sigAAInf_uid102_fpAddTest_q <= redist9_sigA_uid50_fpAddTest_b_3_q and excI_aSig_uid27_fpAddTest_q; - -- signRInf_uid103_fpAddTest(LOGICAL,102)@11 + -- signRInf_uid103_fpAddTest(LOGICAL,102)@3 signRInf_uid103_fpAddTest_q <= sigAAInf_uid102_fpAddTest_q or sigBBInf_uid101_fpAddTest_q; - -- signRInfRZRReg_uid107_fpAddTest(LOGICAL,106)@11 + 1 + -- signRInfRZRReg_uid107_fpAddTest(LOGICAL,106)@3 + 1 signRInfRZRReg_uid107_fpAddTest_qi <= signRInf_uid103_fpAddTest_q or signRZero_uid106_fpAddTest_q or signRReg_uid100_fpAddTest_q; signRInfRZRReg_uid107_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => signRInfRZRReg_uid107_fpAddTest_qi, xout => signRInfRZRReg_uid107_fpAddTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => signRInfRZRReg_uid107_fpAddTest_qi, xout => signRInfRZRReg_uid107_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- fracXIsNotZero_uid40_fpAddTest(LOGICAL,39)@10 - fracXIsNotZero_uid40_fpAddTest_q <= not (redist27_fracXIsZero_uid39_fpAddTest_q_8_q); + -- fracXIsNotZero_uid40_fpAddTest(LOGICAL,39)@3 + fracXIsNotZero_uid40_fpAddTest_q <= not (redist12_fracXIsZero_uid39_fpAddTest_q_3_q); - -- excN_bSig_uid42_fpAddTest(LOGICAL,41)@10 + 1 - excN_bSig_uid42_fpAddTest_qi <= redist28_expXIsMax_uid38_fpAddTest_q_9_q and fracXIsNotZero_uid40_fpAddTest_q; + -- excN_bSig_uid42_fpAddTest(LOGICAL,41)@3 + 1 + excN_bSig_uid42_fpAddTest_qi <= redist13_expXIsMax_uid38_fpAddTest_q_2_q and fracXIsNotZero_uid40_fpAddTest_q; excN_bSig_uid42_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excN_bSig_uid42_fpAddTest_qi, xout => excN_bSig_uid42_fpAddTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => excN_bSig_uid42_fpAddTest_qi, xout => excN_bSig_uid42_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist25_excN_bSig_uid42_fpAddTest_q_2(DELAY,244) - redist25_excN_bSig_uid42_fpAddTest_q_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excN_bSig_uid42_fpAddTest_q, xout => redist25_excN_bSig_uid42_fpAddTest_q_2_q, clk => clk, aclr => areset ); - - -- fracXIsNotZero_uid26_fpAddTest(LOGICAL,25)@10 - fracXIsNotZero_uid26_fpAddTest_q <= not (redist33_fracXIsZero_uid25_fpAddTest_q_4_q); + -- fracXIsNotZero_uid26_fpAddTest(LOGICAL,25)@3 + fracXIsNotZero_uid26_fpAddTest_q <= not (fracXIsZero_uid25_fpAddTest_q); - -- excN_aSig_uid28_fpAddTest(LOGICAL,27)@10 + 1 + -- excN_aSig_uid28_fpAddTest(LOGICAL,27)@3 + 1 excN_aSig_uid28_fpAddTest_qi <= expXIsMax_uid24_fpAddTest_q and fracXIsNotZero_uid26_fpAddTest_q; excN_aSig_uid28_fpAddTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excN_aSig_uid28_fpAddTest_qi, xout => excN_aSig_uid28_fpAddTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => excN_aSig_uid28_fpAddTest_qi, xout => excN_aSig_uid28_fpAddTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist31_excN_aSig_uid28_fpAddTest_q_2(DELAY,250) - redist31_excN_aSig_uid28_fpAddTest_q_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excN_aSig_uid28_fpAddTest_q, xout => redist31_excN_aSig_uid28_fpAddTest_q_2_q, clk => clk, aclr => areset ); + -- excRNaN2_uid94_fpAddTest(LOGICAL,93)@4 + excRNaN2_uid94_fpAddTest_q <= excN_aSig_uid28_fpAddTest_q or excN_bSig_uid42_fpAddTest_q; - -- excRNaN2_uid94_fpAddTest(LOGICAL,93)@12 - excRNaN2_uid94_fpAddTest_q <= redist31_excN_aSig_uid28_fpAddTest_q_2_q or redist25_excN_bSig_uid42_fpAddTest_q_2_q; - - -- redist19_effSub_uid52_fpAddTest_q_10(DELAY,238) - redist19_effSub_uid52_fpAddTest_q_10 : dspba_delay - GENERIC MAP ( width => 1, depth => 9, reset_kind => "ASYNC" ) - PORT MAP ( xin => redist18_effSub_uid52_fpAddTest_q_1_q, xout => redist19_effSub_uid52_fpAddTest_q_10_q, clk => clk, aclr => areset ); + -- redist7_effSub_uid52_fpAddTest_q_4(DELAY,209) + redist7_effSub_uid52_fpAddTest_q_4 : dspba_delay + GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) + PORT MAP ( xin => effSub_uid52_fpAddTest_q, xout => redist7_effSub_uid52_fpAddTest_q_4_q, ena => en(0), clk => clk, aclr => areset ); - -- redist26_excI_bSig_uid41_fpAddTest_q_2(DELAY,245) - redist26_excI_bSig_uid41_fpAddTest_q_2 : dspba_delay + -- redist11_excI_bSig_uid41_fpAddTest_q_1(DELAY,213) + redist11_excI_bSig_uid41_fpAddTest_q_1 : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excI_bSig_uid41_fpAddTest_q, xout => redist26_excI_bSig_uid41_fpAddTest_q_2_q, clk => clk, aclr => areset ); + PORT MAP ( xin => excI_bSig_uid41_fpAddTest_q, xout => redist11_excI_bSig_uid41_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); - -- redist32_excI_aSig_uid27_fpAddTest_q_2(DELAY,251) - redist32_excI_aSig_uid27_fpAddTest_q_2 : dspba_delay + -- redist17_excI_aSig_uid27_fpAddTest_q_1(DELAY,219) + redist17_excI_aSig_uid27_fpAddTest_q_1 : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excI_aSig_uid27_fpAddTest_q, xout => redist32_excI_aSig_uid27_fpAddTest_q_2_q, clk => clk, aclr => areset ); + PORT MAP ( xin => excI_aSig_uid27_fpAddTest_q, xout => redist17_excI_aSig_uid27_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); - -- excAIBISub_uid95_fpAddTest(LOGICAL,94)@12 - excAIBISub_uid95_fpAddTest_q <= redist32_excI_aSig_uid27_fpAddTest_q_2_q and redist26_excI_bSig_uid41_fpAddTest_q_2_q and redist19_effSub_uid52_fpAddTest_q_10_q; + -- excAIBISub_uid95_fpAddTest(LOGICAL,94)@4 + excAIBISub_uid95_fpAddTest_q <= redist17_excI_aSig_uid27_fpAddTest_q_1_q and redist11_excI_bSig_uid41_fpAddTest_q_1_q and redist7_effSub_uid52_fpAddTest_q_4_q; - -- excRNaN_uid96_fpAddTest(LOGICAL,95)@12 + -- excRNaN_uid96_fpAddTest(LOGICAL,95)@4 excRNaN_uid96_fpAddTest_q <= excAIBISub_uid95_fpAddTest_q or excRNaN2_uid94_fpAddTest_q; - -- invExcRNaN_uid108_fpAddTest(LOGICAL,107)@12 + -- invExcRNaN_uid108_fpAddTest(LOGICAL,107)@4 invExcRNaN_uid108_fpAddTest_q <= not (excRNaN_uid96_fpAddTest_q); - -- VCC(CONSTANT,1) - VCC_q <= "1"; - - -- signRPostExc_uid109_fpAddTest(LOGICAL,108)@12 + 1 - signRPostExc_uid109_fpAddTest_qi <= invExcRNaN_uid108_fpAddTest_q and signRInfRZRReg_uid107_fpAddTest_q; - signRPostExc_uid109_fpAddTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => signRPostExc_uid109_fpAddTest_qi, xout => signRPostExc_uid109_fpAddTest_q, clk => clk, aclr => areset ); + -- signRPostExc_uid109_fpAddTest(LOGICAL,108)@4 + signRPostExc_uid109_fpAddTest_q <= invExcRNaN_uid108_fpAddTest_q and signRInfRZRReg_uid107_fpAddTest_q; - -- expInc_uid78_fpAddTest(ADD,77)@9 + 1 - expInc_uid78_fpAddTest_a <= STD_LOGIC_VECTOR("0" & redist36_exp_aSig_uid21_fpAddTest_b_8_outputreg_q); - expInc_uid78_fpAddTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q); - expInc_uid78_fpAddTest_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - expInc_uid78_fpAddTest_o <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - expInc_uid78_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expInc_uid78_fpAddTest_a) + UNSIGNED(expInc_uid78_fpAddTest_b)); - END IF; - END PROCESS; - expInc_uid78_fpAddTest_q <= expInc_uid78_fpAddTest_o(8 downto 0); + -- expInc_uid78_fpAddTest(ADD,77)@3 + expInc_uid78_fpAddTest_a <= STD_LOGIC_VECTOR("0" & redist20_exp_aSig_uid21_fpAddTest_b_3_q); + expInc_uid78_fpAddTest_b <= STD_LOGIC_VECTOR("00000" & VCC_q); + expInc_uid78_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expInc_uid78_fpAddTest_a) + UNSIGNED(expInc_uid78_fpAddTest_b)); + expInc_uid78_fpAddTest_q <= expInc_uid78_fpAddTest_o(5 downto 0); - -- expPostNorm_uid79_fpAddTest(SUB,78)@10 + 1 + -- expPostNorm_uid79_fpAddTest(SUB,78)@3 expPostNorm_uid79_fpAddTest_a <= STD_LOGIC_VECTOR("0" & expInc_uid78_fpAddTest_q); - expPostNorm_uid79_fpAddTest_b <= STD_LOGIC_VECTOR("00000" & r_uid149_lzCountVal_uid74_fpAddTest_q); - expPostNorm_uid79_fpAddTest_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - expPostNorm_uid79_fpAddTest_o <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - expPostNorm_uid79_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expPostNorm_uid79_fpAddTest_a) - UNSIGNED(expPostNorm_uid79_fpAddTest_b)); - END IF; - END PROCESS; - expPostNorm_uid79_fpAddTest_q <= expPostNorm_uid79_fpAddTest_o(9 downto 0); - - -- leftShiftStage2Idx1Rng1_uid210_fracPostNorm_uid75_fpAddTest(BITSELECT,209)@11 - leftShiftStage2Idx1Rng1_uid210_fracPostNorm_uid75_fpAddTest_in <= leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_q(25 downto 0); - leftShiftStage2Idx1Rng1_uid210_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage2Idx1Rng1_uid210_fracPostNorm_uid75_fpAddTest_in(25 downto 0); - - -- leftShiftStage2Idx1_uid211_fracPostNorm_uid75_fpAddTest(BITJOIN,210)@11 - leftShiftStage2Idx1_uid211_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage2Idx1Rng1_uid210_fracPostNorm_uid75_fpAddTest_b & GND_q; + expPostNorm_uid79_fpAddTest_b <= STD_LOGIC_VECTOR("000" & r_uid143_lzCountVal_uid74_fpAddTest_q); + expPostNorm_uid79_fpAddTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expPostNorm_uid79_fpAddTest_a) - UNSIGNED(expPostNorm_uid79_fpAddTest_b)); + expPostNorm_uid79_fpAddTest_q <= expPostNorm_uid79_fpAddTest_o(6 downto 0); - -- leftShiftStage1Idx3Rng6_uid205_fracPostNorm_uid75_fpAddTest(BITSELECT,204)@10 - leftShiftStage1Idx3Rng6_uid205_fracPostNorm_uid75_fpAddTest_in <= leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_q(20 downto 0); - leftShiftStage1Idx3Rng6_uid205_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage1Idx3Rng6_uid205_fracPostNorm_uid75_fpAddTest_in(20 downto 0); + -- leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest(BITSELECT,193)@3 + leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest_in <= leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q(10 downto 0); + leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest_in(10 downto 0); - -- leftShiftStage1Idx3Pad6_uid204_fracPostNorm_uid75_fpAddTest(CONSTANT,203) - leftShiftStage1Idx3Pad6_uid204_fracPostNorm_uid75_fpAddTest_q <= "000000"; + -- leftShiftStage1Idx3Pad3_uid193_fracPostNorm_uid75_fpAddTest(CONSTANT,192) + leftShiftStage1Idx3Pad3_uid193_fracPostNorm_uid75_fpAddTest_q <= "000"; - -- leftShiftStage1Idx3_uid206_fracPostNorm_uid75_fpAddTest(BITJOIN,205)@10 - leftShiftStage1Idx3_uid206_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx3Rng6_uid205_fracPostNorm_uid75_fpAddTest_b & leftShiftStage1Idx3Pad6_uid204_fracPostNorm_uid75_fpAddTest_q; + -- leftShiftStage1Idx3_uid195_fracPostNorm_uid75_fpAddTest(BITJOIN,194)@3 + leftShiftStage1Idx3_uid195_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx3Rng3_uid194_fracPostNorm_uid75_fpAddTest_b & leftShiftStage1Idx3Pad3_uid193_fracPostNorm_uid75_fpAddTest_q; - -- leftShiftStage1Idx2Rng4_uid202_fracPostNorm_uid75_fpAddTest(BITSELECT,201)@10 - leftShiftStage1Idx2Rng4_uid202_fracPostNorm_uid75_fpAddTest_in <= leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_q(22 downto 0); - leftShiftStage1Idx2Rng4_uid202_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage1Idx2Rng4_uid202_fracPostNorm_uid75_fpAddTest_in(22 downto 0); + -- leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest(BITSELECT,190)@3 + leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest_in <= leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q(11 downto 0); + leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest_in(11 downto 0); - -- leftShiftStage1Idx2_uid203_fracPostNorm_uid75_fpAddTest(BITJOIN,202)@10 - leftShiftStage1Idx2_uid203_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx2Rng4_uid202_fracPostNorm_uid75_fpAddTest_b & zs_uid134_lzCountVal_uid74_fpAddTest_q; + -- leftShiftStage1Idx2_uid192_fracPostNorm_uid75_fpAddTest(BITJOIN,191)@3 + leftShiftStage1Idx2_uid192_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx2Rng2_uid191_fracPostNorm_uid75_fpAddTest_b & zs_uid134_lzCountVal_uid74_fpAddTest_q; - -- leftShiftStage1Idx1Rng2_uid199_fracPostNorm_uid75_fpAddTest(BITSELECT,198)@10 - leftShiftStage1Idx1Rng2_uid199_fracPostNorm_uid75_fpAddTest_in <= leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_q(24 downto 0); - leftShiftStage1Idx1Rng2_uid199_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage1Idx1Rng2_uid199_fracPostNorm_uid75_fpAddTest_in(24 downto 0); + -- leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest(BITSELECT,187)@3 + leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest_in <= leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q(12 downto 0); + leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest_in(12 downto 0); - -- leftShiftStage1Idx1_uid200_fracPostNorm_uid75_fpAddTest(BITJOIN,199)@10 - leftShiftStage1Idx1_uid200_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx1Rng2_uid199_fracPostNorm_uid75_fpAddTest_b & zs_uid140_lzCountVal_uid74_fpAddTest_q; + -- leftShiftStage1Idx1_uid189_fracPostNorm_uid75_fpAddTest(BITJOIN,188)@3 + leftShiftStage1Idx1_uid189_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx1Rng1_uid188_fracPostNorm_uid75_fpAddTest_b & GND_q; - -- leftShiftStage0Idx3Rng24_uid194_fracPostNorm_uid75_fpAddTest(BITSELECT,193)@10 - leftShiftStage0Idx3Rng24_uid194_fracPostNorm_uid75_fpAddTest_in <= redist16_fracAddResultNoSignExt_uid73_fpAddTest_b_4_q(2 downto 0); - leftShiftStage0Idx3Rng24_uid194_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage0Idx3Rng24_uid194_fracPostNorm_uid75_fpAddTest_in(2 downto 0); + -- leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest(BITSELECT,182)@3 + leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest_in <= redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q(1 downto 0); + leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest_in(1 downto 0); - -- leftShiftStage0Idx3Pad24_uid193_fracPostNorm_uid75_fpAddTest(CONSTANT,192) - leftShiftStage0Idx3Pad24_uid193_fracPostNorm_uid75_fpAddTest_q <= "000000000000000000000000"; + -- leftShiftStage0Idx3Pad12_uid182_fracPostNorm_uid75_fpAddTest(CONSTANT,181) + leftShiftStage0Idx3Pad12_uid182_fracPostNorm_uid75_fpAddTest_q <= "000000000000"; - -- leftShiftStage0Idx3_uid195_fracPostNorm_uid75_fpAddTest(BITJOIN,194)@10 - leftShiftStage0Idx3_uid195_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx3Rng24_uid194_fracPostNorm_uid75_fpAddTest_b & leftShiftStage0Idx3Pad24_uid193_fracPostNorm_uid75_fpAddTest_q; + -- leftShiftStage0Idx3_uid184_fracPostNorm_uid75_fpAddTest(BITJOIN,183)@3 + leftShiftStage0Idx3_uid184_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx3Rng12_uid183_fracPostNorm_uid75_fpAddTest_b & leftShiftStage0Idx3Pad12_uid182_fracPostNorm_uid75_fpAddTest_q; - -- redist10_vStage_uid124_lzCountVal_uid74_fpAddTest_b_3(DELAY,229) - redist10_vStage_uid124_lzCountVal_uid74_fpAddTest_b_3 : dspba_delay - GENERIC MAP ( width => 11, depth => 3, reset_kind => "ASYNC" ) - PORT MAP ( xin => vStage_uid124_lzCountVal_uid74_fpAddTest_b, xout => redist10_vStage_uid124_lzCountVal_uid74_fpAddTest_b_3_q, clk => clk, aclr => areset ); + -- redist2_vStage_uid124_lzCountVal_uid74_fpAddTest_b_1(DELAY,204) + redist2_vStage_uid124_lzCountVal_uid74_fpAddTest_b_1 : dspba_delay + GENERIC MAP ( width => 6, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => vStage_uid124_lzCountVal_uid74_fpAddTest_b, xout => redist2_vStage_uid124_lzCountVal_uid74_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); - -- leftShiftStage0Idx2_uid192_fracPostNorm_uid75_fpAddTest(BITJOIN,191)@10 - leftShiftStage0Idx2_uid192_fracPostNorm_uid75_fpAddTest_q <= redist10_vStage_uid124_lzCountVal_uid74_fpAddTest_b_3_q & zs_uid120_lzCountVal_uid74_fpAddTest_q; + -- leftShiftStage0Idx2_uid181_fracPostNorm_uid75_fpAddTest(BITJOIN,180)@3 + leftShiftStage0Idx2_uid181_fracPostNorm_uid75_fpAddTest_q <= redist2_vStage_uid124_lzCountVal_uid74_fpAddTest_b_1_q & zs_uid120_lzCountVal_uid74_fpAddTest_q; - -- leftShiftStage0Idx1Rng8_uid188_fracPostNorm_uid75_fpAddTest(BITSELECT,187)@10 - leftShiftStage0Idx1Rng8_uid188_fracPostNorm_uid75_fpAddTest_in <= redist16_fracAddResultNoSignExt_uid73_fpAddTest_b_4_q(18 downto 0); - leftShiftStage0Idx1Rng8_uid188_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage0Idx1Rng8_uid188_fracPostNorm_uid75_fpAddTest_in(18 downto 0); + -- leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest(BITSELECT,176)@3 + leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest_in <= redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q(9 downto 0); + leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest_b <= leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest_in(9 downto 0); - -- leftShiftStage0Idx1_uid189_fracPostNorm_uid75_fpAddTest(BITJOIN,188)@10 - leftShiftStage0Idx1_uid189_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx1Rng8_uid188_fracPostNorm_uid75_fpAddTest_b & cstAllZWE_uid20_fpAddTest_q; + -- leftShiftStage0Idx1_uid178_fracPostNorm_uid75_fpAddTest(BITJOIN,177)@3 + leftShiftStage0Idx1_uid178_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx1Rng4_uid177_fracPostNorm_uid75_fpAddTest_b & zs_uid128_lzCountVal_uid74_fpAddTest_q; - -- redist16_fracAddResultNoSignExt_uid73_fpAddTest_b_4(DELAY,235) - redist16_fracAddResultNoSignExt_uid73_fpAddTest_b_4 : dspba_delay - GENERIC MAP ( width => 27, depth => 3, reset_kind => "ASYNC" ) - PORT MAP ( xin => redist15_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q, xout => redist16_fracAddResultNoSignExt_uid73_fpAddTest_b_4_q, clk => clk, aclr => areset ); + -- redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1(DELAY,208) + redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1 : dspba_delay + GENERIC MAP ( width => 14, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => fracAddResultNoSignExt_uid73_fpAddTest_b, xout => redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); - -- leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest(MUX,196)@10 - leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_s <= leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_b; - leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_combproc: PROCESS (leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_s, redist16_fracAddResultNoSignExt_uid73_fpAddTest_b_4_q, leftShiftStage0Idx1_uid189_fracPostNorm_uid75_fpAddTest_q, leftShiftStage0Idx2_uid192_fracPostNorm_uid75_fpAddTest_q, leftShiftStage0Idx3_uid195_fracPostNorm_uid75_fpAddTest_q) + -- leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest(MUX,185)@3 + leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_s <= leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select_b; + leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_combproc: PROCESS (leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_s, en, redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q, leftShiftStage0Idx1_uid178_fracPostNorm_uid75_fpAddTest_q, leftShiftStage0Idx2_uid181_fracPostNorm_uid75_fpAddTest_q, leftShiftStage0Idx3_uid184_fracPostNorm_uid75_fpAddTest_q) BEGIN - CASE (leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_s) IS - WHEN "00" => leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_q <= redist16_fracAddResultNoSignExt_uid73_fpAddTest_b_4_q; - WHEN "01" => leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx1_uid189_fracPostNorm_uid75_fpAddTest_q; - WHEN "10" => leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx2_uid192_fracPostNorm_uid75_fpAddTest_q; - WHEN "11" => leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx3_uid195_fracPostNorm_uid75_fpAddTest_q; - WHEN OTHERS => leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_q <= (others => '0'); + CASE (leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_s) IS + WHEN "00" => leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q <= redist6_fracAddResultNoSignExt_uid73_fpAddTest_b_1_q; + WHEN "01" => leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx1_uid178_fracPostNorm_uid75_fpAddTest_q; + WHEN "10" => leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx2_uid181_fracPostNorm_uid75_fpAddTest_q; + WHEN "11" => leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0Idx3_uid184_fracPostNorm_uid75_fpAddTest_q; + WHEN OTHERS => leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q <= (others => '0'); END CASE; END PROCESS; - -- leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select(BITSELECT,218)@10 - leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_b <= r_uid149_lzCountVal_uid74_fpAddTest_q(4 downto 3); - leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_c <= r_uid149_lzCountVal_uid74_fpAddTest_q(2 downto 1); - leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_d <= r_uid149_lzCountVal_uid74_fpAddTest_q(0 downto 0); - - -- leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest(MUX,207)@10 + 1 - leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_s <= leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_c; - leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_q <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - CASE (leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_s) IS - WHEN "00" => leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0_uid197_fracPostNorm_uid75_fpAddTest_q; - WHEN "01" => leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx1_uid200_fracPostNorm_uid75_fpAddTest_q; - WHEN "10" => leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx2_uid203_fracPostNorm_uid75_fpAddTest_q; - WHEN "11" => leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx3_uid206_fracPostNorm_uid75_fpAddTest_q; - WHEN OTHERS => leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_q <= (others => '0'); - END CASE; - END IF; - END PROCESS; - - -- redist0_leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_d_1(DELAY,219) - redist0_leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_d_1 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_d, xout => redist0_leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_d_1_q, clk => clk, aclr => areset ); + -- leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select(BITSELECT,201)@3 + leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select_b <= r_uid143_lzCountVal_uid74_fpAddTest_q(3 downto 2); + leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select_c <= r_uid143_lzCountVal_uid74_fpAddTest_q(1 downto 0); - -- leftShiftStage2_uid213_fracPostNorm_uid75_fpAddTest(MUX,212)@11 - leftShiftStage2_uid213_fracPostNorm_uid75_fpAddTest_s <= redist0_leftShiftStageSel4Dto3_uid196_fracPostNorm_uid75_fpAddTest_merged_bit_select_d_1_q; - leftShiftStage2_uid213_fracPostNorm_uid75_fpAddTest_combproc: PROCESS (leftShiftStage2_uid213_fracPostNorm_uid75_fpAddTest_s, leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_q, leftShiftStage2Idx1_uid211_fracPostNorm_uid75_fpAddTest_q) + -- leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest(MUX,196)@3 + leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_s <= leftShiftStageSel3Dto2_uid185_fracPostNorm_uid75_fpAddTest_merged_bit_select_c; + leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_combproc: PROCESS (leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_s, en, leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q, leftShiftStage1Idx1_uid189_fracPostNorm_uid75_fpAddTest_q, leftShiftStage1Idx2_uid192_fracPostNorm_uid75_fpAddTest_q, leftShiftStage1Idx3_uid195_fracPostNorm_uid75_fpAddTest_q) BEGIN - CASE (leftShiftStage2_uid213_fracPostNorm_uid75_fpAddTest_s) IS - WHEN "0" => leftShiftStage2_uid213_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1_uid208_fracPostNorm_uid75_fpAddTest_q; - WHEN "1" => leftShiftStage2_uid213_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage2Idx1_uid211_fracPostNorm_uid75_fpAddTest_q; - WHEN OTHERS => leftShiftStage2_uid213_fracPostNorm_uid75_fpAddTest_q <= (others => '0'); + CASE (leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_s) IS + WHEN "00" => leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage0_uid186_fracPostNorm_uid75_fpAddTest_q; + WHEN "01" => leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx1_uid189_fracPostNorm_uid75_fpAddTest_q; + WHEN "10" => leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx2_uid192_fracPostNorm_uid75_fpAddTest_q; + WHEN "11" => leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_q <= leftShiftStage1Idx3_uid195_fracPostNorm_uid75_fpAddTest_q; + WHEN OTHERS => leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_q <= (others => '0'); END CASE; END PROCESS; - -- fracPostNormRndRange_uid80_fpAddTest(BITSELECT,79)@11 - fracPostNormRndRange_uid80_fpAddTest_in <= leftShiftStage2_uid213_fracPostNorm_uid75_fpAddTest_q(25 downto 0); - fracPostNormRndRange_uid80_fpAddTest_b <= fracPostNormRndRange_uid80_fpAddTest_in(25 downto 2); + -- fracPostNormRndRange_uid80_fpAddTest(BITSELECT,79)@3 + fracPostNormRndRange_uid80_fpAddTest_in <= leftShiftStage1_uid197_fracPostNorm_uid75_fpAddTest_q(12 downto 0); + fracPostNormRndRange_uid80_fpAddTest_b <= fracPostNormRndRange_uid80_fpAddTest_in(12 downto 2); - -- expFracR_uid81_fpAddTest(BITJOIN,80)@11 + -- expFracR_uid81_fpAddTest(BITJOIN,80)@3 expFracR_uid81_fpAddTest_q <= expPostNorm_uid79_fpAddTest_q & fracPostNormRndRange_uid80_fpAddTest_b; - -- expRPreExc_uid87_fpAddTest(BITSELECT,86)@11 - expRPreExc_uid87_fpAddTest_in <= expFracR_uid81_fpAddTest_q(31 downto 0); - expRPreExc_uid87_fpAddTest_b <= expRPreExc_uid87_fpAddTest_in(31 downto 24); + -- redist5_expFracR_uid81_fpAddTest_q_1(DELAY,207) + redist5_expFracR_uid81_fpAddTest_q_1 : dspba_delay + GENERIC MAP ( width => 18, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => expFracR_uid81_fpAddTest_q, xout => redist5_expFracR_uid81_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); - -- redist13_expRPreExc_uid87_fpAddTest_b_2(DELAY,232) - redist13_expRPreExc_uid87_fpAddTest_b_2 : dspba_delay - GENERIC MAP ( width => 8, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => expRPreExc_uid87_fpAddTest_b, xout => redist13_expRPreExc_uid87_fpAddTest_b_2_q, clk => clk, aclr => areset ); + -- expRPreExc_uid87_fpAddTest(BITSELECT,86)@4 + expRPreExc_uid87_fpAddTest_in <= redist5_expFracR_uid81_fpAddTest_q_1_q(15 downto 0); + expRPreExc_uid87_fpAddTest_b <= expRPreExc_uid87_fpAddTest_in(15 downto 11); -- wEP2AllOwE_uid82_fpAddTest(CONSTANT,81) - wEP2AllOwE_uid82_fpAddTest_q <= "0011111111"; + wEP2AllOwE_uid82_fpAddTest_q <= "0011111"; - -- rndExp_uid83_fpAddTest(BITSELECT,82)@11 - rndExp_uid83_fpAddTest_b <= expFracR_uid81_fpAddTest_q(33 downto 24); + -- rndExp_uid83_fpAddTest(BITSELECT,82)@4 + rndExp_uid83_fpAddTest_b <= redist5_expFracR_uid81_fpAddTest_q_1_q(17 downto 11); - -- rOvf_uid84_fpAddTest(LOGICAL,83)@11 + 1 - rOvf_uid84_fpAddTest_qi <= "1" WHEN rndExp_uid83_fpAddTest_b = wEP2AllOwE_uid82_fpAddTest_q ELSE "0"; - rOvf_uid84_fpAddTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => rOvf_uid84_fpAddTest_qi, xout => rOvf_uid84_fpAddTest_q, clk => clk, aclr => areset ); + -- rOvf_uid84_fpAddTest(LOGICAL,83)@4 + rOvf_uid84_fpAddTest_q <= "1" WHEN rndExp_uid83_fpAddTest_b = wEP2AllOwE_uid82_fpAddTest_q ELSE "0"; - -- regInputs_uid88_fpAddTest(LOGICAL,87)@11 + -- regInputs_uid88_fpAddTest(LOGICAL,87)@3 regInputs_uid88_fpAddTest_q <= excR_aSig_uid31_fpAddTest_q and excR_bSig_uid45_fpAddTest_q; - -- redist12_regInputs_uid88_fpAddTest_q_1(DELAY,231) - redist12_regInputs_uid88_fpAddTest_q_1 : dspba_delay + -- redist4_regInputs_uid88_fpAddTest_q_1(DELAY,206) + redist4_regInputs_uid88_fpAddTest_q_1 : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => regInputs_uid88_fpAddTest_q, xout => redist12_regInputs_uid88_fpAddTest_q_1_q, clk => clk, aclr => areset ); + PORT MAP ( xin => regInputs_uid88_fpAddTest_q, xout => redist4_regInputs_uid88_fpAddTest_q_1_q, ena => en(0), clk => clk, aclr => areset ); - -- rInfOvf_uid91_fpAddTest(LOGICAL,90)@12 - rInfOvf_uid91_fpAddTest_q <= redist12_regInputs_uid88_fpAddTest_q_1_q and rOvf_uid84_fpAddTest_q; + -- rInfOvf_uid91_fpAddTest(LOGICAL,90)@4 + rInfOvf_uid91_fpAddTest_q <= redist4_regInputs_uid88_fpAddTest_q_1_q and rOvf_uid84_fpAddTest_q; - -- excRInfVInC_uid92_fpAddTest(BITJOIN,91)@12 - excRInfVInC_uid92_fpAddTest_q <= rInfOvf_uid91_fpAddTest_q & redist25_excN_bSig_uid42_fpAddTest_q_2_q & redist31_excN_aSig_uid28_fpAddTest_q_2_q & redist26_excI_bSig_uid41_fpAddTest_q_2_q & redist32_excI_aSig_uid27_fpAddTest_q_2_q & redist19_effSub_uid52_fpAddTest_q_10_q; + -- excRInfVInC_uid92_fpAddTest(BITJOIN,91)@4 + excRInfVInC_uid92_fpAddTest_q <= rInfOvf_uid91_fpAddTest_q & excN_bSig_uid42_fpAddTest_q & excN_aSig_uid28_fpAddTest_q & redist11_excI_bSig_uid41_fpAddTest_q_1_q & redist17_excI_aSig_uid27_fpAddTest_q_1_q & redist7_effSub_uid52_fpAddTest_q_4_q; - -- excRInf_uid93_fpAddTest(LOOKUP,92)@12 + -- excRInf_uid93_fpAddTest(LOOKUP,92)@4 excRInf_uid93_fpAddTest_combproc: PROCESS (excRInfVInC_uid92_fpAddTest_q) BEGIN -- Begin reserved scope level @@ -1585,88 +1053,88 @@ begin -- End reserved scope level END PROCESS; - -- rUdf_uid85_fpAddTest(BITSELECT,84)@11 - rUdf_uid85_fpAddTest_b <= STD_LOGIC_VECTOR(expFracR_uid81_fpAddTest_q(33 downto 33)); + -- rUdf_uid85_fpAddTest(BITSELECT,84)@3 + rUdf_uid85_fpAddTest_b <= STD_LOGIC_VECTOR(expFracR_uid81_fpAddTest_q(17 downto 17)); - -- excRZeroVInC_uid89_fpAddTest(BITJOIN,88)@11 - excRZeroVInC_uid89_fpAddTest_q <= aMinusA_uid77_fpAddTest_q & rUdf_uid85_fpAddTest_b & regInputs_uid88_fpAddTest_q & redist29_excZ_bSig_uid17_uid37_fpAddTest_q_10_q & redist34_excZ_aSig_uid16_uid23_fpAddTest_q_2_q; + -- excRZeroVInC_uid89_fpAddTest(BITJOIN,88)@3 + excRZeroVInC_uid89_fpAddTest_q <= aMinusA_uid77_fpAddTest_q & rUdf_uid85_fpAddTest_b & regInputs_uid88_fpAddTest_q & redist15_excZ_bSig_uid17_uid37_fpAddTest_q_3_q & excZ_aSig_uid16_uid23_fpAddTest_q; - -- excRZero_uid90_fpAddTest(LOOKUP,89)@11 + 1 + -- excRZero_uid90_fpAddTest(LOOKUP,89)@3 + 1 excRZero_uid90_fpAddTest_clkproc: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN excRZero_uid90_fpAddTest_q <= "0"; ELSIF (clk'EVENT AND clk = '1') THEN - CASE (excRZeroVInC_uid89_fpAddTest_q) IS - WHEN "00000" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "00001" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "00010" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "00011" => excRZero_uid90_fpAddTest_q <= "1"; - WHEN "00100" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "00101" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "00110" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "00111" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "01000" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "01001" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "01010" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "01011" => excRZero_uid90_fpAddTest_q <= "1"; - WHEN "01100" => excRZero_uid90_fpAddTest_q <= "1"; - WHEN "01101" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "01110" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "01111" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "10000" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "10001" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "10010" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "10011" => excRZero_uid90_fpAddTest_q <= "1"; - WHEN "10100" => excRZero_uid90_fpAddTest_q <= "1"; - WHEN "10101" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "10110" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "10111" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "11000" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "11001" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "11010" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "11011" => excRZero_uid90_fpAddTest_q <= "1"; - WHEN "11100" => excRZero_uid90_fpAddTest_q <= "1"; - WHEN "11101" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "11110" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN "11111" => excRZero_uid90_fpAddTest_q <= "0"; - WHEN OTHERS => -- unreachable - excRZero_uid90_fpAddTest_q <= (others => '-'); - END CASE; + IF (en = "1") THEN + CASE (excRZeroVInC_uid89_fpAddTest_q) IS + WHEN "00000" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "00001" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "00010" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "00011" => excRZero_uid90_fpAddTest_q <= "1"; + WHEN "00100" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "00101" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "00110" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "00111" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "01000" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "01001" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "01010" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "01011" => excRZero_uid90_fpAddTest_q <= "1"; + WHEN "01100" => excRZero_uid90_fpAddTest_q <= "1"; + WHEN "01101" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "01110" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "01111" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "10000" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "10001" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "10010" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "10011" => excRZero_uid90_fpAddTest_q <= "1"; + WHEN "10100" => excRZero_uid90_fpAddTest_q <= "1"; + WHEN "10101" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "10110" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "10111" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "11000" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "11001" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "11010" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "11011" => excRZero_uid90_fpAddTest_q <= "1"; + WHEN "11100" => excRZero_uid90_fpAddTest_q <= "1"; + WHEN "11101" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "11110" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN "11111" => excRZero_uid90_fpAddTest_q <= "0"; + WHEN OTHERS => -- unreachable + excRZero_uid90_fpAddTest_q <= (others => '-'); + END CASE; + END IF; END IF; END PROCESS; - -- concExc_uid97_fpAddTest(BITJOIN,96)@12 + -- concExc_uid97_fpAddTest(BITJOIN,96)@4 concExc_uid97_fpAddTest_q <= excRNaN_uid96_fpAddTest_q & excRInf_uid93_fpAddTest_q & excRZero_uid90_fpAddTest_q; - -- excREnc_uid98_fpAddTest(LOOKUP,97)@12 + 1 - excREnc_uid98_fpAddTest_clkproc: PROCESS (clk, areset) + -- excREnc_uid98_fpAddTest(LOOKUP,97)@4 + excREnc_uid98_fpAddTest_combproc: PROCESS (concExc_uid97_fpAddTest_q) BEGIN - IF (areset = '1') THEN - excREnc_uid98_fpAddTest_q <= "01"; - ELSIF (clk'EVENT AND clk = '1') THEN - CASE (concExc_uid97_fpAddTest_q) IS - WHEN "000" => excREnc_uid98_fpAddTest_q <= "01"; - WHEN "001" => excREnc_uid98_fpAddTest_q <= "00"; - WHEN "010" => excREnc_uid98_fpAddTest_q <= "10"; - WHEN "011" => excREnc_uid98_fpAddTest_q <= "10"; - WHEN "100" => excREnc_uid98_fpAddTest_q <= "11"; - WHEN "101" => excREnc_uid98_fpAddTest_q <= "11"; - WHEN "110" => excREnc_uid98_fpAddTest_q <= "11"; - WHEN "111" => excREnc_uid98_fpAddTest_q <= "11"; - WHEN OTHERS => -- unreachable - excREnc_uid98_fpAddTest_q <= (others => '-'); - END CASE; - END IF; + -- Begin reserved scope level + CASE (concExc_uid97_fpAddTest_q) IS + WHEN "000" => excREnc_uid98_fpAddTest_q <= "01"; + WHEN "001" => excREnc_uid98_fpAddTest_q <= "00"; + WHEN "010" => excREnc_uid98_fpAddTest_q <= "10"; + WHEN "011" => excREnc_uid98_fpAddTest_q <= "10"; + WHEN "100" => excREnc_uid98_fpAddTest_q <= "11"; + WHEN "101" => excREnc_uid98_fpAddTest_q <= "11"; + WHEN "110" => excREnc_uid98_fpAddTest_q <= "11"; + WHEN "111" => excREnc_uid98_fpAddTest_q <= "11"; + WHEN OTHERS => -- unreachable + excREnc_uid98_fpAddTest_q <= (others => '-'); + END CASE; + -- End reserved scope level END PROCESS; - -- expRPostExc_uid117_fpAddTest(MUX,116)@13 + -- expRPostExc_uid117_fpAddTest(MUX,116)@4 expRPostExc_uid117_fpAddTest_s <= excREnc_uid98_fpAddTest_q; - expRPostExc_uid117_fpAddTest_combproc: PROCESS (expRPostExc_uid117_fpAddTest_s, cstAllZWE_uid20_fpAddTest_q, redist13_expRPreExc_uid87_fpAddTest_b_2_q, cstAllOWE_uid18_fpAddTest_q) + expRPostExc_uid117_fpAddTest_combproc: PROCESS (expRPostExc_uid117_fpAddTest_s, en, cstAllZWE_uid20_fpAddTest_q, expRPreExc_uid87_fpAddTest_b, cstAllOWE_uid18_fpAddTest_q) BEGIN CASE (expRPostExc_uid117_fpAddTest_s) IS WHEN "00" => expRPostExc_uid117_fpAddTest_q <= cstAllZWE_uid20_fpAddTest_q; - WHEN "01" => expRPostExc_uid117_fpAddTest_q <= redist13_expRPreExc_uid87_fpAddTest_b_2_q; + WHEN "01" => expRPostExc_uid117_fpAddTest_q <= expRPreExc_uid87_fpAddTest_b; WHEN "10" => expRPostExc_uid117_fpAddTest_q <= cstAllOWE_uid18_fpAddTest_q; WHEN "11" => expRPostExc_uid117_fpAddTest_q <= cstAllOWE_uid18_fpAddTest_q; WHEN OTHERS => expRPostExc_uid117_fpAddTest_q <= (others => '0'); @@ -1674,34 +1142,29 @@ begin END PROCESS; -- oneFracRPostExc2_uid110_fpAddTest(CONSTANT,109) - oneFracRPostExc2_uid110_fpAddTest_q <= "00000000000000000000001"; - - -- fracRPreExc_uid86_fpAddTest(BITSELECT,85)@11 - fracRPreExc_uid86_fpAddTest_in <= expFracR_uid81_fpAddTest_q(23 downto 0); - fracRPreExc_uid86_fpAddTest_b <= fracRPreExc_uid86_fpAddTest_in(23 downto 1); + oneFracRPostExc2_uid110_fpAddTest_q <= "0000000001"; - -- redist14_fracRPreExc_uid86_fpAddTest_b_2(DELAY,233) - redist14_fracRPreExc_uid86_fpAddTest_b_2 : dspba_delay - GENERIC MAP ( width => 23, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracRPreExc_uid86_fpAddTest_b, xout => redist14_fracRPreExc_uid86_fpAddTest_b_2_q, clk => clk, aclr => areset ); + -- fracRPreExc_uid86_fpAddTest(BITSELECT,85)@4 + fracRPreExc_uid86_fpAddTest_in <= redist5_expFracR_uid81_fpAddTest_q_1_q(10 downto 0); + fracRPreExc_uid86_fpAddTest_b <= fracRPreExc_uid86_fpAddTest_in(10 downto 1); - -- fracRPostExc_uid113_fpAddTest(MUX,112)@13 + -- fracRPostExc_uid113_fpAddTest(MUX,112)@4 fracRPostExc_uid113_fpAddTest_s <= excREnc_uid98_fpAddTest_q; - fracRPostExc_uid113_fpAddTest_combproc: PROCESS (fracRPostExc_uid113_fpAddTest_s, cstZeroWF_uid19_fpAddTest_q, redist14_fracRPreExc_uid86_fpAddTest_b_2_q, oneFracRPostExc2_uid110_fpAddTest_q) + fracRPostExc_uid113_fpAddTest_combproc: PROCESS (fracRPostExc_uid113_fpAddTest_s, en, cstZeroWF_uid19_fpAddTest_q, fracRPreExc_uid86_fpAddTest_b, oneFracRPostExc2_uid110_fpAddTest_q) BEGIN CASE (fracRPostExc_uid113_fpAddTest_s) IS WHEN "00" => fracRPostExc_uid113_fpAddTest_q <= cstZeroWF_uid19_fpAddTest_q; - WHEN "01" => fracRPostExc_uid113_fpAddTest_q <= redist14_fracRPreExc_uid86_fpAddTest_b_2_q; + WHEN "01" => fracRPostExc_uid113_fpAddTest_q <= fracRPreExc_uid86_fpAddTest_b; WHEN "10" => fracRPostExc_uid113_fpAddTest_q <= cstZeroWF_uid19_fpAddTest_q; WHEN "11" => fracRPostExc_uid113_fpAddTest_q <= oneFracRPostExc2_uid110_fpAddTest_q; WHEN OTHERS => fracRPostExc_uid113_fpAddTest_q <= (others => '0'); END CASE; END PROCESS; - -- R_uid118_fpAddTest(BITJOIN,117)@13 + -- R_uid118_fpAddTest(BITJOIN,117)@4 R_uid118_fpAddTest_q <= signRPostExc_uid109_fpAddTest_q & expRPostExc_uid117_fpAddTest_q & fracRPostExc_uid113_fpAddTest_q; - -- xOut(GPOUT,4)@13 + -- xOut(GPOUT,4)@4 q <= R_uid118_fpAddTest_q; END normal; diff --git a/ip/ip_fp_add_sim/aldec/rivierapro_setup.tcl b/ip/ip_fp_add_sim/aldec/rivierapro_setup.tcl index a6ecfc3..30e7693 100644 --- a/ip/ip_fp_add_sim/aldec/rivierapro_setup.tcl +++ b/ip/ip_fp_add_sim/aldec/rivierapro_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.04:46:09 +# ACDS 20.1 720 linux 2023.10.21.20:34:02 # ---------------------------------------- # Auto-generated simulation script rivierapro_setup.tcl # ---------------------------------------- diff --git a/ip/ip_fp_add_sim/cadence/ncsim_setup.sh b/ip/ip_fp_add_sim/cadence/ncsim_setup.sh index 62715d5..f2c4933 100755 --- a/ip/ip_fp_add_sim/cadence/ncsim_setup.sh +++ b/ip/ip_fp_add_sim/cadence/ncsim_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.04:46:09 +# ACDS 20.1 720 linux 2023.10.21.20:34:02 # ---------------------------------------- # ncsim - auto-generated simulation script @@ -106,7 +106,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.04:46:09 +# ACDS 20.1 720 linux 2023.10.21.20:34:02 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="ip_fp_add" diff --git a/ip/ip_fp_add_sim/ip_fp_add.vo b/ip/ip_fp_add_sim/ip_fp_add.vo index ce49c05..3f5f32a 100644 --- a/ip/ip_fp_add_sim/ip_fp_add.vo +++ b/ip/ip_fp_add_sim/ip_fp_add.vo @@ -27,7 +27,7 @@ //synopsys translate_off -//synthesis_resources = altera_syncram 2 lut 628 mux21 195 oper_add 11 oper_mux 137 +//synthesis_resources = lut 135 mux21 66 oper_add 7 oper_mux 68 `timescale 1 ps / 1 ps module ip_fp_add ( @@ -35,20 +35,15 @@ module ip_fp_add areset, b, clk, + en, q) /* synthesis synthesis_clearbox=1 */; - input [31:0] a; + input [15:0] a; input areset; - input [31:0] b; + input [15:0] b; input clk; - output [31:0] q; + input [0:0] en; + output [15:0] q; - wire [22:0] wire_ni0Oii_q_b; - wire [7:0] wire_nil10l_q_b; - reg n010O; - reg n011O; - reg n11Oi; - reg nll00i; - reg nlOO1i; reg n000i; reg n000l; reg n000O; @@ -65,50 +60,58 @@ module ip_fp_add reg n00Ol; reg n00OO; reg n010i; + reg n010l; + reg n010O; + reg n011i; + reg n011l; + reg n011O; reg n01ii; reg n01il; + reg n01iO; + reg n01li; + reg n01ll; reg n01lO; + reg n01Oi; reg n01Ol; reg n01OO; - reg n0i0i; - reg n0i0l; - reg n0i0O; reg n0i1i; reg n0i1l; - reg n0i1O; - reg n0iii; - reg n0iil; - reg n0iiO; - reg n0ili; - reg n0ill; - reg n0OiO; - reg n0Oll; - reg n0OlO; - reg n0OlOl; - reg n0OlOO; - reg n0OO0i; - reg n0OO0l; - reg n0OO0O; - reg n0OO1i; - reg n0OO1l; - reg n0OO1O; - reg n0OOi; - reg n0OOii; - reg n0OOil; - reg n0OOiO; - reg n0OOl; - reg n0OOli; - reg n0OOll; - reg n0OOlO; - reg n0OOO; - reg n0OOOi; - reg n0OOOl; - reg n0OOOO; + reg n0ii; + reg n0il; + reg n0iO; + reg n0li; + reg n0ll; + reg n0lO; + reg n0Oi; + reg n0Ol; + reg n100i; + reg n100l; + reg n100O; reg n101i; reg n101l; reg n101O; + reg n10ii; + reg n10il; reg n10iO; + reg n10li; + reg n10ll; + reg n10lO; + reg n10Oi; + reg n10Ol; + reg n10OO; + reg n110i; + reg n110l; + reg n110O; + reg n111i; + reg n111l; + reg n111O; + reg n11ii; + reg n11il; + reg n11iO; + reg n11li; + reg n11ll; reg n11lO; + reg n11Oi; reg n11Ol; reg n11OO; reg n1i0i; @@ -118,6 +121,13 @@ module ip_fp_add reg n1i1l; reg n1i1O; reg n1iii; + reg n1iil; + reg n1iiO; + reg n1ili; + reg n1ill; + reg n1ilO; + reg n1iOi; + reg n1iOl; reg n1iOO; reg n1l0i; reg n1l0l; @@ -134,687 +144,80 @@ module ip_fp_add reg n1lOi; reg n1lOl; reg n1lOO; - reg ni000i; - reg ni000l; - reg ni000O; - reg ni001i; - reg ni001l; - reg ni001O; - reg ni00i; - reg ni00ii; - reg ni00il; - reg ni00iO; - reg ni00l; - reg ni00li; - reg ni00ll; - reg ni00lO; - reg ni00O; - reg ni00Oi; - reg ni00Ol; - reg ni00OO; - reg ni010i; - reg ni010l; - reg ni010O; - reg ni011i; - reg ni011l; - reg ni011O; - reg ni01i; - reg ni01ii; - reg ni01il; - reg ni01iO; - reg ni01l; - reg ni01li; - reg ni01ll; - reg ni01lO; - reg ni01O; - reg ni01Oi; - reg ni01Ol; - reg ni01OO; - reg ni0i0i; - reg ni0i0l; - reg ni0i0O; - reg ni0i1i; - reg ni0i1l; - reg ni0i1O; - reg ni0ii; - reg ni0iii; - reg ni0iil; - reg ni0iiO; - reg ni0ili; - reg ni0ill; - reg ni0ilO; - reg ni0iOi; - reg ni0iOl; - reg ni0iOO; - reg ni0l0i; - reg ni0l0l; - reg ni0l0O; - reg ni0l1i; - reg ni0l1l; - reg ni0l1O; - reg ni0lii; - reg ni0lil; - reg ni0liO; - reg ni0lli; - reg ni0lll; - reg ni0llO; - reg ni0lOi; - reg ni0lOl; - reg ni0lOO; - reg ni0O0i; - reg ni0O0l; - reg ni0O0O; - reg ni0O1i; - reg ni0O1l; - reg ni0O1O; - reg ni0Oil; - reg ni0OiO; - reg ni0Oli; - reg ni0Oll; - reg ni0OlO; - reg ni0OOi; - reg ni0OOl; - reg ni0OOO; - reg ni100i; - reg ni100l; - reg ni100O; - reg ni101i; - reg ni101l; - reg ni101O; - reg ni10i; - reg ni10ii; - reg ni10il; - reg ni10iO; - reg ni10l; - reg ni10li; - reg ni10ll; - reg ni10lO; - reg ni10O; - reg ni10Oi; - reg ni10Ol; - reg ni10OO; - reg ni110i; - reg ni110l; - reg ni110O; - reg ni111i; - reg ni111l; - reg ni111O; - reg ni11i; - reg ni11ii; - reg ni11il; - reg ni11iO; - reg ni11l; - reg ni11li; - reg ni11ll; - reg ni11lO; - reg ni11O; - reg ni11Oi; - reg ni11Ol; - reg ni11OO; - reg ni1i0i; - reg ni1i0l; - reg ni1i0O; - reg ni1i1i; - reg ni1i1l; - reg ni1i1O; - reg ni1ii; - reg ni1iii; - reg ni1iil; - reg ni1iiO; - reg ni1il; - reg ni1ili; - reg ni1ill; - reg ni1ilO; - reg ni1iO; - reg ni1iOi; - reg ni1iOl; - reg ni1iOO; - reg ni1l0i; - reg ni1l0l; - reg ni1l0O; - reg ni1l1i; - reg ni1l1l; - reg ni1l1O; - reg ni1li; - reg ni1lii; - reg ni1lil; - reg ni1liO; - reg ni1ll; - reg ni1lli; - reg ni1lll; - reg ni1llO; - reg ni1lO; - reg ni1lOi; - reg ni1lOl; - reg ni1lOO; - reg ni1O0i; - reg ni1O0l; - reg ni1O0O; - reg ni1O1i; - reg ni1O1l; - reg ni1O1O; - reg ni1Oi; - reg ni1Oii; - reg ni1Oil; - reg ni1OiO; - reg ni1Ol; - reg ni1Oli; - reg ni1Oll; - reg ni1OlO; - reg ni1OO; - reg ni1OOi; - reg ni1OOl; - reg ni1OOO; - reg nii00i; - reg nii00l; - reg nii00O; - reg nii01i; - reg nii01l; - reg nii01O; - reg nii0ii; - reg nii0il; - reg nii0iO; - reg nii0li; - reg nii0ll; - reg nii0lO; - reg nii0Oi; - reg nii0Ol; - reg nii0OO; - reg nii10i; - reg nii10l; - reg nii10O; - reg nii11i; - reg nii11l; - reg nii11O; - reg nii1ii; - reg nii1il; - reg nii1iO; - reg nii1li; - reg nii1ll; - reg nii1lO; - reg nii1Oi; - reg nii1Ol; - reg nii1OO; - reg niii0i; - reg niii0l; - reg niii0O; - reg niii1i; - reg niii1l; - reg niii1O; - reg niiiii; - reg niiiil; - reg niiiiO; - reg niiili; - reg niiill; - reg niiilO; - reg niiiOi; - reg niiiOl; - reg niiiOO; - reg niil0i; - reg niil0l; - reg niil0O; - reg niil1i; - reg niil1l; - reg niil1O; - reg niilii; - reg niilil; - reg niiliO; - reg niilli; - reg niilll; - reg niillO; - reg niilOi; - reg niilOl; - reg niilOO; - reg niiO0i; - reg niiO0l; - reg niiO0O; - reg niiO1i; - reg niiO1l; - reg niiO1O; - reg niiOii; - reg niiOil; - reg niiOiO; - reg niiOli; - reg niiOll; - reg niiOlO; - reg niiOOi; - reg niiOOl; - reg niiOOO; - reg nil00i; - reg nil00l; - reg nil00O; - reg nil01i; - reg nil01l; - reg nil01O; - reg nil0ii; - reg nil0il; - reg nil0iO; - reg nil0li; - reg nil0ll; - reg nil0lO; - reg nil0Oi; - reg nil0Ol; - reg nil0OO; - reg nil10i; - reg nil10O; - reg nil11i; - reg nil11l; - reg nil11O; - reg nil1ii; - reg nil1il; - reg nil1iO; - reg nil1li; - reg nil1ll; - reg nil1lO; - reg nil1Oi; - reg nil1Ol; - reg nil1OO; - reg nili0i; - reg nili0l; - reg nili0O; - reg nili1i; - reg nili1l; - reg nili1O; - reg niliii; - reg niliil; - reg niliiO; - reg nilili; - reg nilill; - reg nililO; - reg niliOi; - reg niliOl; - reg niliOO; - reg nill0i; - reg nill0l; - reg nill0O; - reg nill1i; - reg nill1l; - reg nill1O; - reg nillii; - reg nillil; - reg nilliO; - reg nillli; - reg nillll; - reg nilllO; - reg nillOi; - reg nillOl; - reg nillOO; - reg nilO0i; - reg nilO0l; - reg nilO0O; - reg nilO1i; - reg nilO1l; - reg nilO1O; - reg nilOii; - reg nilOil; - reg nilOiO; - reg nilOli; - reg nilOll; - reg nilOlO; - reg nilOOi; - reg nilOOl; - reg nilOOO; - reg niO00i; - reg niO00l; - reg niO00O; - reg niO01i; - reg niO01l; - reg niO01O; - reg niO0ii; - reg niO0il; - reg niO0iO; - reg niO0li; - reg niO0ll; - reg niO0lO; - reg niO0Oi; - reg niO0Ol; - reg niO0OO; - reg niO10i; - reg niO10l; - reg niO10O; - reg niO11i; - reg niO11l; - reg niO11O; - reg niO1ii; - reg niO1il; - reg niO1iO; - reg niO1li; - reg niO1ll; - reg niO1lO; - reg niO1Oi; - reg niO1Ol; - reg niO1OO; - reg niOi0i; - reg niOi0l; - reg niOi0O; - reg niOi1i; - reg niOi1l; - reg niOi1O; - reg niOiii; - reg niOiil; - reg niOiiO; - reg niOili; - reg niOill; - reg niOilO; - reg niOiOi; - reg niOiOl; - reg niOiOO; - reg niOl0i; - reg niOl0l; - reg niOl0O; - reg niOl1i; - reg niOl1l; - reg niOl1O; - reg niOlii; - reg niOlil; - reg niOliO; - reg niOlli; - reg niOlll; - reg niOllO; - reg niOlOi; - reg niOlOl; - reg niOlOO; - reg niOO0i; - reg niOO0l; - reg niOO0O; - reg niOO1i; - reg niOO1l; - reg niOO1O; - reg niOOii; - reg niOOil; - reg niOOiO; - reg niOOli; - reg niOOll; - reg niOOlO; - reg niOOOi; - reg niOOOl; - reg niOOOO; - reg nl010i; - reg nl010l; - reg nl010O; - reg nl011i; - reg nl011l; - reg nl011O; - reg nl01ii; - reg nl01il; - reg nl01iO; - reg nl01li; - reg nl01ll; - reg nl01lO; - reg nl01Oi; - reg nl01Ol; - reg nl0ll; - reg nl0lO; - reg nl0Oi; - reg nl0Ol; + reg n1O0i; + reg n1O0l; + reg n1O0O; + reg n1O1i; + reg n1O1l; + reg n1O1O; + reg n1Oii; + reg n1Oil; + reg n1OiO; + reg n1Oli; + reg n1Oll; + reg n1OlO; + reg n1OOi; + reg n1OOl; + reg n1OOO; + reg ni1i; + reg niiii; + reg niilO; reg nl0OO; - reg nl100i; - reg nl100l; - reg nl100O; - reg nl101i; - reg nl101l; - reg nl101O; - reg nl10ii; - reg nl10il; - reg nl10iO; - reg nl10li; - reg nl10ll; - reg nl10lO; - reg nl10Oi; - reg nl10Ol; - reg nl10OO; - reg nl110i; - reg nl110l; - reg nl110O; - reg nl111i; - reg nl111l; - reg nl111O; - reg nl11ii; - reg nl11il; - reg nl11iO; - reg nl11li; - reg nl11ll; - reg nl11lO; - reg nl11Oi; - reg nl11Ol; - reg nl11OO; - reg nl1i0i; - reg nl1i0l; - reg nl1i0O; - reg nl1i1i; - reg nl1i1l; - reg nl1i1O; - reg nl1iii; - reg nl1iil; - reg nl1iiO; - reg nl1ili; - reg nl1ill; - reg nl1ilO; - reg nl1iOi; - reg nl1iOl; - reg nl1iOO; - reg nl1l0i; - reg nl1l0l; - reg nl1l0O; - reg nl1l1i; - reg nl1l1l; - reg nl1l1O; - reg nl1lii; - reg nl1lil; - reg nl1liO; - reg nl1lli; - reg nl1lll; - reg nl1llO; - reg nl1lOi; - reg nl1lOl; - reg nl1lOO; - reg nl1O0i; - reg nl1O0l; - reg nl1O0O; - reg nl1O1i; - reg nl1O1l; - reg nl1O1O; - reg nl1Oii; - reg nl1Oil; - reg nl1OiO; - reg nl1Oli; - reg nl1Oll; - reg nl1OlO; - reg nl1OOi; - reg nl1OOl; - reg nl1OOO; + reg nli0i; reg nli0l; + reg nli0O; reg nli1i; reg nli1l; reg nli1O; - reg nll1li; - reg nll1ll; - reg nll1Ol; - reg nlliOi; - reg nlliOl; - reg nlliOO; - reg nlll0i; - reg nlll0l; - reg nlll0O; - reg nlll1i; - reg nlll1l; - reg nlll1O; - reg nlllii; - reg nlllil; - reg nllliO; - reg nlllli; - reg nlllll; - reg nllllO; - reg nlllOi; - reg nlllOl; - reg nlllOO; - reg nllO0i; - reg nllO0l; - reg nllO0O; - reg nllO1i; - reg nllO1l; - reg nllO1O; - reg nlOilO; - reg nlOiOi; - reg nlOiOl; - reg nlOiOO; - reg nlOl0i; - reg nlOl0l; - reg nlOl0O; - reg nlOl1i; - reg nlOl1l; - reg nlOl1O; - reg nlOlil; - reg nlOliO; - reg nlOlli; - reg nlOlll; - reg nlOllO; - reg nlOlOi; - reg nlOlOl; - reg nlOlOO; - wire wire_n00i_dataout; - wire wire_n00l_dataout; - wire wire_n00O_dataout; - wire wire_n01i_dataout; - wire wire_n01iO_dataout; - wire wire_n01l_dataout; - wire wire_n01O_dataout; - wire wire_n01Oi_dataout; + reg nliii; + reg nliil; + reg nliiO; + reg nlili; + reg nlill; + reg nlilO; + reg nliOi; + reg nlOOOi; + reg nlOOOl; + reg nlOOOO; + wire wire_n0OO_ENA; wire wire_n0i_dataout; - wire wire_n0ii_dataout; - wire wire_n0il_dataout; - wire wire_n0ilO_dataout; - wire wire_n0iO_dataout; - wire wire_n0iOi_dataout; - wire wire_n0iOl_dataout; - wire wire_n0iOO_dataout; wire wire_n0l_dataout; - wire wire_n0l0i_dataout; - wire wire_n0l0l_dataout; - wire wire_n0l0O_dataout; - wire wire_n0l1i_dataout; - wire wire_n0l1l_dataout; - wire wire_n0l1O_dataout; - wire wire_n0li_dataout; - wire wire_n0lii_dataout; - wire wire_n0lil_dataout; - wire wire_n0liO_dataout; - wire wire_n0ll_dataout; - wire wire_n0lli_dataout; - wire wire_n0lll_dataout; - wire wire_n0llO_dataout; - wire wire_n0lO_dataout; - wire wire_n0lOi_dataout; - wire wire_n0lOl_dataout; - wire wire_n0lOO_dataout; wire wire_n0O_dataout; - wire wire_n0O0i_dataout; - wire wire_n0O0l_dataout; - wire wire_n0O0O_dataout; - wire wire_n0O1i_dataout; - wire wire_n0O1l_dataout; - wire wire_n0O1O_dataout; - wire wire_n0Oi_dataout; - wire wire_n0Oii_dataout; - wire wire_n0Oil_dataout; - wire wire_n0Ol_dataout; - wire wire_n0OO_dataout; - wire wire_n100i_dataout; - wire wire_n100l_dataout; - wire wire_n100O_dataout; - wire wire_n10i_dataout; - wire wire_n10l_dataout; - wire wire_n10li_dataout; - wire wire_n10lO_dataout; - wire wire_n10O_dataout; - wire wire_n10Oi_dataout; - wire wire_n10Ol_dataout; - wire wire_n10OO_dataout; - wire wire_n11i_dataout; - wire wire_n11l_dataout; - wire wire_n11O_dataout; wire wire_n1i_dataout; - wire wire_n1ii_dataout; - wire wire_n1iil_dataout; - wire wire_n1iiO_dataout; - wire wire_n1il_dataout; - wire wire_n1ili_dataout; - wire wire_n1ill_dataout; - wire wire_n1ilO_dataout; - wire wire_n1iO_dataout; - wire wire_n1iOi_dataout; - wire wire_n1iOl_dataout; wire wire_n1l_dataout; - wire wire_n1ll_dataout; - wire wire_n1lO_dataout; wire wire_n1O_dataout; - wire wire_n1O0i_dataout; - wire wire_n1O0l_dataout; - wire wire_n1O0O_dataout; - wire wire_n1O1i_dataout; - wire wire_n1O1l_dataout; - wire wire_n1O1O_dataout; - wire wire_n1Oi_dataout; - wire wire_n1Oii_dataout; - wire wire_n1Oil_dataout; - wire wire_n1OiO_dataout; - wire wire_n1Ol_dataout; - wire wire_n1Oli_dataout; - wire wire_n1Oll_dataout; - wire wire_n1OlO_dataout; - wire wire_n1OO_dataout; - wire wire_n1OOi_dataout; - wire wire_n1OOl_dataout; - wire wire_n1OOO_dataout; wire wire_ni_dataout; wire wire_ni0i_dataout; - wire wire_ni0il_dataout; - wire wire_ni0iO_dataout; wire wire_ni0l_dataout; - wire wire_ni0li_dataout; - wire wire_ni0ll_dataout; - wire wire_ni0lO_dataout; wire wire_ni0O_dataout; - wire wire_ni0Oi_dataout; - wire wire_ni0Ol_dataout; - wire wire_ni0OO_dataout; - wire wire_ni1i_dataout; wire wire_ni1l_dataout; wire wire_ni1O_dataout; wire wire_nii_dataout; - wire wire_nii0i_dataout; - wire wire_nii0l_dataout; - wire wire_nii0O_dataout; - wire wire_nii1i_dataout; - wire wire_nii1l_dataout; - wire wire_nii1O_dataout; wire wire_niii_dataout; - wire wire_niiii_dataout; - wire wire_niiil_dataout; - wire wire_niiiO_dataout; wire wire_niil_dataout; - wire wire_niili_dataout; - wire wire_niill_dataout; - wire wire_niilO_dataout; wire wire_niiO_dataout; - wire wire_niiOi_dataout; - wire wire_niiOl_dataout; - wire wire_niiOO_dataout; wire wire_nil_dataout; - wire wire_nil1i_dataout; - wire wire_nil1l_dataout; - wire wire_nil1O_dataout; wire wire_nili_dataout; wire wire_nill_dataout; - wire wire_nilO_dataout; wire wire_niO_dataout; wire wire_niOi_dataout; wire wire_niOl_dataout; wire wire_niOO_dataout; wire wire_nl_dataout; + wire wire_nl00i_dataout; + wire wire_nl00l_dataout; + wire wire_nl00O_dataout; + wire wire_nl01O_dataout; wire wire_nl0i_dataout; + wire wire_nl0ii_dataout; + wire wire_nl0il_dataout; + wire wire_nl0iO_dataout; wire wire_nl0l_dataout; + wire wire_nl0li_dataout; + wire wire_nl0ll_dataout; + wire wire_nl0lO_dataout; wire wire_nl0O_dataout; + wire wire_nl0Oi_dataout; wire wire_nl1i_dataout; wire wire_nl1l_dataout; wire wire_nl1O_dataout; @@ -822,65 +225,71 @@ module ip_fp_add wire wire_nlii_dataout; wire wire_nlil_dataout; wire wire_nliO_dataout; + wire wire_nliOl_dataout; + wire wire_nliOO_dataout; wire wire_nll_dataout; - wire wire_nll00l_dataout; - wire wire_nll00O_dataout; - wire wire_nll0ii_dataout; - wire wire_nll0il_dataout; - wire wire_nll0iO_dataout; - wire wire_nll0li_dataout; - wire wire_nll0ll_dataout; - wire wire_nll0lO_dataout; - wire wire_nll0Oi_dataout; - wire wire_nll0Ol_dataout; - wire wire_nll0OO_dataout; + wire wire_nll0i_dataout; + wire wire_nll0l_dataout; + wire wire_nll0O_dataout; + wire wire_nll1i_dataout; + wire wire_nll1l_dataout; + wire wire_nll1O_dataout; wire wire_nlli_dataout; - wire wire_nlli0i_dataout; - wire wire_nlli0l_dataout; - wire wire_nlli0O_dataout; - wire wire_nlli1i_dataout; - wire wire_nlli1l_dataout; - wire wire_nlli1O_dataout; - wire wire_nlliii_dataout; - wire wire_nlliil_dataout; - wire wire_nlliiO_dataout; - wire wire_nllili_dataout; - wire wire_nllill_dataout; - wire wire_nllilO_dataout; + wire wire_nllii_dataout; + wire wire_nllil_dataout; + wire wire_nlliO_dataout; wire wire_nlll_dataout; + wire wire_nllli_dataout; + wire wire_nllll_dataout; wire wire_nllO_dataout; wire wire_nlO_dataout; - wire wire_nlO0i_dataout; - wire wire_nlO0l_dataout; - wire wire_nlO0O_dataout; - wire wire_nlO1l_dataout; - wire wire_nlO1O_dataout; wire wire_nlOi_dataout; - wire wire_nlOii_dataout; - wire wire_nlOil_dataout; - wire wire_nlOiO_dataout; wire wire_nlOl_dataout; - wire wire_nlOli_dataout; - wire wire_nlOll_dataout; - wire wire_nlOlO_dataout; wire wire_nlOO_dataout; - wire wire_nlOOi_dataout; - wire wire_nlOOl_dataout; - wire wire_nlOOO_dataout; - wire [27:0] wire_n011i_o; - wire [1:0] wire_n01li_o; - wire [0:0] wire_n01ll_o; - wire [11:0] wire_n0Oli_o; - wire [2:0] wire_n10ii_o; - wire [2:0] wire_n10il_o; - wire [9:0] wire_nli0O_o; - wire [27:0] wire_nliii_o; - wire [10:0] wire_nlOlii_o; - wire [8:0] wire_nlOO1l_o; - wire [33:0] wire_nO_o; + wire [14:0] wire_n1li_o; + wire [7:0] wire_niO0O_o; + wire [5:0] wire_niOii_o; + wire [14:0] wire_nl0Ol_o; + wire [8:0] wire_nlllO_o; + wire [6:0] wire_nlOll_o; + wire [17:0] wire_nO_o; + wire wire_n10i_o; + wire wire_n10l_o; + wire wire_n10O_o; + wire wire_n11i_o; + wire wire_n11l_o; + wire wire_n11O_o; + wire wire_n1ii_o; + wire wire_n1il_o; + wire wire_n1iO_o; + wire wire_ni00l_o; + wire wire_ni00O_o; + wire wire_ni0ii_o; + wire wire_ni0il_o; + wire wire_ni0iO_o; + wire wire_ni0li_o; + wire wire_ni0ll_o; + wire wire_ni0lO_o; + wire wire_ni0Oi_o; + wire wire_ni0Ol_o; + wire wire_ni0OO_o; + wire wire_nii0i_o; + wire wire_nii0l_o; + wire wire_nii0O_o; + wire wire_nii1i_o; + wire wire_nii1l_o; + wire wire_nii1O_o; + wire wire_niiil_o; + wire wire_niiiO_o; + wire wire_niiOi_o; + wire wire_niiOl_o; + wire wire_niiOO_o; wire wire_nil0i_o; wire wire_nil0l_o; wire wire_nil0O_o; + wire wire_nil1i_o; + wire wire_nil1l_o; + wire wire_nil1O_o; wire wire_nilii_o; wire wire_nilil_o; wire wire_niliO_o; @@ -892,360 +301,44 @@ module ip_fp_add wire wire_nilOO_o; wire wire_niO0i_o; wire wire_niO0l_o; - wire wire_niO0O_o; wire wire_niO1i_o; wire wire_niO1l_o; wire wire_niO1O_o; - wire wire_niOii_o; - wire wire_niOil_o; - wire wire_niOiO_o; - wire wire_niOli_o; - wire wire_niOll_o; - wire wire_niOlO_o; - wire wire_niOOi_o; - wire wire_niOOl_o; - wire wire_niOOO_o; - wire wire_nl00i_o; - wire wire_nl00l_o; - wire wire_nl00O_o; - wire wire_nl01i_o; - wire wire_nl01l_o; - wire wire_nl01O_o; - wire wire_nl0ii_o; - wire wire_nl0il_o; - wire wire_nl0iO_o; - wire wire_nl0li_o; - wire wire_nl10i_o; - wire wire_nl10l_o; - wire wire_nl10O_o; - wire wire_nl11i_o; - wire wire_nl11l_o; - wire wire_nl11O_o; - wire wire_nl1ii_o; - wire wire_nl1il_o; - wire wire_nl1iO_o; - wire wire_nl1li_o; - wire wire_nl1ll_o; - wire wire_nl1lO_o; - wire wire_nl1Oi_o; - wire wire_nl1Ol_o; - wire wire_nl1OO_o; - wire wire_nliliO_o; - wire wire_nlilli_o; - wire wire_nlilll_o; - wire wire_nlillO_o; - wire wire_nlilOi_o; - wire wire_nlilOl_o; - wire wire_nlilOO_o; - wire wire_nliO0i_o; - wire wire_nliO0l_o; - wire wire_nliO0O_o; - wire wire_nliO1i_o; - wire wire_nliO1l_o; - wire wire_nliO1O_o; - wire wire_nliOii_o; - wire wire_nliOil_o; - wire wire_nliOiO_o; - wire wire_nliOli_o; - wire wire_nliOll_o; - wire wire_nliOlO_o; - wire wire_nliOOi_o; - wire wire_nliOOl_o; - wire wire_nliOOO_o; - wire wire_nll01i_o; - wire wire_nll10i_o; - wire wire_nll10l_o; - wire wire_nll10O_o; - wire wire_nll11i_o; - wire wire_nll11l_o; - wire wire_nll11O_o; - wire wire_nll1ii_o; - wire wire_nll1il_o; - wire wire_nll1iO_o; - wire wire_nll1lO_o; - wire wire_nll1Oi_o; - wire wire_nll1OO_o; - wire wire_nllOii_o; - wire wire_nllOil_o; - wire wire_nllOiO_o; - wire wire_nllOli_o; - wire wire_nllOll_o; - wire wire_nllOlO_o; - wire wire_nllOOi_o; - wire wire_nllOOl_o; - wire wire_nllOOO_o; - wire wire_nlO00i_o; - wire wire_nlO00l_o; - wire wire_nlO00O_o; - wire wire_nlO01i_o; - wire wire_nlO01l_o; - wire wire_nlO01O_o; - wire wire_nlO0ii_o; - wire wire_nlO0il_o; - wire wire_nlO0iO_o; - wire wire_nlO0li_o; - wire wire_nlO0ll_o; - wire wire_nlO0lO_o; - wire wire_nlO0Oi_o; - wire wire_nlO0Ol_o; - wire wire_nlO0OO_o; - wire wire_nlO10i_o; - wire wire_nlO10l_o; - wire wire_nlO10O_o; - wire wire_nlO11i_o; - wire wire_nlO11l_o; - wire wire_nlO11O_o; - wire wire_nlO1ii_o; - wire wire_nlO1il_o; - wire wire_nlO1iO_o; - wire wire_nlO1li_o; - wire wire_nlO1ll_o; - wire wire_nlO1lO_o; - wire wire_nlO1Oi_o; - wire wire_nlO1Ol_o; - wire wire_nlO1OO_o; - wire wire_nlOi0i_o; - wire wire_nlOi0l_o; - wire wire_nlOi0O_o; - wire wire_nlOi1i_o; - wire wire_nlOi1l_o; - wire wire_nlOi1O_o; - wire wire_nlOiii_o; - wire wire_nlOiil_o; - wire wire_nlOiiO_o; - wire wire_nlOili_o; - wire wire_nlOill_o; - wire n0OilO; - wire n0OiOi; - wire n0OiOl; - wire n0OiOO; - wire n0Ol0i; - wire n0Ol0l; - wire n0Ol0O; - wire n0Ol1i; - wire n0Ol1l; - wire n0Ol1O; - wire n0Olii; - wire n0Olil; - wire n0OliO; - wire n0Olli; - wire n0Olll; + wire wire_nllOi_o; + wire wire_nllOl_o; + wire wire_nllOO_o; + wire wire_nlO0i_o; + wire wire_nlO0l_o; + wire wire_nlO0O_o; + wire wire_nlO1i_o; + wire wire_nlO1l_o; + wire wire_nlO1O_o; + wire wire_nlOii_o; + wire wire_nlOil_o; + wire wire_nlOiO_o; + wire wire_nlOli_o; + wire wire_nlOlO_o; + wire wire_nlOOi_o; + wire wire_nlOOl_o; + wire wire_nlOOO_o; + wire nlOliO; + wire nlOlli; + wire nlOlll; + wire nlOllO; + wire nlOlOi; + wire nlOlOl; + wire nlOlOO; + wire nlOO0i; + wire nlOO0l; + wire nlOO0O; + wire nlOO1i; + wire nlOO1l; + wire nlOO1O; + wire nlOOii; + wire nlOOil; + wire nlOOiO; + wire nlOOli; - altera_syncram ni0Oii - ( - .aclr1(areset), - .address_a({n011O, n1lOO}), - .address_b({n01ii, n010O}), - .clock0(clk), - .clock1(clk), - .clocken0(1'b1), - .clocken1(n01il), - .data_a({wire_ni1O_dataout, wire_ni1l_dataout, wire_ni1i_dataout, wire_n0OO_dataout, wire_n0Ol_dataout, wire_n0Oi_dataout, wire_n0lO_dataout, wire_n0ll_dataout, wire_n0li_dataout, wire_n0iO_dataout, wire_n0il_dataout, wire_n0ii_dataout, wire_n00O_dataout, wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout, wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout, wire_n1ll_dataout}), - .eccstatus(), - .q_a(), - .q_b(wire_ni0Oii_q_b), - .wren_a(1'b1), - .aclr0(), - .address2_a(), - .address2_b(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .clocken2(), - .clocken3(), - .data_b(), - .eccencbypass(), - .eccencparity(), - .rden_a(), - .rden_b(), - .sclr(), - .wren_b() - ); - defparam - ni0Oii.address_aclr_a = "NONE", - ni0Oii.address_aclr_b = "NONE", - ni0Oii.address_reg_b = "CLOCK0", - ni0Oii.byte_size = 0, - ni0Oii.byteena_reg_b = "CLOCK0", - ni0Oii.clock_enable_core_a = "USE_INPUT_CLKEN", - ni0Oii.clock_enable_core_b = "USE_INPUT_CLKEN", - ni0Oii.clock_enable_input_a = "NORMAL", - ni0Oii.clock_enable_input_b = "NORMAL", - ni0Oii.clock_enable_output_a = "NORMAL", - ni0Oii.clock_enable_output_b = "NORMAL", - ni0Oii.ecc_pipeline_stage_enabled = "FALSE", - ni0Oii.enable_coherent_read = "FALSE", - ni0Oii.enable_ecc = "FALSE", - ni0Oii.enable_ecc_encoder_bypass = "FALSE", - ni0Oii.enable_force_to_zero = "FALSE", - ni0Oii.implement_in_les = "OFF", - ni0Oii.indata_reg_b = "CLOCK0", - ni0Oii.init_file_layout = "PORT_A", - ni0Oii.intended_device_family = "Cyclone V", - ni0Oii.numwords_a = 3, - ni0Oii.numwords_b = 3, - ni0Oii.operation_mode = "DUAL_PORT", - ni0Oii.outdata_aclr_a = "NONE", - ni0Oii.outdata_aclr_b = "CLEAR1", - ni0Oii.outdata_reg_a = "UNREGISTERED", - ni0Oii.outdata_reg_b = "CLOCK1", - ni0Oii.outdata_sclr_a = "NONE", - ni0Oii.outdata_sclr_b = "NONE", - ni0Oii.power_up_uninitialized = "TRUE", - ni0Oii.ram_block_type = "MLAB", - ni0Oii.rdcontrol_reg_b = "CLOCK0", - ni0Oii.read_during_write_mode_mixed_ports = "DONT_CARE", - ni0Oii.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", - ni0Oii.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", - ni0Oii.width_a = 23, - ni0Oii.width_b = 23, - ni0Oii.width_byteena_a = 1, - ni0Oii.width_byteena_b = 1, - ni0Oii.width_eccencparity = 8, - ni0Oii.width_eccstatus = 2, - ni0Oii.widthad2_a = 1, - ni0Oii.widthad2_b = 1, - ni0Oii.widthad_a = 2, - ni0Oii.widthad_b = 2, - ni0Oii.lpm_hint = "ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES=DONT CARE, ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS=AUTO, ACF_DISABLE_MLAB_RAM_USE=FALSE, ACF_IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE=FALSE, CLOCK_DUTY_CYCLE_DEPENDENCE=AUTO, ENABLE_RUNTIME_MOD=NO, LOW_POWER_MODE=AUTO, RDEN_POWER_OPTIMIZATION=ON"; - altera_syncram nil10l - ( - .aclr1(areset), - .address_a({n11Oi, n11lO, nlOO1i}), - .address_b({n101l, n101i, n11OO}), - .clock0(clk), - .clock1(clk), - .clocken0(1'b1), - .clocken1(n101O), - .data_a({wire_nill_dataout, wire_nili_dataout, wire_niiO_dataout, wire_niil_dataout, wire_niii_dataout, wire_ni0O_dataout, wire_ni0l_dataout, wire_ni0i_dataout}), - .eccstatus(), - .q_a(), - .q_b(wire_nil10l_q_b), - .wren_a(1'b1), - .aclr0(), - .address2_a(), - .address2_b(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .clocken2(), - .clocken3(), - .data_b(), - .eccencbypass(), - .eccencparity(), - .rden_a(), - .rden_b(), - .sclr(), - .wren_b() - ); - defparam - nil10l.address_aclr_a = "NONE", - nil10l.address_aclr_b = "NONE", - nil10l.address_reg_b = "CLOCK0", - nil10l.byte_size = 0, - nil10l.byteena_reg_b = "CLOCK0", - nil10l.clock_enable_core_a = "USE_INPUT_CLKEN", - nil10l.clock_enable_core_b = "USE_INPUT_CLKEN", - nil10l.clock_enable_input_a = "NORMAL", - nil10l.clock_enable_input_b = "NORMAL", - nil10l.clock_enable_output_a = "NORMAL", - nil10l.clock_enable_output_b = "NORMAL", - nil10l.ecc_pipeline_stage_enabled = "FALSE", - nil10l.enable_coherent_read = "FALSE", - nil10l.enable_ecc = "FALSE", - nil10l.enable_ecc_encoder_bypass = "FALSE", - nil10l.enable_force_to_zero = "FALSE", - nil10l.implement_in_les = "OFF", - nil10l.indata_reg_b = "CLOCK0", - nil10l.init_file_layout = "PORT_A", - nil10l.intended_device_family = "Cyclone V", - nil10l.numwords_a = 6, - nil10l.numwords_b = 6, - nil10l.operation_mode = "DUAL_PORT", - nil10l.outdata_aclr_a = "NONE", - nil10l.outdata_aclr_b = "CLEAR1", - nil10l.outdata_reg_a = "UNREGISTERED", - nil10l.outdata_reg_b = "CLOCK1", - nil10l.outdata_sclr_a = "NONE", - nil10l.outdata_sclr_b = "NONE", - nil10l.power_up_uninitialized = "TRUE", - nil10l.ram_block_type = "MLAB", - nil10l.rdcontrol_reg_b = "CLOCK0", - nil10l.read_during_write_mode_mixed_ports = "DONT_CARE", - nil10l.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", - nil10l.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", - nil10l.width_a = 8, - nil10l.width_b = 8, - nil10l.width_byteena_a = 1, - nil10l.width_byteena_b = 1, - nil10l.width_eccencparity = 8, - nil10l.width_eccstatus = 2, - nil10l.widthad2_a = 1, - nil10l.widthad2_b = 1, - nil10l.widthad_a = 3, - nil10l.widthad_b = 3, - nil10l.lpm_hint = "ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES=DONT CARE, ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS=AUTO, ACF_DISABLE_MLAB_RAM_USE=FALSE, ACF_IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE=FALSE, CLOCK_DUTY_CYCLE_DEPENDENCE=AUTO, ENABLE_RUNTIME_MOD=NO, LOW_POWER_MODE=AUTO, RDEN_POWER_OPTIMIZATION=ON"; - initial - begin - n010O = 0; - end - always @ ( posedge clk or posedge areset) - begin - if (areset == 1'b1) - begin - n010O <= 0; - end - else if (n010i == 1'b0) - begin - n010O <= wire_n01li_o[0]; - end - end - initial - begin - n011O = 0; - n11Oi = 0; - nll00i = 0; - nlOO1i = 0; - end - always @ ( posedge clk or posedge areset) - begin - if (areset == 1'b1) - begin - n011O <= 1; - n11Oi <= 1; - nll00i <= 1; - nlOO1i <= 1; - end - else - begin - n011O <= n01ii; - n11Oi <= n101l; - nll00i <= wire_nll1lO_o; - nlOO1i <= n11OO; - end - end - event n011O_event; - event n11Oi_event; - event nll00i_event; - event nlOO1i_event; - initial - #1 ->n011O_event; - initial - #1 ->n11Oi_event; - initial - #1 ->nll00i_event; - initial - #1 ->nlOO1i_event; - always @(n011O_event) - n011O <= 1; - always @(n11Oi_event) - n11Oi <= 1; - always @(nll00i_event) - nll00i <= 1; - always @(nlOO1i_event) - nlOO1i <= 1; initial begin n000i = 0; @@ -1264,50 +357,58 @@ module ip_fp_add n00Ol = 0; n00OO = 0; n010i = 0; + n010l = 0; + n010O = 0; + n011i = 0; + n011l = 0; + n011O = 0; n01ii = 0; n01il = 0; + n01iO = 0; + n01li = 0; + n01ll = 0; n01lO = 0; + n01Oi = 0; n01Ol = 0; n01OO = 0; - n0i0i = 0; - n0i0l = 0; - n0i0O = 0; n0i1i = 0; n0i1l = 0; - n0i1O = 0; - n0iii = 0; - n0iil = 0; - n0iiO = 0; - n0ili = 0; - n0ill = 0; - n0OiO = 0; - n0Oll = 0; - n0OlO = 0; - n0OlOl = 0; - n0OlOO = 0; - n0OO0i = 0; - n0OO0l = 0; - n0OO0O = 0; - n0OO1i = 0; - n0OO1l = 0; - n0OO1O = 0; - n0OOi = 0; - n0OOii = 0; - n0OOil = 0; - n0OOiO = 0; - n0OOl = 0; - n0OOli = 0; - n0OOll = 0; - n0OOlO = 0; - n0OOO = 0; - n0OOOi = 0; - n0OOOl = 0; - n0OOOO = 0; + n0ii = 0; + n0il = 0; + n0iO = 0; + n0li = 0; + n0ll = 0; + n0lO = 0; + n0Oi = 0; + n0Ol = 0; + n100i = 0; + n100l = 0; + n100O = 0; n101i = 0; n101l = 0; n101O = 0; + n10ii = 0; + n10il = 0; n10iO = 0; + n10li = 0; + n10ll = 0; + n10lO = 0; + n10Oi = 0; + n10Ol = 0; + n10OO = 0; + n110i = 0; + n110l = 0; + n110O = 0; + n111i = 0; + n111l = 0; + n111O = 0; + n11ii = 0; + n11il = 0; + n11iO = 0; + n11li = 0; + n11ll = 0; n11lO = 0; + n11Oi = 0; n11Ol = 0; n11OO = 0; n1i0i = 0; @@ -1317,6 +418,13 @@ module ip_fp_add n1i1l = 0; n1i1O = 0; n1iii = 0; + n1iil = 0; + n1iiO = 0; + n1ili = 0; + n1ill = 0; + n1ilO = 0; + n1iOi = 0; + n1iOl = 0; n1iOO = 0; n1l0i = 0; n1l0l = 0; @@ -1333,544 +441,41 @@ module ip_fp_add n1lOi = 0; n1lOl = 0; n1lOO = 0; - ni000i = 0; - ni000l = 0; - ni000O = 0; - ni001i = 0; - ni001l = 0; - ni001O = 0; - ni00i = 0; - ni00ii = 0; - ni00il = 0; - ni00iO = 0; - ni00l = 0; - ni00li = 0; - ni00ll = 0; - ni00lO = 0; - ni00O = 0; - ni00Oi = 0; - ni00Ol = 0; - ni00OO = 0; - ni010i = 0; - ni010l = 0; - ni010O = 0; - ni011i = 0; - ni011l = 0; - ni011O = 0; - ni01i = 0; - ni01ii = 0; - ni01il = 0; - ni01iO = 0; - ni01l = 0; - ni01li = 0; - ni01ll = 0; - ni01lO = 0; - ni01O = 0; - ni01Oi = 0; - ni01Ol = 0; - ni01OO = 0; - ni0i0i = 0; - ni0i0l = 0; - ni0i0O = 0; - ni0i1i = 0; - ni0i1l = 0; - ni0i1O = 0; - ni0ii = 0; - ni0iii = 0; - ni0iil = 0; - ni0iiO = 0; - ni0ili = 0; - ni0ill = 0; - ni0ilO = 0; - ni0iOi = 0; - ni0iOl = 0; - ni0iOO = 0; - ni0l0i = 0; - ni0l0l = 0; - ni0l0O = 0; - ni0l1i = 0; - ni0l1l = 0; - ni0l1O = 0; - ni0lii = 0; - ni0lil = 0; - ni0liO = 0; - ni0lli = 0; - ni0lll = 0; - ni0llO = 0; - ni0lOi = 0; - ni0lOl = 0; - ni0lOO = 0; - ni0O0i = 0; - ni0O0l = 0; - ni0O0O = 0; - ni0O1i = 0; - ni0O1l = 0; - ni0O1O = 0; - ni0Oil = 0; - ni0OiO = 0; - ni0Oli = 0; - ni0Oll = 0; - ni0OlO = 0; - ni0OOi = 0; - ni0OOl = 0; - ni0OOO = 0; - ni100i = 0; - ni100l = 0; - ni100O = 0; - ni101i = 0; - ni101l = 0; - ni101O = 0; - ni10i = 0; - ni10ii = 0; - ni10il = 0; - ni10iO = 0; - ni10l = 0; - ni10li = 0; - ni10ll = 0; - ni10lO = 0; - ni10O = 0; - ni10Oi = 0; - ni10Ol = 0; - ni10OO = 0; - ni110i = 0; - ni110l = 0; - ni110O = 0; - ni111i = 0; - ni111l = 0; - ni111O = 0; - ni11i = 0; - ni11ii = 0; - ni11il = 0; - ni11iO = 0; - ni11l = 0; - ni11li = 0; - ni11ll = 0; - ni11lO = 0; - ni11O = 0; - ni11Oi = 0; - ni11Ol = 0; - ni11OO = 0; - ni1i0i = 0; - ni1i0l = 0; - ni1i0O = 0; - ni1i1i = 0; - ni1i1l = 0; - ni1i1O = 0; - ni1ii = 0; - ni1iii = 0; - ni1iil = 0; - ni1iiO = 0; - ni1il = 0; - ni1ili = 0; - ni1ill = 0; - ni1ilO = 0; - ni1iO = 0; - ni1iOi = 0; - ni1iOl = 0; - ni1iOO = 0; - ni1l0i = 0; - ni1l0l = 0; - ni1l0O = 0; - ni1l1i = 0; - ni1l1l = 0; - ni1l1O = 0; - ni1li = 0; - ni1lii = 0; - ni1lil = 0; - ni1liO = 0; - ni1ll = 0; - ni1lli = 0; - ni1lll = 0; - ni1llO = 0; - ni1lO = 0; - ni1lOi = 0; - ni1lOl = 0; - ni1lOO = 0; - ni1O0i = 0; - ni1O0l = 0; - ni1O0O = 0; - ni1O1i = 0; - ni1O1l = 0; - ni1O1O = 0; - ni1Oi = 0; - ni1Oii = 0; - ni1Oil = 0; - ni1OiO = 0; - ni1Ol = 0; - ni1Oli = 0; - ni1Oll = 0; - ni1OlO = 0; - ni1OO = 0; - ni1OOi = 0; - ni1OOl = 0; - ni1OOO = 0; - nii00i = 0; - nii00l = 0; - nii00O = 0; - nii01i = 0; - nii01l = 0; - nii01O = 0; - nii0ii = 0; - nii0il = 0; - nii0iO = 0; - nii0li = 0; - nii0ll = 0; - nii0lO = 0; - nii0Oi = 0; - nii0Ol = 0; - nii0OO = 0; - nii10i = 0; - nii10l = 0; - nii10O = 0; - nii11i = 0; - nii11l = 0; - nii11O = 0; - nii1ii = 0; - nii1il = 0; - nii1iO = 0; - nii1li = 0; - nii1ll = 0; - nii1lO = 0; - nii1Oi = 0; - nii1Ol = 0; - nii1OO = 0; - niii0i = 0; - niii0l = 0; - niii0O = 0; - niii1i = 0; - niii1l = 0; - niii1O = 0; - niiiii = 0; - niiiil = 0; - niiiiO = 0; - niiili = 0; - niiill = 0; - niiilO = 0; - niiiOi = 0; - niiiOl = 0; - niiiOO = 0; - niil0i = 0; - niil0l = 0; - niil0O = 0; - niil1i = 0; - niil1l = 0; - niil1O = 0; - niilii = 0; - niilil = 0; - niiliO = 0; - niilli = 0; - niilll = 0; - niillO = 0; - niilOi = 0; - niilOl = 0; - niilOO = 0; - niiO0i = 0; - niiO0l = 0; - niiO0O = 0; - niiO1i = 0; - niiO1l = 0; - niiO1O = 0; - niiOii = 0; - niiOil = 0; - niiOiO = 0; - niiOli = 0; - niiOll = 0; - niiOlO = 0; - niiOOi = 0; - niiOOl = 0; - niiOOO = 0; - nil00i = 0; - nil00l = 0; - nil00O = 0; - nil01i = 0; - nil01l = 0; - nil01O = 0; - nil0ii = 0; - nil0il = 0; - nil0iO = 0; - nil0li = 0; - nil0ll = 0; - nil0lO = 0; - nil0Oi = 0; - nil0Ol = 0; - nil0OO = 0; - nil10i = 0; - nil10O = 0; - nil11i = 0; - nil11l = 0; - nil11O = 0; - nil1ii = 0; - nil1il = 0; - nil1iO = 0; - nil1li = 0; - nil1ll = 0; - nil1lO = 0; - nil1Oi = 0; - nil1Ol = 0; - nil1OO = 0; - nili0i = 0; - nili0l = 0; - nili0O = 0; - nili1i = 0; - nili1l = 0; - nili1O = 0; - niliii = 0; - niliil = 0; - niliiO = 0; - nilili = 0; - nilill = 0; - nililO = 0; - niliOi = 0; - niliOl = 0; - niliOO = 0; - nill0i = 0; - nill0l = 0; - nill0O = 0; - nill1i = 0; - nill1l = 0; - nill1O = 0; - nillii = 0; - nillil = 0; - nilliO = 0; - nillli = 0; - nillll = 0; - nilllO = 0; - nillOi = 0; - nillOl = 0; - nillOO = 0; - nilO0i = 0; - nilO0l = 0; - nilO0O = 0; - nilO1i = 0; - nilO1l = 0; - nilO1O = 0; - nilOii = 0; - nilOil = 0; - nilOiO = 0; - nilOli = 0; - nilOll = 0; - nilOlO = 0; - nilOOi = 0; - nilOOl = 0; - nilOOO = 0; - niO00i = 0; - niO00l = 0; - niO00O = 0; - niO01i = 0; - niO01l = 0; - niO01O = 0; - niO0ii = 0; - niO0il = 0; - niO0iO = 0; - niO0li = 0; - niO0ll = 0; - niO0lO = 0; - niO0Oi = 0; - niO0Ol = 0; - niO0OO = 0; - niO10i = 0; - niO10l = 0; - niO10O = 0; - niO11i = 0; - niO11l = 0; - niO11O = 0; - niO1ii = 0; - niO1il = 0; - niO1iO = 0; - niO1li = 0; - niO1ll = 0; - niO1lO = 0; - niO1Oi = 0; - niO1Ol = 0; - niO1OO = 0; - niOi0i = 0; - niOi0l = 0; - niOi0O = 0; - niOi1i = 0; - niOi1l = 0; - niOi1O = 0; - niOiii = 0; - niOiil = 0; - niOiiO = 0; - niOili = 0; - niOill = 0; - niOilO = 0; - niOiOi = 0; - niOiOl = 0; - niOiOO = 0; - niOl0i = 0; - niOl0l = 0; - niOl0O = 0; - niOl1i = 0; - niOl1l = 0; - niOl1O = 0; - niOlii = 0; - niOlil = 0; - niOliO = 0; - niOlli = 0; - niOlll = 0; - niOllO = 0; - niOlOi = 0; - niOlOl = 0; - niOlOO = 0; - niOO0i = 0; - niOO0l = 0; - niOO0O = 0; - niOO1i = 0; - niOO1l = 0; - niOO1O = 0; - niOOii = 0; - niOOil = 0; - niOOiO = 0; - niOOli = 0; - niOOll = 0; - niOOlO = 0; - niOOOi = 0; - niOOOl = 0; - niOOOO = 0; - nl010i = 0; - nl010l = 0; - nl010O = 0; - nl011i = 0; - nl011l = 0; - nl011O = 0; - nl01ii = 0; - nl01il = 0; - nl01iO = 0; - nl01li = 0; - nl01ll = 0; - nl01lO = 0; - nl01Oi = 0; - nl01Ol = 0; - nl0ll = 0; - nl0lO = 0; - nl0Oi = 0; - nl0Ol = 0; + n1O0i = 0; + n1O0l = 0; + n1O0O = 0; + n1O1i = 0; + n1O1l = 0; + n1O1O = 0; + n1Oii = 0; + n1Oil = 0; + n1OiO = 0; + n1Oli = 0; + n1Oll = 0; + n1OlO = 0; + n1OOi = 0; + n1OOl = 0; + n1OOO = 0; + ni1i = 0; + niiii = 0; + niilO = 0; nl0OO = 0; - nl100i = 0; - nl100l = 0; - nl100O = 0; - nl101i = 0; - nl101l = 0; - nl101O = 0; - nl10ii = 0; - nl10il = 0; - nl10iO = 0; - nl10li = 0; - nl10ll = 0; - nl10lO = 0; - nl10Oi = 0; - nl10Ol = 0; - nl10OO = 0; - nl110i = 0; - nl110l = 0; - nl110O = 0; - nl111i = 0; - nl111l = 0; - nl111O = 0; - nl11ii = 0; - nl11il = 0; - nl11iO = 0; - nl11li = 0; - nl11ll = 0; - nl11lO = 0; - nl11Oi = 0; - nl11Ol = 0; - nl11OO = 0; - nl1i0i = 0; - nl1i0l = 0; - nl1i0O = 0; - nl1i1i = 0; - nl1i1l = 0; - nl1i1O = 0; - nl1iii = 0; - nl1iil = 0; - nl1iiO = 0; - nl1ili = 0; - nl1ill = 0; - nl1ilO = 0; - nl1iOi = 0; - nl1iOl = 0; - nl1iOO = 0; - nl1l0i = 0; - nl1l0l = 0; - nl1l0O = 0; - nl1l1i = 0; - nl1l1l = 0; - nl1l1O = 0; - nl1lii = 0; - nl1lil = 0; - nl1liO = 0; - nl1lli = 0; - nl1lll = 0; - nl1llO = 0; - nl1lOi = 0; - nl1lOl = 0; - nl1lOO = 0; - nl1O0i = 0; - nl1O0l = 0; - nl1O0O = 0; - nl1O1i = 0; - nl1O1l = 0; - nl1O1O = 0; - nl1Oii = 0; - nl1Oil = 0; - nl1OiO = 0; - nl1Oli = 0; - nl1Oll = 0; - nl1OlO = 0; - nl1OOi = 0; - nl1OOl = 0; - nl1OOO = 0; + nli0i = 0; nli0l = 0; + nli0O = 0; nli1i = 0; nli1l = 0; nli1O = 0; - nll1li = 0; - nll1ll = 0; - nll1Ol = 0; - nlliOi = 0; - nlliOl = 0; - nlliOO = 0; - nlll0i = 0; - nlll0l = 0; - nlll0O = 0; - nlll1i = 0; - nlll1l = 0; - nlll1O = 0; - nlllii = 0; - nlllil = 0; - nllliO = 0; - nlllli = 0; - nlllll = 0; - nllllO = 0; - nlllOi = 0; - nlllOl = 0; - nlllOO = 0; - nllO0i = 0; - nllO0l = 0; - nllO0O = 0; - nllO1i = 0; - nllO1l = 0; - nllO1O = 0; - nlOilO = 0; - nlOiOi = 0; - nlOiOl = 0; - nlOiOO = 0; - nlOl0i = 0; - nlOl0l = 0; - nlOl0O = 0; - nlOl1i = 0; - nlOl1l = 0; - nlOl1O = 0; - nlOlil = 0; - nlOliO = 0; - nlOlli = 0; - nlOlll = 0; - nlOllO = 0; - nlOlOi = 0; - nlOlOl = 0; - nlOlOO = 0; + nliii = 0; + nliil = 0; + nliiO = 0; + nlili = 0; + nlill = 0; + nlilO = 0; + nliOi = 0; + nlOOOi = 0; + nlOOOl = 0; + nlOOOO = 0; end always @ ( posedge clk or posedge areset) begin @@ -1892,50 +497,58 @@ module ip_fp_add n00Ol <= 0; n00OO <= 0; n010i <= 0; + n010l <= 0; + n010O <= 0; + n011i <= 0; + n011l <= 0; + n011O <= 0; n01ii <= 0; n01il <= 0; + n01iO <= 0; + n01li <= 0; + n01ll <= 0; n01lO <= 0; + n01Oi <= 0; n01Ol <= 0; n01OO <= 0; - n0i0i <= 0; - n0i0l <= 0; - n0i0O <= 0; n0i1i <= 0; n0i1l <= 0; - n0i1O <= 0; - n0iii <= 0; - n0iil <= 0; - n0iiO <= 0; - n0ili <= 0; - n0ill <= 0; - n0OiO <= 0; - n0Oll <= 0; - n0OlO <= 0; - n0OlOl <= 0; - n0OlOO <= 0; - n0OO0i <= 0; - n0OO0l <= 0; - n0OO0O <= 0; - n0OO1i <= 0; - n0OO1l <= 0; - n0OO1O <= 0; - n0OOi <= 0; - n0OOii <= 0; - n0OOil <= 0; - n0OOiO <= 0; - n0OOl <= 0; - n0OOli <= 0; - n0OOll <= 0; - n0OOlO <= 0; - n0OOO <= 0; - n0OOOi <= 0; - n0OOOl <= 0; - n0OOOO <= 0; + n0ii <= 0; + n0il <= 0; + n0iO <= 0; + n0li <= 0; + n0ll <= 0; + n0lO <= 0; + n0Oi <= 0; + n0Ol <= 0; + n100i <= 0; + n100l <= 0; + n100O <= 0; n101i <= 0; n101l <= 0; n101O <= 0; + n10ii <= 0; + n10il <= 0; n10iO <= 0; + n10li <= 0; + n10ll <= 0; + n10lO <= 0; + n10Oi <= 0; + n10Ol <= 0; + n10OO <= 0; + n110i <= 0; + n110l <= 0; + n110O <= 0; + n111i <= 0; + n111l <= 0; + n111O <= 0; + n11ii <= 0; + n11il <= 0; + n11iO <= 0; + n11li <= 0; + n11ll <= 0; n11lO <= 0; + n11Oi <= 0; n11Ol <= 0; n11OO <= 0; n1i0i <= 0; @@ -1945,6 +558,13 @@ module ip_fp_add n1i1l <= 0; n1i1O <= 0; n1iii <= 0; + n1iil <= 0; + n1iiO <= 0; + n1ili <= 0; + n1ill <= 0; + n1ilO <= 0; + n1iOi <= 0; + n1iOl <= 0; n1iOO <= 0; n1l0i <= 0; n1l0l <= 0; @@ -1961,2612 +581,896 @@ module ip_fp_add n1lOi <= 0; n1lOl <= 0; n1lOO <= 0; - ni000i <= 0; - ni000l <= 0; - ni000O <= 0; - ni001i <= 0; - ni001l <= 0; - ni001O <= 0; - ni00i <= 0; - ni00ii <= 0; - ni00il <= 0; - ni00iO <= 0; - ni00l <= 0; - ni00li <= 0; - ni00ll <= 0; - ni00lO <= 0; - ni00O <= 0; - ni00Oi <= 0; - ni00Ol <= 0; - ni00OO <= 0; - ni010i <= 0; - ni010l <= 0; - ni010O <= 0; - ni011i <= 0; - ni011l <= 0; - ni011O <= 0; - ni01i <= 0; - ni01ii <= 0; - ni01il <= 0; - ni01iO <= 0; - ni01l <= 0; - ni01li <= 0; - ni01ll <= 0; - ni01lO <= 0; - ni01O <= 0; - ni01Oi <= 0; - ni01Ol <= 0; - ni01OO <= 0; - ni0i0i <= 0; - ni0i0l <= 0; - ni0i0O <= 0; - ni0i1i <= 0; - ni0i1l <= 0; - ni0i1O <= 0; - ni0ii <= 0; - ni0iii <= 0; - ni0iil <= 0; - ni0iiO <= 0; - ni0ili <= 0; - ni0ill <= 0; - ni0ilO <= 0; - ni0iOi <= 0; - ni0iOl <= 0; - ni0iOO <= 0; - ni0l0i <= 0; - ni0l0l <= 0; - ni0l0O <= 0; - ni0l1i <= 0; - ni0l1l <= 0; - ni0l1O <= 0; - ni0lii <= 0; - ni0lil <= 0; - ni0liO <= 0; - ni0lli <= 0; - ni0lll <= 0; - ni0llO <= 0; - ni0lOi <= 0; - ni0lOl <= 0; - ni0lOO <= 0; - ni0O0i <= 0; - ni0O0l <= 0; - ni0O0O <= 0; - ni0O1i <= 0; - ni0O1l <= 0; - ni0O1O <= 0; - ni0Oil <= 0; - ni0OiO <= 0; - ni0Oli <= 0; - ni0Oll <= 0; - ni0OlO <= 0; - ni0OOi <= 0; - ni0OOl <= 0; - ni0OOO <= 0; - ni100i <= 0; - ni100l <= 0; - ni100O <= 0; - ni101i <= 0; - ni101l <= 0; - ni101O <= 0; - ni10i <= 0; - ni10ii <= 0; - ni10il <= 0; - ni10iO <= 0; - ni10l <= 0; - ni10li <= 0; - ni10ll <= 0; - ni10lO <= 0; - ni10O <= 0; - ni10Oi <= 0; - ni10Ol <= 0; - ni10OO <= 0; - ni110i <= 0; - ni110l <= 0; - ni110O <= 0; - ni111i <= 0; - ni111l <= 0; - ni111O <= 0; - ni11i <= 0; - ni11ii <= 0; - ni11il <= 0; - ni11iO <= 0; - ni11l <= 0; - ni11li <= 0; - ni11ll <= 0; - ni11lO <= 0; - ni11O <= 0; - ni11Oi <= 0; - ni11Ol <= 0; - ni11OO <= 0; - ni1i0i <= 0; - ni1i0l <= 0; - ni1i0O <= 0; - ni1i1i <= 0; - ni1i1l <= 0; - ni1i1O <= 0; - ni1ii <= 0; - ni1iii <= 0; - ni1iil <= 0; - ni1iiO <= 0; - ni1il <= 0; - ni1ili <= 0; - ni1ill <= 0; - ni1ilO <= 0; - ni1iO <= 0; - ni1iOi <= 0; - ni1iOl <= 0; - ni1iOO <= 0; - ni1l0i <= 0; - ni1l0l <= 0; - ni1l0O <= 0; - ni1l1i <= 0; - ni1l1l <= 0; - ni1l1O <= 0; - ni1li <= 0; - ni1lii <= 0; - ni1lil <= 0; - ni1liO <= 0; - ni1ll <= 0; - ni1lli <= 0; - ni1lll <= 0; - ni1llO <= 0; - ni1lO <= 0; - ni1lOi <= 0; - ni1lOl <= 0; - ni1lOO <= 0; - ni1O0i <= 0; - ni1O0l <= 0; - ni1O0O <= 0; - ni1O1i <= 0; - ni1O1l <= 0; - ni1O1O <= 0; - ni1Oi <= 0; - ni1Oii <= 0; - ni1Oil <= 0; - ni1OiO <= 0; - ni1Ol <= 0; - ni1Oli <= 0; - ni1Oll <= 0; - ni1OlO <= 0; - ni1OO <= 0; - ni1OOi <= 0; - ni1OOl <= 0; - ni1OOO <= 0; - nii00i <= 0; - nii00l <= 0; - nii00O <= 0; - nii01i <= 0; - nii01l <= 0; - nii01O <= 0; - nii0ii <= 0; - nii0il <= 0; - nii0iO <= 0; - nii0li <= 0; - nii0ll <= 0; - nii0lO <= 0; - nii0Oi <= 0; - nii0Ol <= 0; - nii0OO <= 0; - nii10i <= 0; - nii10l <= 0; - nii10O <= 0; - nii11i <= 0; - nii11l <= 0; - nii11O <= 0; - nii1ii <= 0; - nii1il <= 0; - nii1iO <= 0; - nii1li <= 0; - nii1ll <= 0; - nii1lO <= 0; - nii1Oi <= 0; - nii1Ol <= 0; - nii1OO <= 0; - niii0i <= 0; - niii0l <= 0; - niii0O <= 0; - niii1i <= 0; - niii1l <= 0; - niii1O <= 0; - niiiii <= 0; - niiiil <= 0; - niiiiO <= 0; - niiili <= 0; - niiill <= 0; - niiilO <= 0; - niiiOi <= 0; - niiiOl <= 0; - niiiOO <= 0; - niil0i <= 0; - niil0l <= 0; - niil0O <= 0; - niil1i <= 0; - niil1l <= 0; - niil1O <= 0; - niilii <= 0; - niilil <= 0; - niiliO <= 0; - niilli <= 0; - niilll <= 0; - niillO <= 0; - niilOi <= 0; - niilOl <= 0; - niilOO <= 0; - niiO0i <= 0; - niiO0l <= 0; - niiO0O <= 0; - niiO1i <= 0; - niiO1l <= 0; - niiO1O <= 0; - niiOii <= 0; - niiOil <= 0; - niiOiO <= 0; - niiOli <= 0; - niiOll <= 0; - niiOlO <= 0; - niiOOi <= 0; - niiOOl <= 0; - niiOOO <= 0; - nil00i <= 0; - nil00l <= 0; - nil00O <= 0; - nil01i <= 0; - nil01l <= 0; - nil01O <= 0; - nil0ii <= 0; - nil0il <= 0; - nil0iO <= 0; - nil0li <= 0; - nil0ll <= 0; - nil0lO <= 0; - nil0Oi <= 0; - nil0Ol <= 0; - nil0OO <= 0; - nil10i <= 0; - nil10O <= 0; - nil11i <= 0; - nil11l <= 0; - nil11O <= 0; - nil1ii <= 0; - nil1il <= 0; - nil1iO <= 0; - nil1li <= 0; - nil1ll <= 0; - nil1lO <= 0; - nil1Oi <= 0; - nil1Ol <= 0; - nil1OO <= 0; - nili0i <= 0; - nili0l <= 0; - nili0O <= 0; - nili1i <= 0; - nili1l <= 0; - nili1O <= 0; - niliii <= 0; - niliil <= 0; - niliiO <= 0; - nilili <= 0; - nilill <= 0; - nililO <= 0; - niliOi <= 0; - niliOl <= 0; - niliOO <= 0; - nill0i <= 0; - nill0l <= 0; - nill0O <= 0; - nill1i <= 0; - nill1l <= 0; - nill1O <= 0; - nillii <= 0; - nillil <= 0; - nilliO <= 0; - nillli <= 0; - nillll <= 0; - nilllO <= 0; - nillOi <= 0; - nillOl <= 0; - nillOO <= 0; - nilO0i <= 0; - nilO0l <= 0; - nilO0O <= 0; - nilO1i <= 0; - nilO1l <= 0; - nilO1O <= 0; - nilOii <= 0; - nilOil <= 0; - nilOiO <= 0; - nilOli <= 0; - nilOll <= 0; - nilOlO <= 0; - nilOOi <= 0; - nilOOl <= 0; - nilOOO <= 0; - niO00i <= 0; - niO00l <= 0; - niO00O <= 0; - niO01i <= 0; - niO01l <= 0; - niO01O <= 0; - niO0ii <= 0; - niO0il <= 0; - niO0iO <= 0; - niO0li <= 0; - niO0ll <= 0; - niO0lO <= 0; - niO0Oi <= 0; - niO0Ol <= 0; - niO0OO <= 0; - niO10i <= 0; - niO10l <= 0; - niO10O <= 0; - niO11i <= 0; - niO11l <= 0; - niO11O <= 0; - niO1ii <= 0; - niO1il <= 0; - niO1iO <= 0; - niO1li <= 0; - niO1ll <= 0; - niO1lO <= 0; - niO1Oi <= 0; - niO1Ol <= 0; - niO1OO <= 0; - niOi0i <= 0; - niOi0l <= 0; - niOi0O <= 0; - niOi1i <= 0; - niOi1l <= 0; - niOi1O <= 0; - niOiii <= 0; - niOiil <= 0; - niOiiO <= 0; - niOili <= 0; - niOill <= 0; - niOilO <= 0; - niOiOi <= 0; - niOiOl <= 0; - niOiOO <= 0; - niOl0i <= 0; - niOl0l <= 0; - niOl0O <= 0; - niOl1i <= 0; - niOl1l <= 0; - niOl1O <= 0; - niOlii <= 0; - niOlil <= 0; - niOliO <= 0; - niOlli <= 0; - niOlll <= 0; - niOllO <= 0; - niOlOi <= 0; - niOlOl <= 0; - niOlOO <= 0; - niOO0i <= 0; - niOO0l <= 0; - niOO0O <= 0; - niOO1i <= 0; - niOO1l <= 0; - niOO1O <= 0; - niOOii <= 0; - niOOil <= 0; - niOOiO <= 0; - niOOli <= 0; - niOOll <= 0; - niOOlO <= 0; - niOOOi <= 0; - niOOOl <= 0; - niOOOO <= 0; - nl010i <= 0; - nl010l <= 0; - nl010O <= 0; - nl011i <= 0; - nl011l <= 0; - nl011O <= 0; - nl01ii <= 0; - nl01il <= 0; - nl01iO <= 0; - nl01li <= 0; - nl01ll <= 0; - nl01lO <= 0; - nl01Oi <= 0; - nl01Ol <= 0; - nl0ll <= 0; - nl0lO <= 0; - nl0Oi <= 0; - nl0Ol <= 0; + n1O0i <= 0; + n1O0l <= 0; + n1O0O <= 0; + n1O1i <= 0; + n1O1l <= 0; + n1O1O <= 0; + n1Oii <= 0; + n1Oil <= 0; + n1OiO <= 0; + n1Oli <= 0; + n1Oll <= 0; + n1OlO <= 0; + n1OOi <= 0; + n1OOl <= 0; + n1OOO <= 0; + ni1i <= 0; + niiii <= 0; + niilO <= 0; nl0OO <= 0; - nl100i <= 0; - nl100l <= 0; - nl100O <= 0; - nl101i <= 0; - nl101l <= 0; - nl101O <= 0; - nl10ii <= 0; - nl10il <= 0; - nl10iO <= 0; - nl10li <= 0; - nl10ll <= 0; - nl10lO <= 0; - nl10Oi <= 0; - nl10Ol <= 0; - nl10OO <= 0; - nl110i <= 0; - nl110l <= 0; - nl110O <= 0; - nl111i <= 0; - nl111l <= 0; - nl111O <= 0; - nl11ii <= 0; - nl11il <= 0; - nl11iO <= 0; - nl11li <= 0; - nl11ll <= 0; - nl11lO <= 0; - nl11Oi <= 0; - nl11Ol <= 0; - nl11OO <= 0; - nl1i0i <= 0; - nl1i0l <= 0; - nl1i0O <= 0; - nl1i1i <= 0; - nl1i1l <= 0; - nl1i1O <= 0; - nl1iii <= 0; - nl1iil <= 0; - nl1iiO <= 0; - nl1ili <= 0; - nl1ill <= 0; - nl1ilO <= 0; - nl1iOi <= 0; - nl1iOl <= 0; - nl1iOO <= 0; - nl1l0i <= 0; - nl1l0l <= 0; - nl1l0O <= 0; - nl1l1i <= 0; - nl1l1l <= 0; - nl1l1O <= 0; - nl1lii <= 0; - nl1lil <= 0; - nl1liO <= 0; - nl1lli <= 0; - nl1lll <= 0; - nl1llO <= 0; - nl1lOi <= 0; - nl1lOl <= 0; - nl1lOO <= 0; - nl1O0i <= 0; - nl1O0l <= 0; - nl1O0O <= 0; - nl1O1i <= 0; - nl1O1l <= 0; - nl1O1O <= 0; - nl1Oii <= 0; - nl1Oil <= 0; - nl1OiO <= 0; - nl1Oli <= 0; - nl1Oll <= 0; - nl1OlO <= 0; - nl1OOi <= 0; - nl1OOl <= 0; - nl1OOO <= 0; + nli0i <= 0; nli0l <= 0; + nli0O <= 0; nli1i <= 0; nli1l <= 0; nli1O <= 0; - nll1li <= 0; - nll1ll <= 0; - nll1Ol <= 0; - nlliOi <= 0; - nlliOl <= 0; - nlliOO <= 0; - nlll0i <= 0; - nlll0l <= 0; - nlll0O <= 0; - nlll1i <= 0; - nlll1l <= 0; - nlll1O <= 0; - nlllii <= 0; - nlllil <= 0; - nllliO <= 0; - nlllli <= 0; - nlllll <= 0; - nllllO <= 0; - nlllOi <= 0; - nlllOl <= 0; - nlllOO <= 0; - nllO0i <= 0; - nllO0l <= 0; - nllO0O <= 0; - nllO1i <= 0; - nllO1l <= 0; - nllO1O <= 0; - nlOilO <= 0; - nlOiOi <= 0; - nlOiOl <= 0; - nlOiOO <= 0; - nlOl0i <= 0; - nlOl0l <= 0; - nlOl0O <= 0; - nlOl1i <= 0; - nlOl1l <= 0; - nlOl1O <= 0; - nlOlil <= 0; - nlOliO <= 0; - nlOlli <= 0; - nlOlll <= 0; - nlOllO <= 0; - nlOlOi <= 0; - nlOlOl <= 0; - nlOlOO <= 0; + nliii <= 0; + nliil <= 0; + nliiO <= 0; + nlili <= 0; + nlill <= 0; + nlilO <= 0; + nliOi <= 0; + nlOOOi <= 0; + nlOOOl <= 0; + nlOOOO <= 0; end - else + else if (wire_n0OO_ENA == 1'b1) begin - n000i <= wire_n0l1l_dataout; - n000l <= wire_n0l1O_dataout; - n000O <= wire_n0l0i_dataout; - n001i <= wire_n0iOl_dataout; - n001l <= wire_n0iOO_dataout; - n001O <= wire_n0l1i_dataout; - n00ii <= wire_n0l0l_dataout; - n00il <= wire_n0l0O_dataout; - n00iO <= wire_n0lii_dataout; - n00li <= wire_n0lil_dataout; - n00ll <= wire_n0liO_dataout; - n00lO <= wire_n0lli_dataout; - n00Oi <= wire_n0lll_dataout; - n00Ol <= wire_n0llO_dataout; - n00OO <= wire_n0lOi_dataout; - n010i <= ((~ n01ii) & n010O); - n01ii <= wire_n01iO_dataout; - n01il <= wire_n01Oi_dataout; - n01lO <= ((~ n01ii) & n010O); - n01Ol <= wire_n0ilO_dataout; - n01OO <= wire_n0iOi_dataout; - n0i0i <= wire_n0O1l_dataout; - n0i0l <= wire_n0O1O_dataout; - n0i0O <= wire_n0O0i_dataout; - n0i1i <= wire_n0lOl_dataout; - n0i1l <= wire_n0lOO_dataout; - n0i1O <= wire_n0O1i_dataout; - n0iii <= wire_n0O0l_dataout; - n0iil <= wire_n0O0O_dataout; - n0iiO <= wire_n0Oii_dataout; - n0ili <= wire_n0Oil_dataout; - n0ill <= wire_n0Oli_o[11]; - n0OiO <= wire_ni0il_dataout; - n0Oll <= wire_ni0iO_dataout; - n0OlO <= wire_ni0li_dataout; - n0OlOl <= b[0]; - n0OlOO <= b[1]; - n0OO0i <= b[5]; - n0OO0l <= b[6]; - n0OO0O <= b[7]; - n0OO1i <= b[2]; - n0OO1l <= b[3]; - n0OO1O <= b[4]; - n0OOi <= wire_ni0ll_dataout; - n0OOii <= b[8]; - n0OOil <= b[9]; - n0OOiO <= b[10]; - n0OOl <= wire_ni0lO_dataout; - n0OOli <= b[11]; - n0OOll <= b[12]; - n0OOlO <= b[13]; - n0OOO <= wire_ni0Oi_dataout; - n0OOOi <= b[14]; - n0OOOl <= b[15]; - n0OOOO <= b[16]; - n101i <= wire_n100l_dataout; - n101l <= wire_n100O_dataout; - n101O <= wire_n10li_dataout; - n10iO <= ((n101l & (~ n101i)) & (~ n11OO)); - n11lO <= n101i; - n11Ol <= ((n101l & (~ n101i)) & (~ n11OO)); - n11OO <= wire_n100i_dataout; - n1i0i <= wire_n1ill_dataout; - n1i0l <= wire_n1ilO_dataout; - n1i0O <= wire_n1iOi_dataout; - n1i1i <= wire_n1iil_dataout; - n1i1l <= wire_n1iiO_dataout; - n1i1O <= wire_n1ili_dataout; - n1iii <= wire_n1iOl_dataout; - n1iOO <= wire_n1O1i_dataout; - n1l0i <= wire_n1O0l_dataout; - n1l0l <= wire_n1O0O_dataout; - n1l0O <= wire_n1Oii_dataout; - n1l1i <= wire_n1O1l_dataout; - n1l1l <= wire_n1O1O_dataout; - n1l1O <= wire_n1O0i_dataout; - n1lii <= wire_n1Oil_dataout; - n1lil <= wire_n1OiO_dataout; - n1liO <= wire_n1Oli_dataout; - n1lli <= wire_n1Oll_dataout; - n1lll <= wire_n1OlO_dataout; - n1llO <= wire_n1OOi_dataout; - n1lOi <= wire_n1OOl_dataout; - n1lOl <= wire_n1OOO_dataout; - n1lOO <= n010O; - ni000i <= (n0Olll ^ wire_n10i_dataout); - ni000l <= (n0Olll ^ wire_n10l_dataout); - ni000O <= (n0Olll ^ wire_n10O_dataout); - ni001i <= (n0Olll ^ wire_n11i_dataout); - ni001l <= (n0Olll ^ wire_n11l_dataout); - ni001O <= (n0Olll ^ wire_n11O_dataout); - ni00i <= wire_nil1l_dataout; - ni00ii <= (n0Olll ^ wire_n1ii_dataout); - ni00il <= (n0Olll ^ wire_n1il_dataout); - ni00iO <= (n0Olll ^ wire_n1iO_dataout); - ni00l <= wire_nil1O_dataout; - ni00li <= (n0Olll ^ (~ ni1l0O)); - ni00ll <= n0Olll; - ni00lO <= wire_nliii_o[0]; - ni00O <= ni0lil; - ni00Oi <= wire_nliii_o[1]; - ni00Ol <= wire_nliii_o[2]; - ni00OO <= wire_nliii_o[3]; - ni010i <= (n0Olll ^ wire_nlO0i_dataout); - ni010l <= (n0Olll ^ wire_nlO0l_dataout); - ni010O <= (n0Olll ^ wire_nlO0O_dataout); - ni011i <= n0Olll; - ni011l <= (n0Olll ^ wire_nlO1l_dataout); - ni011O <= (n0Olll ^ wire_nlO1O_dataout); - ni01i <= wire_niiOl_dataout; - ni01ii <= (n0Olll ^ wire_nlOii_dataout); - ni01il <= (n0Olll ^ wire_nlOil_dataout); - ni01iO <= (n0Olll ^ wire_nlOiO_dataout); - ni01l <= wire_niiOO_dataout; - ni01li <= (n0Olll ^ wire_nlOli_dataout); - ni01ll <= (n0Olll ^ wire_nlOll_dataout); - ni01lO <= (n0Olll ^ wire_nlOlO_dataout); - ni01O <= wire_nil1i_dataout; - ni01Oi <= (n0Olll ^ wire_nlOOi_dataout); - ni01Ol <= (n0Olll ^ wire_nlOOl_dataout); - ni01OO <= (n0Olll ^ wire_nlOOO_dataout); - ni0i0i <= wire_nliii_o[7]; - ni0i0l <= wire_nliii_o[8]; - ni0i0O <= wire_nliii_o[9]; - ni0i1i <= wire_nliii_o[4]; - ni0i1l <= wire_nliii_o[5]; - ni0i1O <= wire_nliii_o[6]; - ni0ii <= wire_nli0O_o[1]; - ni0iii <= wire_nliii_o[10]; - ni0iil <= wire_nliii_o[11]; - ni0iiO <= wire_nliii_o[12]; - ni0ili <= wire_nliii_o[13]; - ni0ill <= wire_nliii_o[14]; - ni0ilO <= wire_nliii_o[15]; - ni0iOi <= wire_nliii_o[16]; - ni0iOl <= wire_nliii_o[17]; - ni0iOO <= wire_nliii_o[18]; - ni0l0i <= wire_nliii_o[22]; - ni0l0l <= wire_nliii_o[23]; - ni0l0O <= wire_nliii_o[24]; - ni0l1i <= wire_nliii_o[19]; - ni0l1l <= wire_nliii_o[20]; - ni0l1O <= wire_nliii_o[21]; - ni0lii <= wire_nliii_o[25]; - ni0lil <= wire_nliii_o[26]; - ni0liO <= ni0lil; - ni0lli <= ni0llO; - ni0lll <= ni0lOi; - ni0llO <= nl0Oi; - ni0lOi <= nl0Ol; - ni0lOl <= ni0O1i; - ni0lOO <= ni0O1l; - ni0O0i <= ni0ii; - ni0O0l <= ni0O0O; - ni0O0O <= (~ n0ill); - ni0O1i <= nl0ll; - ni0O1l <= nl0lO; - ni0O1O <= ni0O0i; - ni0Oil <= wire_ni0Oii_q_b[0]; - ni0OiO <= wire_ni0Oii_q_b[1]; - ni0Oli <= wire_ni0Oii_q_b[2]; - ni0Oll <= wire_ni0Oii_q_b[3]; - ni0OlO <= wire_ni0Oii_q_b[4]; - ni0OOi <= wire_ni0Oii_q_b[5]; - ni0OOl <= wire_ni0Oii_q_b[6]; - ni0OOO <= wire_ni0Oii_q_b[7]; - ni100i <= a[3]; - ni100l <= a[4]; - ni100O <= a[5]; - ni101i <= a[0]; - ni101l <= a[1]; - ni101O <= a[2]; - ni10i <= wire_nii1l_dataout; - ni10ii <= a[6]; - ni10il <= a[7]; - ni10iO <= a[8]; - ni10l <= wire_nii1O_dataout; - ni10li <= a[9]; - ni10ll <= a[10]; - ni10lO <= a[11]; - ni10O <= wire_nii0i_dataout; - ni10Oi <= a[12]; - ni10Ol <= a[13]; - ni10OO <= a[14]; - ni110i <= b[20]; - ni110l <= b[21]; - ni110O <= b[22]; - ni111i <= b[17]; - ni111l <= b[18]; - ni111O <= b[19]; - ni11i <= wire_ni0Ol_dataout; - ni11ii <= b[23]; - ni11il <= b[24]; - ni11iO <= b[25]; - ni11l <= wire_ni0OO_dataout; - ni11li <= b[26]; - ni11ll <= b[27]; - ni11lO <= b[28]; - ni11O <= wire_nii1i_dataout; - ni11Oi <= b[29]; - ni11Ol <= b[30]; - ni11OO <= b[31]; - ni1i0i <= a[18]; - ni1i0l <= a[19]; - ni1i0O <= a[20]; - ni1i1i <= a[15]; - ni1i1l <= a[16]; - ni1i1O <= a[17]; - ni1ii <= wire_nii0l_dataout; - ni1iii <= a[21]; - ni1iil <= a[22]; - ni1iiO <= a[23]; - ni1il <= wire_nii0O_dataout; - ni1ili <= a[24]; - ni1ill <= a[25]; - ni1ilO <= a[26]; - ni1iO <= wire_niiii_dataout; - ni1iOi <= a[27]; - ni1iOl <= a[28]; - ni1iOO <= a[29]; - ni1l0i <= wire_nilO_dataout; - ni1l0l <= n0Olll; - ni1l0O <= n0Ol0i; - ni1l1i <= a[30]; - ni1l1l <= a[31]; - ni1l1O <= wire_nl_dataout; - ni1li <= wire_niiil_dataout; - ni1lii <= wire_niOi_dataout; - ni1lil <= wire_niOl_dataout; - ni1liO <= wire_niOO_dataout; - ni1ll <= wire_niiiO_dataout; - ni1lli <= wire_nl1i_dataout; - ni1lll <= wire_nl1l_dataout; - ni1llO <= wire_nl1O_dataout; - ni1lO <= wire_niili_dataout; - ni1lOi <= wire_nl0i_dataout; - ni1lOl <= wire_nl0l_dataout; - ni1lOO <= wire_nl0O_dataout; - ni1O0i <= wire_nlli_dataout; - ni1O0l <= wire_nlll_dataout; - ni1O0O <= wire_nllO_dataout; - ni1O1i <= wire_nlii_dataout; - ni1O1l <= wire_nlil_dataout; - ni1O1O <= wire_nliO_dataout; - ni1Oi <= wire_niill_dataout; - ni1Oii <= wire_nlOi_dataout; - ni1Oil <= wire_nlOl_dataout; - ni1OiO <= wire_nlOO_dataout; - ni1Ol <= wire_niilO_dataout; - ni1Oli <= wire_n1i_dataout; - ni1Oll <= wire_n1l_dataout; - ni1OlO <= wire_n1O_dataout; - ni1OO <= wire_niiOi_dataout; - ni1OOi <= wire_n0i_dataout; - ni1OOl <= wire_n0l_dataout; - ni1OOO <= n0Olll; - nii00i <= wire_n011i_o[3]; - nii00l <= wire_n011i_o[4]; - nii00O <= wire_n011i_o[5]; - nii01i <= wire_n011i_o[0]; - nii01l <= wire_n011i_o[1]; - nii01O <= wire_n011i_o[2]; - nii0ii <= wire_n011i_o[6]; - nii0il <= wire_n011i_o[7]; - nii0iO <= wire_n011i_o[8]; - nii0li <= wire_n011i_o[9]; - nii0ll <= wire_n011i_o[10]; - nii0lO <= wire_n011i_o[11]; - nii0Oi <= wire_n011i_o[12]; - nii0Ol <= wire_n011i_o[13]; - nii0OO <= wire_n011i_o[14]; - nii10i <= wire_ni0Oii_q_b[11]; - nii10l <= wire_ni0Oii_q_b[12]; - nii10O <= wire_ni0Oii_q_b[13]; - nii11i <= wire_ni0Oii_q_b[8]; - nii11l <= wire_ni0Oii_q_b[9]; - nii11O <= wire_ni0Oii_q_b[10]; - nii1ii <= wire_ni0Oii_q_b[14]; - nii1il <= wire_ni0Oii_q_b[15]; - nii1iO <= wire_ni0Oii_q_b[16]; - nii1li <= wire_ni0Oii_q_b[17]; - nii1ll <= wire_ni0Oii_q_b[18]; - nii1lO <= wire_ni0Oii_q_b[19]; - nii1Oi <= wire_ni0Oii_q_b[20]; - nii1Ol <= wire_ni0Oii_q_b[21]; - nii1OO <= wire_ni0Oii_q_b[22]; - niii0i <= wire_n011i_o[18]; - niii0l <= wire_n011i_o[19]; - niii0O <= wire_n011i_o[20]; - niii1i <= wire_n011i_o[15]; - niii1l <= wire_n011i_o[16]; - niii1O <= wire_n011i_o[17]; - niiiii <= wire_n011i_o[21]; - niiiil <= wire_n011i_o[22]; - niiiiO <= wire_n011i_o[23]; - niiili <= wire_n011i_o[24]; - niiill <= wire_n011i_o[25]; - niiilO <= wire_n011i_o[26]; - niiiOi <= niiiOl; - niiiOl <= niiiOO; - niiiOO <= n0OliO; - niil0i <= ((~ wire_n10OO_dataout) & (~ wire_n10Ol_dataout)); - niil0l <= wire_n10Oi_dataout; - niil0O <= wire_n10OO_dataout; - niil1i <= niil1l; - niil1l <= n0Olil; - niil1O <= n0Olii; - niilii <= n0Ol1O; - niilil <= niiliO; - niiliO <= niilli; - niilli <= niilll; - niilll <= niillO; - niillO <= niilOi; - niilOi <= niilOl; - niilOl <= niilOO; - niilOO <= niiO1i; - niiO0i <= niiO0l; - niiO0l <= niiO0O; - niiO0O <= niiOii; - niiO1i <= ni1l0i; - niiO1l <= n0Ol1l; - niiO1O <= niiO0i; - niiOii <= niiOil; - niiOil <= niiOiO; - niiOiO <= niiOli; - niiOli <= niiO1l; - niiOll <= niiOlO; - niiOlO <= niiOOi; - niiOOi <= niiOOl; - niiOOl <= niiOOO; - niiOOO <= nil11i; - nil00i <= nil00l; - nil00l <= nil00O; - nil00O <= nil0ii; - nil01i <= ((~ nil1Ol) & (~ nil1OO)); - nil01l <= nil01O; - nil01O <= nil00i; - nil0ii <= nil0il; - nil0il <= nil0iO; - nil0iO <= nil0li; - nil0li <= ni1l1O; - nil0ll <= nil0lO; - nil0lO <= nil0Oi; - nil0Oi <= nil0Ol; - nil0Ol <= nil0OO; - nil0OO <= nili1i; - nil10i <= ((~ niiO1O) & niiOll); - nil10O <= wire_nil10l_q_b[0]; - nil11i <= nil11l; - nil11l <= nil11O; - nil11O <= (~ ni1l0O); - nil1ii <= wire_nil10l_q_b[1]; - nil1il <= wire_nil10l_q_b[2]; - nil1iO <= wire_nil10l_q_b[3]; - nil1li <= wire_nil10l_q_b[4]; - nil1ll <= wire_nil10l_q_b[5]; - nil1lO <= wire_nil10l_q_b[6]; - nil1Oi <= wire_nil10l_q_b[7]; - nil1Ol <= n0Ol1i; - nil1OO <= n0OiOO; - nili0i <= ni1l0O; - nili0l <= nil1OO; - nili0O <= n0OiOl; - nili1i <= nili1l; - nili1l <= nili1O; - nili1O <= nili0i; - niliii <= niliil; - niliil <= niliiO; - niliiO <= nilili; - nilili <= nilill; - nilill <= nililO; - nililO <= niliOi; - niliOi <= nili0O; - niliOl <= (niiO1O & niliii); - niliOO <= n0OiOi; - nill0i <= (nil1Ol & nill1i); - nill0l <= ((((nil10i & nil01i) & niilil) & (~ niilii)) | (((((nil0ll & nili0l) & niilil) & nil01l) | ((nil01i & nil0ll) & niilil)) | ((nil01l & niliOl) | (niilil & nill0i)))); - nill0O <= (niiO1O & (~ niliii)); - nill1i <= nill1l; - nill1l <= nill1O; - nill1O <= niliOO; - nillii <= nill0O; - nillil <= (nil1Ol & (~ nill1i)); - nilliO <= nillil; - nillli <= nillll; - nillll <= nilllO; - nilllO <= nillOi; - nillOi <= nillOl; - nillOl <= nillOO; - nillOO <= nilO1i; - nilO0i <= niliOl; - nilO0l <= nill0i; - nilO0O <= ((~ n0Ol0O) & nill0l); - nilO1i <= nilO1l; - nilO1l <= nilO1O; - nilO1O <= ni1l0l; - nilOii <= niO11l; - nilOil <= niO11O; - nilOiO <= niO10i; - nilOli <= niO10l; - nilOll <= niO10O; - nilOlO <= niO1ii; - nilOOi <= niO1il; - nilOOl <= niO1iO; - nilOOO <= niO1li; - niO00i <= nii0il; - niO00l <= nii0iO; - niO00O <= nii0li; - niO01i <= nii00l; - niO01l <= nii00O; - niO01O <= nii0ii; - niO0ii <= niOl1O; - niO0il <= niOl0i; - niO0iO <= niOl0l; - niO0li <= niOl0O; - niO0ll <= niOlii; - niO0lO <= niOlil; - niO0Oi <= niOliO; - niO0Ol <= niOlli; - niO0OO <= niOlll; - niO10i <= niO1Ol; - niO10l <= niO1OO; - niO10O <= niO01i; - niO11i <= niO1ll; - niO11l <= niO1lO; - niO11O <= niO1Oi; - niO1ii <= niO01l; - niO1il <= niO01O; - niO1iO <= niO00i; - niO1li <= niO00l; - niO1ll <= niO00O; - niO1lO <= nii01i; - niO1Oi <= nii01l; - niO1Ol <= nii01O; - niO1OO <= nii00i; - niOi0i <= niOlOO; - niOi0l <= niOO1i; - niOi0O <= niOO1l; - niOi1i <= niOllO; - niOi1l <= niOlOi; - niOi1O <= niOlOl; - niOiii <= niOO1O; - niOiil <= niOO0i; - niOiiO <= niOO0l; - niOili <= niOO0O; - niOill <= niOOii; - niOilO <= niOOil; - niOiOi <= niOOiO; - niOiOl <= niOOli; - niOiOO <= niOOll; - niOl0i <= niOOOO; - niOl0l <= nl111i; - niOl0O <= nl111l; - niOl1i <= niOOlO; - niOl1l <= niOOOi; - niOl1O <= niOOOl; - niOlii <= nl111O; - niOlil <= nl110i; - niOliO <= nl110l; - niOlli <= nl110O; - niOlll <= nl11ii; - niOllO <= nl11il; - niOlOi <= nl11iO; - niOlOl <= nl11li; - niOlOO <= nl11ll; - niOO0i <= nl11OO; - niOO0l <= nl101i; - niOO0O <= nl101l; - niOO1i <= nl11lO; - niOO1l <= nl11Oi; - niOO1O <= nl11Ol; - niOOii <= nl101O; - niOOil <= nl100i; - niOOiO <= nl100l; - niOOli <= nl100O; - niOOll <= nl10ii; - niOOlO <= nl10il; - niOOOi <= nl10iO; - niOOOl <= nii01i; - niOOOO <= nii01l; - nl010i <= wire_nlli1l_dataout; - nl010l <= wire_nlli1O_dataout; - nl010O <= wire_nlli0i_dataout; - nl011i <= wire_nll0Ol_dataout; - nl011l <= wire_nll0OO_dataout; - nl011O <= wire_nlli1i_dataout; - nl01ii <= wire_nlli0l_dataout; - nl01il <= wire_nlli0O_dataout; - nl01iO <= wire_nlliii_dataout; - nl01li <= wire_nlliil_dataout; - nl01ll <= wire_nlliiO_dataout; - nl01lO <= wire_nllili_dataout; - nl01Oi <= wire_nllill_dataout; - nl01Ol <= wire_nllilO_dataout; - nl0ll <= wire_nli0O_o[2]; - nl0lO <= wire_nli0O_o[3]; - nl0Oi <= wire_nli0O_o[4]; - nl0Ol <= wire_nli0O_o[5]; - nl0OO <= wire_nli0O_o[6]; - nl100i <= niii0O; - nl100l <= niiiii; - nl100O <= niiiil; - nl101i <= niii1O; - nl101l <= niii0i; - nl101O <= niii0l; - nl10ii <= niiiiO; - nl10il <= niiili; - nl10iO <= niiill; - nl10li <= (~ wire_n10lO_dataout); - nl10ll <= nl1i0i; - nl10lO <= nl1i0l; - nl10Oi <= nl1i0O; - nl10Ol <= nl1iii; - nl10OO <= nl1iil; - nl110i <= nii00O; - nl110l <= nii0ii; - nl110O <= nii0il; - nl111i <= nii01O; - nl111l <= nii00i; - nl111O <= nii00l; - nl11ii <= nii0iO; - nl11il <= nii0li; - nl11iO <= nii0ll; - nl11li <= nii0lO; - nl11ll <= nii0Oi; - nl11lO <= nii0Ol; - nl11Oi <= nii0OO; - nl11Ol <= niii1i; - nl11OO <= niii1l; - nl1i0i <= nllO0O; - nl1i0l <= nlOilO; - nl1i0O <= nlOiOi; - nl1i1i <= nl1iiO; - nl1i1l <= nl1ili; - nl1i1O <= nl1ill; - nl1iii <= nlOiOl; - nl1iil <= nlOiOO; - nl1iiO <= nlOl1i; - nl1ili <= nlOl1l; - nl1ill <= nlOl1O; - nl1ilO <= n0OilO; - nl1iOi <= n0Ol0l; - nl1iOl <= nl1Oii; - nl1iOO <= nl1Oil; - nl1l0i <= nl1OlO; - nl1l0l <= nl1OOi; - nl1l0O <= nl1OOl; - nl1l1i <= nl1OiO; - nl1l1l <= nl1Oli; - nl1l1O <= nl1Oll; - nl1lii <= nl1OOO; - nl1lil <= nl011i; - nl1liO <= nl011l; - nl1lli <= nl011O; - nl1lll <= nl010i; - nl1llO <= nl010l; - nl1lOi <= nl010O; - nl1lOl <= nl01ii; - nl1lOO <= nl01il; - nl1O0i <= nl01lO; - nl1O0l <= nl01Oi; - nl1O0O <= nl01Ol; - nl1O1i <= nl01iO; - nl1O1l <= nl01li; - nl1O1O <= nl01ll; - nl1Oii <= wire_nll00l_dataout; - nl1Oil <= wire_nll00O_dataout; - nl1OiO <= wire_nll0ii_dataout; - nl1Oli <= wire_nll0il_dataout; - nl1Oll <= wire_nll0iO_dataout; - nl1OlO <= wire_nll0li_dataout; - nl1OOi <= wire_nll0ll_dataout; - nl1OOl <= wire_nll0lO_dataout; - nl1OOO <= wire_nll0Oi_dataout; - nli0l <= wire_nO_o[33]; - nli1i <= wire_nli0O_o[7]; - nli1l <= wire_nli0O_o[8]; - nli1O <= wire_nli0O_o[9]; - nll1li <= wire_nll1Oi_o; - nll1ll <= wire_nll1OO_o; - nll1Ol <= wire_nllOii_o; - nlliOi <= wire_nllOil_o; - nlliOl <= wire_nllOiO_o; - nlliOO <= wire_nllOli_o; - nlll0i <= wire_nllOOl_o; - nlll0l <= wire_nllOOO_o; - nlll0O <= wire_nlO11i_o; - nlll1i <= wire_nllOll_o; - nlll1l <= wire_nllOlO_o; - nlll1O <= wire_nllOOi_o; - nlllii <= wire_nlO11l_o; - nlllil <= wire_nlO11O_o; - nllliO <= wire_nlO10i_o; - nlllli <= wire_nlO10l_o; - nlllll <= wire_nlO10O_o; - nllllO <= wire_nlO1ii_o; - nlllOi <= wire_nlO1il_o; - nlllOl <= wire_nlO1iO_o; - nlllOO <= wire_nlO1li_o; - nllO0i <= wire_nlO1Ol_o; - nllO0l <= wire_nlO1OO_o; - nllO0O <= wire_nlOlii_o[1]; - nllO1i <= wire_nlO1ll_o; - nllO1l <= wire_nlO1lO_o; - nllO1O <= wire_nlO1Oi_o; - nlOilO <= wire_nlOlii_o[2]; - nlOiOi <= wire_nlOlii_o[3]; - nlOiOl <= wire_nlOlii_o[4]; - nlOiOO <= wire_nlOlii_o[5]; - nlOl0i <= wire_nlOlii_o[9]; - nlOl0l <= wire_nlOlii_o[10]; - nlOl0O <= wire_nlOO1l_o[0]; - nlOl1i <= wire_nlOlii_o[6]; - nlOl1l <= wire_nlOlii_o[7]; - nlOl1O <= wire_nlOlii_o[8]; - nlOlil <= wire_nlOO1l_o[1]; - nlOliO <= wire_nlOO1l_o[2]; - nlOlli <= wire_nlOO1l_o[3]; - nlOlll <= wire_nlOO1l_o[4]; - nlOllO <= wire_nlOO1l_o[5]; - nlOlOi <= wire_nlOO1l_o[6]; - nlOlOl <= wire_nlOO1l_o[7]; - nlOlOO <= wire_nlOO1l_o[8]; + n000i <= wire_nil1l_o; + n000l <= wire_nil1O_o; + n000O <= wire_nil0i_o; + n001i <= wire_niiOl_o; + n001l <= wire_niiOO_o; + n001O <= wire_nil1i_o; + n00ii <= wire_nil0l_o; + n00il <= wire_nil0O_o; + n00iO <= wire_nilii_o; + n00li <= wire_niO0O_o[1]; + n00ll <= wire_niO0O_o[2]; + n00lO <= wire_niO0O_o[3]; + n00Oi <= wire_niO0O_o[4]; + n00Ol <= wire_niO0O_o[5]; + n00OO <= wire_niO0O_o[6]; + n010i <= wire_nl0Ol_o[2]; + n010l <= wire_nl0Ol_o[3]; + n010O <= wire_nl0Ol_o[4]; + n011i <= wire_nl0Ol_o[4]; + n011l <= wire_nl0Ol_o[0]; + n011O <= wire_nl0Ol_o[1]; + n01ii <= wire_nl0Ol_o[5]; + n01il <= wire_nl0Ol_o[6]; + n01iO <= wire_nl0Ol_o[7]; + n01li <= wire_nl0Ol_o[8]; + n01ll <= wire_nl0Ol_o[9]; + n01lO <= wire_nl0Ol_o[10]; + n01Oi <= wire_nl0Ol_o[11]; + n01Ol <= wire_nl0Ol_o[12]; + n01OO <= wire_niiOi_o; + n0i1i <= wire_niO0O_o[7]; + n0i1l <= nlOlOl; + n0ii <= wire_ni1O_dataout; + n0il <= wire_ni0i_dataout; + n0iO <= wire_ni0l_dataout; + n0li <= wire_ni0O_dataout; + n0ll <= wire_niii_dataout; + n0lO <= wire_niil_dataout; + n0Oi <= wire_niiO_dataout; + n0Ol <= wire_nili_dataout; + n100i <= n10Ol; + n100l <= wire_niOi_dataout; + n100O <= wire_niOl_dataout; + n101i <= n10ll; + n101l <= n10lO; + n101O <= n10Oi; + n10ii <= wire_niOO_dataout; + n10il <= wire_nl1i_dataout; + n10iO <= wire_nl1l_dataout; + n10li <= wire_nl1O_dataout; + n10ll <= wire_nl0i_dataout; + n10lO <= wire_nl0l_dataout; + n10Oi <= wire_nl0O_dataout; + n10Ol <= wire_nlii_dataout; + n10OO <= nlOOil; + n110i <= wire_ni_dataout; + n110l <= wire_nlil_dataout; + n110O <= wire_nliO_dataout; + n111i <= wire_nli_dataout; + n111l <= wire_nll_dataout; + n111O <= wire_nlO_dataout; + n11ii <= wire_nlli_dataout; + n11il <= wire_nlll_dataout; + n11iO <= wire_nllO_dataout; + n11li <= n100l; + n11ll <= n100O; + n11lO <= n10ii; + n11Oi <= n10il; + n11Ol <= n10iO; + n11OO <= n10li; + n1i0i <= wire_nl0iO_dataout; + n1i0l <= wire_nl0ll_dataout; + n1i0O <= wire_nl0lO_dataout; + n1i1i <= ((((~ wire_nl0Oi_dataout) & (~ wire_nl0lO_dataout)) & (~ wire_nl0ll_dataout)) & (~ wire_nl0li_dataout)); + n1i1l <= wire_nl0ii_dataout; + n1i1O <= wire_nl0il_dataout; + n1iii <= wire_nl0Oi_dataout; + n1iil <= n1iiO; + n1iiO <= n1ili; + n1ili <= wire_nlOi_dataout; + n1ill <= nlOlll; + n1ilO <= n1ill; + n1iOi <= n1iOl; + n1iOl <= (~ nlOOOl); + n1iOO <= n1l0l; + n1l0i <= n1liO; + n1l0l <= n110l; + n1l0O <= n110O; + n1l1i <= n1l0O; + n1l1l <= n1lii; + n1l1O <= n1lil; + n1lii <= n11ii; + n1lil <= n11il; + n1liO <= n11iO; + n1lli <= n1lll; + n1lll <= n1llO; + n1llO <= wire_nl_dataout; + n1lOi <= n1lOl; + n1lOl <= nlOOOl; + n1lOO <= nlOlli; + n1O0i <= ((((nlOO0O & nlOO1O) & n1iil) & (~ nlOllO)) | (((((nlOO0i & n1lOi) & n1iil) & n1lli) | ((nlOO1O & n1lOi) & n1iil)) | ((nlOO1l & n1lli) | (nlOO1i & n1iil)))); + n1O0l <= (n1ilO & (~ n1O1i)); + n1O0O <= (nlOO0l & (~ n1O1O)); + n1O1i <= n1O1l; + n1O1l <= n1lOO; + n1O1O <= nlOliO; + n1Oii <= n1Oil; + n1Oil <= n1OiO; + n1OiO <= nlOOOi; + n1Oli <= nlOO1l; + n1Oll <= nlOO1i; + n1OlO <= wire_nl0Ol_o[0]; + n1OOi <= wire_nl0Ol_o[1]; + n1OOl <= wire_nl0Ol_o[2]; + n1OOO <= wire_nl0Ol_o[3]; + ni1i <= wire_nill_dataout; + niiii <= wire_nliOl_dataout; + niilO <= wire_niiil_o; + nl0OO <= wire_nliOO_dataout; + nli0i <= wire_nll0i_dataout; + nli0l <= wire_nll0l_dataout; + nli0O <= wire_nll0O_dataout; + nli1i <= wire_nll1i_dataout; + nli1l <= wire_nll1l_dataout; + nli1O <= wire_nll1O_dataout; + nliii <= wire_nllii_dataout; + nliil <= wire_nllil_dataout; + nliiO <= wire_nlliO_dataout; + nlili <= wire_nllli_dataout; + nlill <= wire_nllll_dataout; + nlilO <= wire_n1li_o[13]; + nliOi <= wire_ni1l_dataout; + nlOOOi <= (wire_nl_dataout ^ wire_nlOi_dataout); + nlOOOl <= nlOOli; + nlOOOO <= wire_niO_dataout; end end - assign wire_n00i_dataout = (nli0l === 1'b1) ? n0OOii : ni10iO; - assign wire_n00l_dataout = (nli0l === 1'b1) ? n0OOil : ni10li; - assign wire_n00O_dataout = (nli0l === 1'b1) ? n0OOiO : ni10ll; - assign wire_n01i_dataout = (nli0l === 1'b1) ? n0OO0i : ni100O; - assign wire_n01iO_dataout = (n010i === 1'b1) ? wire_n01ll_o[0] : wire_n01li_o[1]; - assign wire_n01l_dataout = (nli0l === 1'b1) ? n0OO0l : ni10ii; - assign wire_n01O_dataout = (nli0l === 1'b1) ? n0OO0O : ni10il; - or(wire_n01Oi_dataout, n01lO, n01il); - assign wire_n0i_dataout = (nli0l === 1'b1) ? ni1iii : ni110l; - assign wire_n0ii_dataout = (nli0l === 1'b1) ? n0OOli : ni10lO; - assign wire_n0il_dataout = (nli0l === 1'b1) ? n0OOll : ni10Oi; - assign wire_n0ilO_dataout = ((~ ni0O0l) === 1'b1) ? n0OiO : ni0liO; - assign wire_n0iO_dataout = (nli0l === 1'b1) ? n0OOlO : ni10Ol; - assign wire_n0iOi_dataout = ((~ ni0O0l) === 1'b1) ? n0Oll : ni0liO; - assign wire_n0iOl_dataout = ((~ ni0O0l) === 1'b1) ? n0OlO : ni0liO; - assign wire_n0iOO_dataout = ((~ ni0O0l) === 1'b1) ? n0OOi : ni0liO; - assign wire_n0l_dataout = (nli0l === 1'b1) ? ni1iil : ni110O; - assign wire_n0l0i_dataout = ((~ ni0O0l) === 1'b1) ? ni11l : ni0liO; - assign wire_n0l0l_dataout = ((~ ni0O0l) === 1'b1) ? ni11O : ni0liO; - assign wire_n0l0O_dataout = ((~ ni0O0l) === 1'b1) ? ni10i : ni0liO; - assign wire_n0l1i_dataout = ((~ ni0O0l) === 1'b1) ? n0OOl : ni0liO; - assign wire_n0l1l_dataout = ((~ ni0O0l) === 1'b1) ? n0OOO : ni0liO; - assign wire_n0l1O_dataout = ((~ ni0O0l) === 1'b1) ? ni11i : ni0liO; - assign wire_n0li_dataout = (nli0l === 1'b1) ? n0OOOi : ni10OO; - assign wire_n0lii_dataout = ((~ ni0O0l) === 1'b1) ? ni10l : ni0liO; - assign wire_n0lil_dataout = ((~ ni0O0l) === 1'b1) ? ni10O : ni0liO; - assign wire_n0liO_dataout = ((~ ni0O0l) === 1'b1) ? ni1ii : ni0liO; - assign wire_n0ll_dataout = (nli0l === 1'b1) ? n0OOOl : ni1i1i; - assign wire_n0lli_dataout = ((~ ni0O0l) === 1'b1) ? ni1il : ni0liO; - assign wire_n0lll_dataout = ((~ ni0O0l) === 1'b1) ? ni1iO : ni0liO; - assign wire_n0llO_dataout = ((~ ni0O0l) === 1'b1) ? ni1li : ni0liO; - assign wire_n0lO_dataout = (nli0l === 1'b1) ? n0OOOO : ni1i1l; - assign wire_n0lOi_dataout = ((~ ni0O0l) === 1'b1) ? ni1ll : ni0liO; - assign wire_n0lOl_dataout = ((~ ni0O0l) === 1'b1) ? ni1lO : ni0liO; - assign wire_n0lOO_dataout = ((~ ni0O0l) === 1'b1) ? ni1Oi : ni0liO; - assign wire_n0O_dataout = (nli0l === 1'b1) ? ni1iiO : ni11ii; - assign wire_n0O0i_dataout = ((~ ni0O0l) === 1'b1) ? ni01l : ni0liO; - assign wire_n0O0l_dataout = ((~ ni0O0l) === 1'b1) ? ni01O : ni0liO; - assign wire_n0O0O_dataout = ((~ ni0O0l) === 1'b1) ? ni00i : ni0liO; - assign wire_n0O1i_dataout = ((~ ni0O0l) === 1'b1) ? ni1Ol : ni0liO; - assign wire_n0O1l_dataout = ((~ ni0O0l) === 1'b1) ? ni1OO : ni0liO; - assign wire_n0O1O_dataout = ((~ ni0O0l) === 1'b1) ? ni01i : ni0liO; - assign wire_n0Oi_dataout = (nli0l === 1'b1) ? ni111i : ni1i1O; - assign wire_n0Oii_dataout = ((~ ni0O0l) === 1'b1) ? ni00l : ni0liO; - assign wire_n0Oil_dataout = ((~ ni0O0l) === 1'b1) ? ni00O : ni0liO; - assign wire_n0Ol_dataout = (nli0l === 1'b1) ? ni111l : ni1i0i; - assign wire_n0OO_dataout = (nli0l === 1'b1) ? ni111O : ni1i0l; - assign wire_n100i_dataout = (n11Ol === 1'b1) ? wire_n10il_o[0] : wire_n10ii_o[0]; - assign wire_n100l_dataout = (n11Ol === 1'b1) ? wire_n10il_o[1] : wire_n10ii_o[1]; - assign wire_n100O_dataout = (n11Ol === 1'b1) ? wire_n10il_o[2] : wire_n10ii_o[2]; - and(wire_n10i_dataout, ni1OiO, (~ ni1l0O)); - and(wire_n10l_dataout, ni1Oli, (~ ni1l0O)); - or(wire_n10li_dataout, n10iO, n101O); - assign wire_n10lO_dataout = ((~ niil0i) === 1'b1) ? niil0O : niil0l; - and(wire_n10O_dataout, ni1Oll, (~ ni1l0O)); - assign wire_n10Oi_dataout = ((~ n0Olii) === 1'b1) ? n1i0l : n1i1i; - assign wire_n10Ol_dataout = ((~ n0Olii) === 1'b1) ? n1i0O : n1i1l; - assign wire_n10OO_dataout = ((~ n0Olii) === 1'b1) ? n1iii : n1i1O; - and(wire_n11i_dataout, ni1O0O, (~ ni1l0O)); - and(wire_n11l_dataout, ni1Oii, (~ ni1l0O)); - and(wire_n11O_dataout, ni1Oil, (~ ni1l0O)); - assign wire_n1i_dataout = (nli0l === 1'b1) ? ni1i0i : ni111l; - and(wire_n1ii_dataout, ni1OlO, (~ ni1l0O)); - assign wire_n1iil_dataout = ((~ n0Olil) === 1'b1) ? n1lil : n1iOO; - assign wire_n1iiO_dataout = ((~ n0Olil) === 1'b1) ? n1liO : n1l1i; - and(wire_n1il_dataout, ni1OOi, (~ ni1l0O)); - assign wire_n1ili_dataout = ((~ n0Olil) === 1'b1) ? n1lli : n1l1l; - assign wire_n1ill_dataout = ((~ n0Olil) === 1'b1) ? n1lll : n1l1O; - assign wire_n1ilO_dataout = ((~ n0Olil) === 1'b1) ? n1llO : n1l0i; - and(wire_n1iO_dataout, ni1OOl, (~ ni1l0O)); - assign wire_n1iOi_dataout = ((~ n0Olil) === 1'b1) ? n1lOi : n1l0l; - assign wire_n1iOl_dataout = ((~ n0Olil) === 1'b1) ? n1lOl : n1l0O; - assign wire_n1l_dataout = (nli0l === 1'b1) ? ni1i0l : ni111O; - assign wire_n1ll_dataout = (nli0l === 1'b1) ? n0OlOl : ni101i; - assign wire_n1lO_dataout = (nli0l === 1'b1) ? n0OlOO : ni101l; - assign wire_n1O_dataout = (nli0l === 1'b1) ? ni1i0O : ni110i; - or(wire_n1O0i_dataout, niii1i, ~((~ n0OliO))); - assign wire_n1O0l_dataout = ((~ n0OliO) === 1'b1) ? niii1l : nii01i; - assign wire_n1O0O_dataout = ((~ n0OliO) === 1'b1) ? niii1O : nii01l; - or(wire_n1O1i_dataout, nii0Oi, ~((~ n0OliO))); - or(wire_n1O1l_dataout, nii0Ol, ~((~ n0OliO))); - or(wire_n1O1O_dataout, nii0OO, ~((~ n0OliO))); - assign wire_n1Oi_dataout = (nli0l === 1'b1) ? n0OO1i : ni101O; - assign wire_n1Oii_dataout = ((~ n0OliO) === 1'b1) ? niii0i : nii01O; - assign wire_n1Oil_dataout = ((~ n0OliO) === 1'b1) ? niii0l : nii00i; - assign wire_n1OiO_dataout = ((~ n0OliO) === 1'b1) ? niii0O : nii00l; - assign wire_n1Ol_dataout = (nli0l === 1'b1) ? n0OO1l : ni100i; - assign wire_n1Oli_dataout = ((~ n0OliO) === 1'b1) ? niiiii : nii00O; - assign wire_n1Oll_dataout = ((~ n0OliO) === 1'b1) ? niiiil : nii0ii; - assign wire_n1OlO_dataout = ((~ n0OliO) === 1'b1) ? niiiiO : nii0il; - assign wire_n1OO_dataout = (nli0l === 1'b1) ? n0OO1O : ni100l; - assign wire_n1OOi_dataout = ((~ n0OliO) === 1'b1) ? niiili : nii0iO; - assign wire_n1OOl_dataout = ((~ n0OliO) === 1'b1) ? niiill : nii0li; - assign wire_n1OOO_dataout = ((~ n0OliO) === 1'b1) ? niiilO : nii0ll; - assign wire_ni_dataout = (nli0l === 1'b1) ? ni1l1i : ni11Ol; - assign wire_ni0i_dataout = (nli0l === 1'b1) ? ni11ii : ni1iiO; - assign wire_ni0il_dataout = ((~ ni0O1O) === 1'b1) ? wire_nil0i_o : wire_nil0l_o; - assign wire_ni0iO_dataout = ((~ ni0O1O) === 1'b1) ? wire_nil0l_o : wire_nil0O_o; - assign wire_ni0l_dataout = (nli0l === 1'b1) ? ni11il : ni1ili; - assign wire_ni0li_dataout = ((~ ni0O1O) === 1'b1) ? wire_nil0O_o : wire_nilii_o; - assign wire_ni0ll_dataout = ((~ ni0O1O) === 1'b1) ? wire_nilii_o : wire_nilil_o; - assign wire_ni0lO_dataout = ((~ ni0O1O) === 1'b1) ? wire_nilil_o : wire_niliO_o; - assign wire_ni0O_dataout = (nli0l === 1'b1) ? ni11iO : ni1ill; - assign wire_ni0Oi_dataout = ((~ ni0O1O) === 1'b1) ? wire_niliO_o : wire_nilli_o; - assign wire_ni0Ol_dataout = ((~ ni0O1O) === 1'b1) ? wire_nilli_o : wire_nilll_o; - assign wire_ni0OO_dataout = ((~ ni0O1O) === 1'b1) ? wire_nilll_o : wire_nillO_o; - assign wire_ni1i_dataout = (nli0l === 1'b1) ? ni110i : ni1i0O; - assign wire_ni1l_dataout = (nli0l === 1'b1) ? ni110l : ni1iii; - assign wire_ni1O_dataout = (nli0l === 1'b1) ? ni110O : ni1iil; - assign wire_nii_dataout = (nli0l === 1'b1) ? ni1ili : ni11il; - assign wire_nii0i_dataout = ((~ ni0O1O) === 1'b1) ? wire_nilOO_o : wire_niO1i_o; - assign wire_nii0l_dataout = ((~ ni0O1O) === 1'b1) ? wire_niO1i_o : wire_niO1l_o; - assign wire_nii0O_dataout = ((~ ni0O1O) === 1'b1) ? wire_niO1l_o : wire_niO1O_o; - assign wire_nii1i_dataout = ((~ ni0O1O) === 1'b1) ? wire_nillO_o : wire_nilOi_o; - assign wire_nii1l_dataout = ((~ ni0O1O) === 1'b1) ? wire_nilOi_o : wire_nilOl_o; - assign wire_nii1O_dataout = ((~ ni0O1O) === 1'b1) ? wire_nilOl_o : wire_nilOO_o; - assign wire_niii_dataout = (nli0l === 1'b1) ? ni11li : ni1ilO; - assign wire_niiii_dataout = ((~ ni0O1O) === 1'b1) ? wire_niO1O_o : wire_niO0i_o; - assign wire_niiil_dataout = ((~ ni0O1O) === 1'b1) ? wire_niO0i_o : wire_niO0l_o; - assign wire_niiiO_dataout = ((~ ni0O1O) === 1'b1) ? wire_niO0l_o : wire_niO0O_o; - assign wire_niil_dataout = (nli0l === 1'b1) ? ni11ll : ni1iOi; - assign wire_niili_dataout = ((~ ni0O1O) === 1'b1) ? wire_niO0O_o : wire_niOii_o; - assign wire_niill_dataout = ((~ ni0O1O) === 1'b1) ? wire_niOii_o : wire_niOil_o; - assign wire_niilO_dataout = ((~ ni0O1O) === 1'b1) ? wire_niOil_o : wire_niOiO_o; - assign wire_niiO_dataout = (nli0l === 1'b1) ? ni11lO : ni1iOl; - assign wire_niiOi_dataout = ((~ ni0O1O) === 1'b1) ? wire_niOiO_o : wire_niOli_o; - assign wire_niiOl_dataout = ((~ ni0O1O) === 1'b1) ? wire_niOli_o : wire_niOll_o; - assign wire_niiOO_dataout = ((~ ni0O1O) === 1'b1) ? wire_niOll_o : wire_niOlO_o; - assign wire_nil_dataout = (nli0l === 1'b1) ? ni1ill : ni11iO; - assign wire_nil1i_dataout = ((~ ni0O1O) === 1'b1) ? wire_niOlO_o : wire_niOOi_o; - assign wire_nil1l_dataout = ((~ ni0O1O) === 1'b1) ? wire_niOOi_o : wire_niOOl_o; - assign wire_nil1O_dataout = ((~ ni0O1O) === 1'b1) ? wire_niOOl_o : ni0lil; - assign wire_nili_dataout = (nli0l === 1'b1) ? ni11Oi : ni1iOO; - assign wire_nill_dataout = (nli0l === 1'b1) ? ni11Ol : ni1l1i; - assign wire_nilO_dataout = (nli0l === 1'b1) ? ni11OO : ni1l1l; - assign wire_niO_dataout = (nli0l === 1'b1) ? ni1ilO : ni11li; - assign wire_niOi_dataout = (nli0l === 1'b1) ? ni101i : n0OlOl; - assign wire_niOl_dataout = (nli0l === 1'b1) ? ni101l : n0OlOO; - assign wire_niOO_dataout = (nli0l === 1'b1) ? ni101O : n0OO1i; - assign wire_nl_dataout = (nli0l === 1'b1) ? ni1l1l : ni11OO; - assign wire_nl0i_dataout = (nli0l === 1'b1) ? ni10ii : n0OO0l; - assign wire_nl0l_dataout = (nli0l === 1'b1) ? ni10il : n0OO0O; - assign wire_nl0O_dataout = (nli0l === 1'b1) ? ni10iO : n0OOii; - assign wire_nl1i_dataout = (nli0l === 1'b1) ? ni100i : n0OO1l; - assign wire_nl1l_dataout = (nli0l === 1'b1) ? ni100l : n0OO1O; - assign wire_nl1O_dataout = (nli0l === 1'b1) ? ni100O : n0OO0i; - assign wire_nli_dataout = (nli0l === 1'b1) ? ni1iOi : ni11ll; - assign wire_nlii_dataout = (nli0l === 1'b1) ? ni10li : n0OOil; - assign wire_nlil_dataout = (nli0l === 1'b1) ? ni10ll : n0OOiO; - assign wire_nliO_dataout = (nli0l === 1'b1) ? ni10lO : n0OOli; - assign wire_nll_dataout = (nli0l === 1'b1) ? ni1iOl : ni11lO; - assign wire_nll00l_dataout = ((~ nl10li) === 1'b1) ? nlliOi : nll1Ol; - assign wire_nll00O_dataout = ((~ nl10li) === 1'b1) ? nlliOl : nlliOi; - assign wire_nll0ii_dataout = ((~ nl10li) === 1'b1) ? nlliOO : nlliOl; - assign wire_nll0il_dataout = ((~ nl10li) === 1'b1) ? nlll1i : nlliOO; - assign wire_nll0iO_dataout = ((~ nl10li) === 1'b1) ? nlll1l : nlll1i; - assign wire_nll0li_dataout = ((~ nl10li) === 1'b1) ? nlll1O : nlll1l; - assign wire_nll0ll_dataout = ((~ nl10li) === 1'b1) ? nlll0i : nlll1O; - assign wire_nll0lO_dataout = ((~ nl10li) === 1'b1) ? nlll0l : nlll0i; - assign wire_nll0Oi_dataout = ((~ nl10li) === 1'b1) ? nlll0O : nlll0l; - assign wire_nll0Ol_dataout = ((~ nl10li) === 1'b1) ? nlllii : nlll0O; - assign wire_nll0OO_dataout = ((~ nl10li) === 1'b1) ? nlllil : nlllii; - assign wire_nlli_dataout = (nli0l === 1'b1) ? ni10Oi : n0OOll; - assign wire_nlli0i_dataout = ((~ nl10li) === 1'b1) ? nllllO : nlllll; - assign wire_nlli0l_dataout = ((~ nl10li) === 1'b1) ? nlllOi : nllllO; - assign wire_nlli0O_dataout = ((~ nl10li) === 1'b1) ? nlllOl : nlllOi; - assign wire_nlli1i_dataout = ((~ nl10li) === 1'b1) ? nllliO : nlllil; - assign wire_nlli1l_dataout = ((~ nl10li) === 1'b1) ? nlllli : nllliO; - assign wire_nlli1O_dataout = ((~ nl10li) === 1'b1) ? nlllll : nlllli; - assign wire_nlliii_dataout = ((~ nl10li) === 1'b1) ? nlllOO : nlllOl; - assign wire_nlliil_dataout = ((~ nl10li) === 1'b1) ? nllO1i : nlllOO; - assign wire_nlliiO_dataout = ((~ nl10li) === 1'b1) ? nllO1l : nllO1i; - assign wire_nllili_dataout = ((~ nl10li) === 1'b1) ? nllO1O : nllO1l; - assign wire_nllill_dataout = ((~ nl10li) === 1'b1) ? nllO0i : nllO1O; - assign wire_nllilO_dataout = ((~ nl10li) === 1'b1) ? nllO0l : nllO0i; - assign wire_nlll_dataout = (nli0l === 1'b1) ? ni10Ol : n0OOlO; - assign wire_nllO_dataout = (nli0l === 1'b1) ? ni10OO : n0OOOi; - assign wire_nlO_dataout = (nli0l === 1'b1) ? ni1iOO : ni11Oi; - and(wire_nlO0i_dataout, ni1liO, (~ ni1l0O)); - and(wire_nlO0l_dataout, ni1lli, (~ ni1l0O)); - and(wire_nlO0O_dataout, ni1lll, (~ ni1l0O)); - and(wire_nlO1l_dataout, ni1lii, (~ ni1l0O)); - and(wire_nlO1O_dataout, ni1lil, (~ ni1l0O)); - assign wire_nlOi_dataout = (nli0l === 1'b1) ? ni1i1i : n0OOOl; - and(wire_nlOii_dataout, ni1llO, (~ ni1l0O)); - and(wire_nlOil_dataout, ni1lOi, (~ ni1l0O)); - and(wire_nlOiO_dataout, ni1lOl, (~ ni1l0O)); - assign wire_nlOl_dataout = (nli0l === 1'b1) ? ni1i1l : n0OOOO; - and(wire_nlOli_dataout, ni1lOO, (~ ni1l0O)); - and(wire_nlOll_dataout, ni1O1i, (~ ni1l0O)); - and(wire_nlOlO_dataout, ni1O1l, (~ ni1l0O)); - assign wire_nlOO_dataout = (nli0l === 1'b1) ? ni1i1O : ni111i; - and(wire_nlOOi_dataout, ni1O1O, (~ ni1l0O)); - and(wire_nlOOl_dataout, ni1O0i, (~ ni1l0O)); - and(wire_nlOOO_dataout, ni1O0l, (~ ni1l0O)); - oper_add n011i - ( - .a({{2{1'b0}}, 1'b1, nii1OO, nii1Ol, nii1Oi, nii1lO, nii1ll, nii1li, nii1iO, nii1il, nii1ii, nii10O, nii10l, nii10i, nii11O, nii11l, nii11i, ni0OOO, ni0OOl, ni0OOi, ni0OlO, ni0Oll, ni0Oli, ni0OiO, ni0Oil, {2{1'b0}}}), - .b({{2{n0ili}}, n0iiO, n0iil, n0iii, n0i0O, n0i0l, n0i0i, n0i1O, n0i1l, n0i1i, n00OO, n00Ol, n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n000O, n000l, n000i, n001O, n001l, n001i, n01OO, n01Ol}), + assign + wire_n0OO_ENA = en[0]; + assign wire_n0i_dataout = (wire_nO_o[17] === 1'b1) ? a[5] : b[5]; + assign wire_n0l_dataout = (wire_nO_o[17] === 1'b1) ? a[6] : b[6]; + assign wire_n0O_dataout = (wire_nO_o[17] === 1'b1) ? a[7] : b[7]; + assign wire_n1i_dataout = (wire_nO_o[17] === 1'b1) ? a[2] : b[2]; + assign wire_n1l_dataout = (wire_nO_o[17] === 1'b1) ? a[3] : b[3]; + assign wire_n1O_dataout = (wire_nO_o[17] === 1'b1) ? a[4] : b[4]; + assign wire_ni_dataout = (wire_nO_o[17] === 1'b1) ? a[14] : b[14]; + and(wire_ni0i_dataout, wire_n1i_dataout, (~ nlOOli)); + and(wire_ni0l_dataout, wire_n1l_dataout, (~ nlOOli)); + and(wire_ni0O_dataout, wire_n1O_dataout, (~ nlOOli)); + and(wire_ni1l_dataout, wire_nlOl_dataout, (~ nlOOli)); + and(wire_ni1O_dataout, wire_nlOO_dataout, (~ nlOOli)); + assign wire_nii_dataout = (wire_nO_o[17] === 1'b1) ? a[8] : b[8]; + and(wire_niii_dataout, wire_n0i_dataout, (~ nlOOli)); + and(wire_niil_dataout, wire_n0l_dataout, (~ nlOOli)); + and(wire_niiO_dataout, wire_n0O_dataout, (~ nlOOli)); + assign wire_nil_dataout = (wire_nO_o[17] === 1'b1) ? a[9] : b[9]; + and(wire_nili_dataout, wire_nii_dataout, (~ nlOOli)); + and(wire_nill_dataout, wire_nil_dataout, (~ nlOOli)); + assign wire_niO_dataout = (wire_nO_o[17] === 1'b1) ? a[10] : b[10]; + assign wire_niOi_dataout = (wire_nO_o[17] === 1'b1) ? b[0] : a[0]; + assign wire_niOl_dataout = (wire_nO_o[17] === 1'b1) ? b[1] : a[1]; + assign wire_niOO_dataout = (wire_nO_o[17] === 1'b1) ? b[2] : a[2]; + assign wire_nl_dataout = (wire_nO_o[17] === 1'b1) ? a[15] : b[15]; + assign wire_nl00i_dataout = ((~ n1i1i) === 1'b1) ? n1i0l : n1i1l; + assign wire_nl00l_dataout = ((~ n1i1i) === 1'b1) ? n1i0O : n1i1O; + assign wire_nl00O_dataout = ((~ n1i1i) === 1'b1) ? n1iii : n1i0i; + assign wire_nl01O_dataout = ((~ nlOOii) === 1'b1) ? wire_nl00O_dataout : wire_nl00i_dataout; + assign wire_nl0i_dataout = (wire_nO_o[17] === 1'b1) ? b[6] : a[6]; + or(wire_nl0ii_dataout, wire_nl0Ol_o[7], ~((~ nlOOil))); + assign wire_nl0il_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[8] : wire_nl0Ol_o[0]; + assign wire_nl0iO_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[9] : wire_nl0Ol_o[1]; + assign wire_nl0l_dataout = (wire_nO_o[17] === 1'b1) ? b[7] : a[7]; + assign wire_nl0li_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[10] : wire_nl0Ol_o[2]; + assign wire_nl0ll_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[11] : wire_nl0Ol_o[3]; + assign wire_nl0lO_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[12] : wire_nl0Ol_o[4]; + assign wire_nl0O_dataout = (wire_nO_o[17] === 1'b1) ? b[8] : a[8]; + assign wire_nl0Oi_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[13] : wire_nl0Ol_o[5]; + assign wire_nl1i_dataout = (wire_nO_o[17] === 1'b1) ? b[3] : a[3]; + assign wire_nl1l_dataout = (wire_nO_o[17] === 1'b1) ? b[4] : a[4]; + assign wire_nl1O_dataout = (wire_nO_o[17] === 1'b1) ? b[5] : a[5]; + assign wire_nli_dataout = (wire_nO_o[17] === 1'b1) ? a[11] : b[11]; + assign wire_nlii_dataout = (wire_nO_o[17] === 1'b1) ? b[9] : a[9]; + assign wire_nlil_dataout = (wire_nO_o[17] === 1'b1) ? b[10] : a[10]; + assign wire_nliO_dataout = (wire_nO_o[17] === 1'b1) ? b[11] : a[11]; + assign wire_nliOl_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nllOi_o : wire_n1li_o[13]; + assign wire_nliOO_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nllOl_o : wire_n1li_o[13]; + assign wire_nll_dataout = (wire_nO_o[17] === 1'b1) ? a[12] : b[12]; + assign wire_nll0i_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO1O_o : wire_n1li_o[13]; + assign wire_nll0l_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO0i_o : wire_n1li_o[13]; + assign wire_nll0O_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO0l_o : wire_n1li_o[13]; + assign wire_nll1i_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nllOO_o : wire_n1li_o[13]; + assign wire_nll1l_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO1i_o : wire_n1li_o[13]; + assign wire_nll1O_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO1l_o : wire_n1li_o[13]; + assign wire_nlli_dataout = (wire_nO_o[17] === 1'b1) ? b[12] : a[12]; + assign wire_nllii_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO0O_o : wire_n1li_o[13]; + assign wire_nllil_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlOii_o : wire_n1li_o[13]; + assign wire_nlliO_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlOil_o : wire_n1li_o[13]; + assign wire_nlll_dataout = (wire_nO_o[17] === 1'b1) ? b[13] : a[13]; + assign wire_nllli_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlOiO_o : wire_n1li_o[13]; + assign wire_nllll_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlOli_o : wire_n1li_o[13]; + assign wire_nllO_dataout = (wire_nO_o[17] === 1'b1) ? b[14] : a[14]; + assign wire_nlO_dataout = (wire_nO_o[17] === 1'b1) ? a[13] : b[13]; + assign wire_nlOi_dataout = (wire_nO_o[17] === 1'b1) ? b[15] : a[15]; + assign wire_nlOl_dataout = (wire_nO_o[17] === 1'b1) ? a[0] : b[0]; + assign wire_nlOO_dataout = (wire_nO_o[17] === 1'b1) ? a[1] : b[1]; + oper_add n1li + ( + .a({1'b0, nlOOOi, (nlOOOi ^ (~ nlOOOl)), (ni1i ^ nlOOOi), (n0Ol ^ nlOOOi), (n0Oi ^ nlOOOi), (n0lO ^ nlOOOi), (n0ll ^ nlOOOi), (n0li ^ nlOOOi), (n0iO ^ nlOOOi), (n0il ^ nlOOOi), (n0ii ^ nlOOOi), (nliOi ^ nlOOOi), {2{nlOOOi}}}), + .b({{14{1'b0}}, nlOOOi}), .cin(1'b0), .cout(), - .o(wire_n011i_o)); + .o(wire_n1li_o)); defparam - n011i.sgate_representation = 0, - n011i.width_a = 28, - n011i.width_b = 28, - n011i.width_o = 28; - oper_add n01li + n1li.sgate_representation = 0, + n1li.width_a = 15, + n1li.width_b = 15, + n1li.width_o = 15; + oper_add niO0O ( - .a({n01ii, n010O}), - .b({1'b0, 1'b1}), + .a({1'b0, wire_niOii_o[5:0], 1'b1}), + .b({{3{1'b1}}, (~ n10OO), (~ n1i1i), (~ nlOOii), wire_nl01O_dataout, 1'b1}), .cin(1'b0), .cout(), - .o(wire_n01li_o)); + .o(wire_niO0O_o)); defparam - n01li.sgate_representation = 0, - n01li.width_a = 2, - n01li.width_b = 2, - n01li.width_o = 2; - oper_add n01ll + niO0O.sgate_representation = 0, + niO0O.width_a = 8, + niO0O.width_b = 8, + niO0O.width_o = 8; + oper_add niOii ( - .a({n01ii}), - .b({1'b1}), + .a({1'b0, n1l0i, n1l1O, n1l1l, n1l1i, n1iOO}), + .b({{5{1'b0}}, 1'b1}), .cin(1'b0), .cout(), - .o(wire_n01ll_o)); + .o(wire_niOii_o)); defparam - n01ll.sgate_representation = 0, - n01ll.width_a = 1, - n01ll.width_b = 1, - n01ll.width_o = 1; - oper_add n0Oli + niOii.sgate_representation = 0, + niOii.width_a = 6, + niOii.width_b = 6, + niOii.width_o = 6; + oper_add nl0Ol ( - .a({{2{1'b0}}, nli1O, nli1l, nli1i, nl0OO, nl0Ol, nl0Oi, nl0lO, nl0ll, ni0ii, 1'b1}), - .b({{6{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1}), + .a({{2{1'b0}}, 1'b1, n100i, n101O, n101l, n101i, n11OO, n11Ol, n11Oi, n11lO, n11ll, n11li, {2{1'b0}}}), + .b({{2{nlilO}}, nlill, nlili, nliiO, nliil, nliii, nli0O, nli0l, nli0i, nli1O, nli1l, nli1i, nl0OO, niiii}), .cin(1'b0), .cout(), - .o(wire_n0Oli_o)); + .o(wire_nl0Ol_o)); defparam - n0Oli.sgate_representation = 0, - n0Oli.width_a = 12, - n0Oli.width_b = 12, - n0Oli.width_o = 12; - oper_add n10ii + nl0Ol.sgate_representation = 0, + nl0Ol.width_a = 15, + nl0Ol.width_b = 15, + nl0Ol.width_o = 15; + oper_add nlllO ( - .a({n101l, n101i, n11OO}), - .b({{2{1'b0}}, 1'b1}), + .a({{2{1'b0}}, wire_nlOll_o[6:1], 1'b1}), + .b({{4{1'b1}}, {3{1'b0}}, {2{1'b1}}}), .cin(1'b0), .cout(), - .o(wire_n10ii_o)); + .o(wire_nlllO_o)); defparam - n10ii.sgate_representation = 0, - n10ii.width_a = 3, - n10ii.width_b = 3, - n10ii.width_o = 3; - oper_add n10il + nlllO.sgate_representation = 0, + nlllO.width_a = 9, + nlllO.width_b = 9, + nlllO.width_o = 9; + oper_add nlOll ( - .a({n101l, n101i, n11OO}), - .b({1'b0, {2{1'b1}}}), + .a({1'b0, n11iO, n11il, n11ii, n110O, n110l, 1'b1}), + .b({1'b1, (~ n110i), (~ n111O), (~ n111l), (~ n111i), (~ nlOOOO), 1'b1}), .cin(1'b0), .cout(), - .o(wire_n10il_o)); + .o(wire_nlOll_o)); defparam - n10il.sgate_representation = 0, - n10il.width_a = 3, - n10il.width_b = 3, - n10il.width_o = 3; - oper_add nli0O + nlOll.sgate_representation = 0, + nlOll.width_a = 7, + nlOll.width_b = 7, + nlOll.width_o = 7; + oper_add nO ( - .a({1'b0, wire_nill_dataout, wire_nili_dataout, wire_niiO_dataout, wire_niil_dataout, wire_niii_dataout, wire_ni0O_dataout, wire_ni0l_dataout, wire_ni0i_dataout, 1'b1}), - .b({1'b1, (~ wire_ni_dataout), (~ wire_nlO_dataout), (~ wire_nll_dataout), (~ wire_nli_dataout), (~ wire_niO_dataout), (~ wire_nil_dataout), (~ wire_nii_dataout), (~ wire_n0O_dataout), 1'b1}), + .a({{2{1'b0}}, a[14:0], 1'b1}), + .b({{2{1'b1}}, (~ b[14]), (~ b[13]), (~ b[12]), (~ b[11]), (~ b[10]), (~ b[9]), (~ b[8]), (~ b[7]), (~ b[6]), (~ b[5]), (~ b[4]), (~ b[3]), (~ b[2]), (~ b[1]), (~ b[0]), 1'b1}), .cin(1'b0), .cout(), - .o(wire_nli0O_o)); + .o(wire_nO_o)); defparam - nli0O.sgate_representation = 0, - nli0O.width_a = 10, - nli0O.width_b = 10, - nli0O.width_o = 10; - oper_add nliii + nO.sgate_representation = 0, + nO.width_a = 18, + nO.width_b = 18, + nO.width_o = 18; + oper_mux n10i ( - .a({1'b0, ni00ll, ni00li, ni00iO, ni00il, ni00ii, ni000O, ni000l, ni000i, ni001O, ni001l, ni001i, ni01OO, ni01Ol, ni01Oi, ni01lO, ni01ll, ni01li, ni01iO, ni01il, ni01ii, ni010O, ni010l, ni010i, ni011O, ni011l, ni011i, ni1OOO}), - .b({{27{1'b0}}, ni1l0l}), - .cin(1'b0), - .cout(), - .o(wire_nliii_o)); + .data({{2{wire_n1li_o[13]}}, wire_n1li_o[11], wire_n1li_o[7]}), + .o(wire_n10i_o), + .sel({wire_nlOll_o[4:3]})); defparam - nliii.sgate_representation = 0, - nliii.width_a = 28, - nliii.width_b = 28, - nliii.width_o = 28; - oper_add nlOlii + n10i.width_data = 4, + n10i.width_sel = 2; + oper_mux n10l ( - .a({1'b0, nlOlOO, nlOlOl, nlOlOi, nlOllO, nlOlll, nlOlli, nlOliO, nlOlil, nlOl0O, 1'b1}), - .b({{5{1'b1}}, (~ niiiOi), (~ niil1i), (~ niil1O), (~ niil0i), wire_n10lO_dataout, 1'b1}), - .cin(1'b0), - .cout(), - .o(wire_nlOlii_o)); + .data({wire_n1li_o[13], wire_n1li_o[13:12], wire_n1li_o[8]}), + .o(wire_n10l_o), + .sel({wire_nlOll_o[4:3]})); defparam - nlOlii.sgate_representation = 0, - nlOlii.width_a = 11, - nlOlii.width_b = 11, - nlOlii.width_o = 11; - oper_add nlOO1l + n10l.width_data = 4, + n10l.width_sel = 2; + oper_mux n10O ( - .a({1'b0, nil1Oi, nil1lO, nil1ll, nil1li, nil1iO, nil1il, nil1ii, nil10O}), - .b({{8{1'b0}}, 1'b1}), - .cin(1'b0), - .cout(), - .o(wire_nlOO1l_o)); + .data({{3{wire_n1li_o[13]}}, wire_n1li_o[9]}), + .o(wire_n10O_o), + .sel({wire_nlOll_o[4:3]})); defparam - nlOO1l.sgate_representation = 0, - nlOO1l.width_a = 9, - nlOO1l.width_b = 9, - nlOO1l.width_o = 9; - oper_add nO + n10O.width_data = 4, + n10O.width_sel = 2; + oper_mux n11i ( - .a({{2{1'b0}}, a[30:0], 1'b1}), - .b({{2{1'b1}}, (~ b[30]), (~ b[29]), (~ b[28]), (~ b[27]), (~ b[26]), (~ b[25]), (~ b[24]), (~ b[23]), (~ b[22]), (~ b[21]), (~ b[20]), (~ b[19]), (~ b[18]), (~ b[17]), (~ b[16]), (~ b[15]), (~ b[14]), (~ b[13]), (~ b[12]), (~ b[11]), (~ b[10]), (~ b[9]), (~ b[8]), (~ b[7]), (~ b[6]), (~ b[5]), (~ b[4]), (~ b[3]), (~ b[2]), (~ b[1]), (~ b[0]), 1'b1}), - .cin(1'b0), - .cout(), - .o(wire_nO_o)); + .data({wire_n1li_o[13:12], wire_n1li_o[8], wire_n1li_o[4]}), + .o(wire_n11i_o), + .sel({wire_nlOll_o[4:3]})); defparam - nO.sgate_representation = 0, - nO.width_a = 34, - nO.width_b = 34, - nO.width_o = 34; + n11i.width_data = 4, + n11i.width_sel = 2; + oper_mux n11l + ( + .data({{2{wire_n1li_o[13]}}, wire_n1li_o[9], wire_n1li_o[5]}), + .o(wire_n11l_o), + .sel({wire_nlOll_o[4:3]})); + defparam + n11l.width_data = 4, + n11l.width_sel = 2; + oper_mux n11O + ( + .data({{2{wire_n1li_o[13]}}, wire_n1li_o[10], wire_n1li_o[6]}), + .o(wire_n11O_o), + .sel({wire_nlOll_o[4:3]})); + defparam + n11O.width_data = 4, + n11O.width_sel = 2; + oper_mux n1ii + ( + .data({{3{wire_n1li_o[13]}}, wire_n1li_o[10]}), + .o(wire_n1ii_o), + .sel({wire_nlOll_o[4:3]})); + defparam + n1ii.width_data = 4, + n1ii.width_sel = 2; + oper_mux n1il + ( + .data({{3{wire_n1li_o[13]}}, wire_n1li_o[11]}), + .o(wire_n1il_o), + .sel({wire_nlOll_o[4:3]})); + defparam + n1il.width_data = 4, + n1il.width_sel = 2; + oper_mux n1iO + ( + .data({{2{wire_n1li_o[13]}}, wire_n1li_o[13:12]}), + .o(wire_n1iO_o), + .sel({wire_nlOll_o[4:3]})); + defparam + n1iO.width_data = 4, + n1iO.width_sel = 2; + oper_mux ni00l + ( + .data({1'b1, 1'b0, n01OO, 1'b0}), + .o(wire_ni00l_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + ni00l.width_data = 4, + ni00l.width_sel = 2; + oper_mux ni00O + ( + .data({{2{1'b0}}, n001i, 1'b0}), + .o(wire_ni00O_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + ni00O.width_data = 4, + ni00O.width_sel = 2; + oper_mux ni0ii + ( + .data({{2{1'b0}}, n001l, 1'b0}), + .o(wire_ni0ii_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + ni0ii.width_data = 4, + ni0ii.width_sel = 2; + oper_mux ni0il + ( + .data({{2{1'b0}}, n001O, 1'b0}), + .o(wire_ni0il_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + ni0il.width_data = 4, + ni0il.width_sel = 2; + oper_mux ni0iO + ( + .data({{2{1'b0}}, n000i, 1'b0}), + .o(wire_ni0iO_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + ni0iO.width_data = 4, + ni0iO.width_sel = 2; + oper_mux ni0li + ( + .data({{2{1'b0}}, n000l, 1'b0}), + .o(wire_ni0li_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + ni0li.width_data = 4, + ni0li.width_sel = 2; + oper_mux ni0ll + ( + .data({{2{1'b0}}, n000O, 1'b0}), + .o(wire_ni0ll_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + ni0ll.width_data = 4, + ni0ll.width_sel = 2; + oper_mux ni0lO + ( + .data({{2{1'b0}}, n00ii, 1'b0}), + .o(wire_ni0lO_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + ni0lO.width_data = 4, + ni0lO.width_sel = 2; + oper_mux ni0Oi + ( + .data({{2{1'b0}}, n00il, 1'b0}), + .o(wire_ni0Oi_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + ni0Oi.width_data = 4, + ni0Oi.width_sel = 2; + oper_mux ni0Ol + ( + .data({{2{1'b0}}, n00iO, 1'b0}), + .o(wire_ni0Ol_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + ni0Ol.width_data = 4, + ni0Ol.width_sel = 2; + oper_mux ni0OO + ( + .data({{2{1'b1}}, n00li, 1'b0}), + .o(wire_ni0OO_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + ni0OO.width_data = 4, + ni0OO.width_sel = 2; + oper_mux nii0i + ( + .data({{2{1'b1}}, n00Ol, 1'b0}), + .o(wire_nii0i_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + nii0i.width_data = 4, + nii0i.width_sel = 2; + oper_mux nii0l + ( + .data({{4{1'b1}}, {3{1'b0}}, 1'b1}), + .o(wire_nii0l_o), + .sel({nlOlOO, wire_niiiO_o, niilO})); + defparam + nii0l.width_data = 8, + nii0l.width_sel = 3; + oper_mux nii0O + ( + .data({{3{1'b1}}, 1'b0}), + .o(wire_nii0O_o), + .sel({nlOlOO, wire_niiiO_o})); + defparam + nii0O.width_data = 4, + nii0O.width_sel = 2; + oper_mux nii1i + ( + .data({{2{1'b1}}, n00ll, 1'b0}), + .o(wire_nii1i_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + nii1i.width_data = 4, + nii1i.width_sel = 2; + oper_mux nii1l + ( + .data({{2{1'b1}}, n00lO, 1'b0}), + .o(wire_nii1l_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + nii1l.width_data = 4, + nii1l.width_sel = 2; + oper_mux nii1O + ( + .data({{2{1'b1}}, n00Oi, 1'b0}), + .o(wire_nii1O_o), + .sel({wire_nii0O_o, wire_nii0l_o})); + defparam + nii1O.width_data = 4, + nii1O.width_sel = 2; + oper_mux niiil + ( + .data({{3{1'b0}}, {2{1'b1}}, {6{1'b0}}, {2{1'b1}}, {6{1'b0}}, {2{1'b1}}, {7{1'b0}}, 1'b1, {3{1'b0}}}), + .o(wire_niiil_o), + .sel({nlOllO, wire_niO0O_o[7], nlOlOl, n1lOi, nlOO0i})); + defparam + niiil.width_data = 32, + niiil.width_sel = 5; + oper_mux niiiO + ( + .data({{31{1'b0}}, 1'b1, {25{1'b0}}, {5{1'b1}}, {2{1'b0}}}), + .o(wire_niiiO_o), + .sel({(nlOlOi & n0i1l), n1O0l, n1O0O, n1Oli, n1Oll, n1Oii})); + defparam + niiiO.width_data = 64, + niiiO.width_sel = 6; + oper_mux niiOi + ( + .data({wire_niliO_o, wire_nilil_o, wire_nilll_o, wire_nilli_o}), + .o(wire_niiOi_o), + .sel({nlOOii, wire_nl01O_dataout})); + defparam + niiOi.width_data = 4, + niiOi.width_sel = 2; + oper_mux niiOl + ( + .data({wire_nilli_o, wire_niliO_o, wire_nillO_o, wire_nilll_o}), + .o(wire_niiOl_o), + .sel({nlOOii, wire_nl01O_dataout})); + defparam + niiOl.width_data = 4, + niiOl.width_sel = 2; + oper_mux niiOO + ( + .data({wire_nilll_o, wire_nilli_o, wire_nilOi_o, wire_nillO_o}), + .o(wire_niiOO_o), + .sel({nlOOii, wire_nl01O_dataout})); + defparam + niiOO.width_data = 4, + niiOO.width_sel = 2; oper_mux nil0i ( - .data({wire_nl10O_o, wire_nl10i_o, wire_nl11l_o, wire_niOOO_o}), + .data({wire_nilOO_o, wire_nilOl_o, wire_niO1l_o, wire_niO1i_o}), .o(wire_nil0i_o), - .sel({ni0lOO, ni0lOl})); + .sel({nlOOii, wire_nl01O_dataout})); defparam nil0i.width_data = 4, nil0i.width_sel = 2; oper_mux nil0l ( - .data({wire_nl1ii_o, wire_nl10l_o, wire_nl11O_o, wire_nl11i_o}), + .data({wire_niO1i_o, wire_nilOO_o, wire_niO1O_o, wire_niO1l_o}), .o(wire_nil0l_o), - .sel({ni0lOO, ni0lOl})); + .sel({nlOOii, wire_nl01O_dataout})); defparam nil0l.width_data = 4, nil0l.width_sel = 2; oper_mux nil0O ( - .data({wire_nl1il_o, wire_nl10O_o, wire_nl10i_o, wire_nl11l_o}), + .data({wire_niO1l_o, wire_niO1i_o, wire_niO0i_o, wire_niO1O_o}), .o(wire_nil0O_o), - .sel({ni0lOO, ni0lOl})); + .sel({nlOOii, wire_nl01O_dataout})); defparam nil0O.width_data = 4, nil0O.width_sel = 2; + oper_mux nil1i + ( + .data({wire_nillO_o, wire_nilll_o, wire_nilOl_o, wire_nilOi_o}), + .o(wire_nil1i_o), + .sel({nlOOii, wire_nl01O_dataout})); + defparam + nil1i.width_data = 4, + nil1i.width_sel = 2; + oper_mux nil1l + ( + .data({wire_nilOi_o, wire_nillO_o, wire_nilOO_o, wire_nilOl_o}), + .o(wire_nil1l_o), + .sel({nlOOii, wire_nl01O_dataout})); + defparam + nil1l.width_data = 4, + nil1l.width_sel = 2; + oper_mux nil1O + ( + .data({wire_nilOl_o, wire_nilOi_o, wire_niO1i_o, wire_nilOO_o}), + .o(wire_nil1O_o), + .sel({nlOOii, wire_nl01O_dataout})); + defparam + nil1O.width_data = 4, + nil1O.width_sel = 2; oper_mux nilii ( - .data({wire_nl1iO_o, wire_nl1ii_o, wire_nl10l_o, wire_nl11O_o}), + .data({wire_niO1O_o, wire_niO1l_o, wire_niO0l_o, wire_niO0i_o}), .o(wire_nilii_o), - .sel({ni0lOO, ni0lOl})); + .sel({nlOOii, wire_nl01O_dataout})); defparam nilii.width_data = 4, nilii.width_sel = 2; oper_mux nilil ( - .data({wire_nl1li_o, wire_nl1il_o, wire_nl10O_o, wire_nl10i_o}), + .data({{3{1'b0}}, n011l}), .o(wire_nilil_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam nilil.width_data = 4, nilil.width_sel = 2; oper_mux niliO ( - .data({wire_nl1ll_o, wire_nl1iO_o, wire_nl1ii_o, wire_nl10l_o}), + .data({{3{1'b0}}, n011O}), .o(wire_niliO_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam niliO.width_data = 4, niliO.width_sel = 2; oper_mux nilli ( - .data({wire_nl1lO_o, wire_nl1li_o, wire_nl1il_o, wire_nl10O_o}), + .data({{3{1'b0}}, n010i}), .o(wire_nilli_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam nilli.width_data = 4, nilli.width_sel = 2; oper_mux nilll ( - .data({wire_nl1Oi_o, wire_nl1ll_o, wire_nl1iO_o, wire_nl1ii_o}), + .data({{3{1'b0}}, n010l}), .o(wire_nilll_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam nilll.width_data = 4, nilll.width_sel = 2; oper_mux nillO ( - .data({wire_nl1Ol_o, wire_nl1lO_o, wire_nl1li_o, wire_nl1il_o}), + .data({{2{1'b0}}, n011l, n010O}), .o(wire_nillO_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam nillO.width_data = 4, nillO.width_sel = 2; oper_mux nilOi ( - .data({wire_nl1OO_o, wire_nl1Oi_o, wire_nl1ll_o, wire_nl1iO_o}), + .data({{2{1'b0}}, n011O, n01ii}), .o(wire_nilOi_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam nilOi.width_data = 4, nilOi.width_sel = 2; oper_mux nilOl ( - .data({wire_nl01i_o, wire_nl1Ol_o, wire_nl1lO_o, wire_nl1li_o}), + .data({{2{1'b0}}, n010i, n01il}), .o(wire_nilOl_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam nilOl.width_data = 4, nilOl.width_sel = 2; oper_mux nilOO ( - .data({wire_nl01l_o, wire_nl1OO_o, wire_nl1Oi_o, wire_nl1ll_o}), + .data({{2{1'b0}}, n010l, n01iO}), .o(wire_nilOO_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam nilOO.width_data = 4, nilOO.width_sel = 2; oper_mux niO0i ( - .data({wire_nl00O_o, wire_nl00i_o, wire_nl01l_o, wire_nl1OO_o}), + .data({1'b0, n1OOO, n01iO, n01Oi}), .o(wire_niO0i_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam niO0i.width_data = 4, niO0i.width_sel = 2; oper_mux niO0l ( - .data({wire_nl0ii_o, wire_nl00l_o, wire_nl01O_o, wire_nl01i_o}), + .data({n011l, n011i, n01li, n01Ol}), .o(wire_niO0l_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam niO0l.width_data = 4, niO0l.width_sel = 2; - oper_mux niO0O - ( - .data({wire_nl0il_o, wire_nl00O_o, wire_nl00i_o, wire_nl01l_o}), - .o(wire_niO0O_o), - .sel({ni0lOO, ni0lOl})); - defparam - niO0O.width_data = 4, - niO0O.width_sel = 2; oper_mux niO1i ( - .data({wire_nl01O_o, wire_nl01i_o, wire_nl1Ol_o, wire_nl1lO_o}), + .data({1'b0, n1OlO, n010O, n01li}), .o(wire_niO1i_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam niO1i.width_data = 4, niO1i.width_sel = 2; oper_mux niO1l ( - .data({wire_nl00i_o, wire_nl01l_o, wire_nl1OO_o, wire_nl1Oi_o}), + .data({1'b0, n1OOi, n01ii, n01ll}), .o(wire_niO1l_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam niO1l.width_data = 4, niO1l.width_sel = 2; oper_mux niO1O ( - .data({wire_nl00l_o, wire_nl01O_o, wire_nl01i_o, wire_nl1Ol_o}), + .data({1'b0, n1OOl, n01il, n01lO}), .o(wire_niO1O_o), - .sel({ni0lOO, ni0lOl})); + .sel({n10OO, n1i1i})); defparam niO1O.width_data = 4, niO1O.width_sel = 2; - oper_mux niOii - ( - .data({wire_nl0iO_o, wire_nl0ii_o, wire_nl00l_o, wire_nl01O_o}), - .o(wire_niOii_o), - .sel({ni0lOO, ni0lOl})); - defparam - niOii.width_data = 4, - niOii.width_sel = 2; - oper_mux niOil - ( - .data({wire_nl0li_o, wire_nl0il_o, wire_nl00O_o, wire_nl00i_o}), - .o(wire_niOil_o), - .sel({ni0lOO, ni0lOl})); - defparam - niOil.width_data = 4, - niOil.width_sel = 2; - oper_mux niOiO - ( - .data({ni0lil, wire_nl0iO_o, wire_nl0ii_o, wire_nl00l_o}), - .o(wire_niOiO_o), - .sel({ni0lOO, ni0lOl})); - defparam - niOiO.width_data = 4, - niOiO.width_sel = 2; - oper_mux niOli - ( - .data({ni0lil, wire_nl0li_o, wire_nl0il_o, wire_nl00O_o}), - .o(wire_niOli_o), - .sel({ni0lOO, ni0lOl})); - defparam - niOli.width_data = 4, - niOli.width_sel = 2; - oper_mux niOll - ( - .data({{2{ni0lil}}, wire_nl0iO_o, wire_nl0ii_o}), - .o(wire_niOll_o), - .sel({ni0lOO, ni0lOl})); - defparam - niOll.width_data = 4, - niOll.width_sel = 2; - oper_mux niOlO - ( - .data({{2{ni0lil}}, wire_nl0li_o, wire_nl0il_o}), - .o(wire_niOlO_o), - .sel({ni0lOO, ni0lOl})); - defparam - niOlO.width_data = 4, - niOlO.width_sel = 2; - oper_mux niOOi - ( - .data({{3{ni0lil}}, wire_nl0iO_o}), - .o(wire_niOOi_o), - .sel({ni0lOO, ni0lOl})); - defparam - niOOi.width_data = 4, - niOOi.width_sel = 2; - oper_mux niOOl - ( - .data({{3{ni0lil}}, wire_nl0li_o}), - .o(wire_niOOl_o), - .sel({ni0lOO, ni0lOl})); - defparam - niOOl.width_data = 4, - niOOl.width_sel = 2; - oper_mux niOOO - ( - .data({ni0l0O, ni0iOi, ni0i0l, ni00lO}), - .o(wire_niOOO_o), - .sel({ni0lll, ni0lli})); - defparam - niOOO.width_data = 4, - niOOO.width_sel = 2; - oper_mux nl00i - ( - .data({{3{ni0lil}}, ni0l1i}), - .o(wire_nl00i_o), - .sel({ni0lll, ni0lli})); - defparam - nl00i.width_data = 4, - nl00i.width_sel = 2; - oper_mux nl00l - ( - .data({{3{ni0lil}}, ni0l1l}), - .o(wire_nl00l_o), - .sel({ni0lll, ni0lli})); - defparam - nl00l.width_data = 4, - nl00l.width_sel = 2; - oper_mux nl00O - ( - .data({{3{ni0lil}}, ni0l1O}), - .o(wire_nl00O_o), - .sel({ni0lll, ni0lli})); - defparam - nl00O.width_data = 4, - nl00O.width_sel = 2; - oper_mux nl01i - ( - .data({{2{ni0lil}}, ni0l0O, ni0iOi}), - .o(wire_nl01i_o), - .sel({ni0lll, ni0lli})); - defparam - nl01i.width_data = 4, - nl01i.width_sel = 2; - oper_mux nl01l - ( - .data({{2{ni0lil}}, ni0lii, ni0iOl}), - .o(wire_nl01l_o), - .sel({ni0lll, ni0lli})); - defparam - nl01l.width_data = 4, - nl01l.width_sel = 2; - oper_mux nl01O - ( - .data({{3{ni0lil}}, ni0iOO}), - .o(wire_nl01O_o), - .sel({ni0lll, ni0lli})); - defparam - nl01O.width_data = 4, - nl01O.width_sel = 2; - oper_mux nl0ii - ( - .data({{3{ni0lil}}, ni0l0i}), - .o(wire_nl0ii_o), - .sel({ni0lll, ni0lli})); - defparam - nl0ii.width_data = 4, - nl0ii.width_sel = 2; - oper_mux nl0il - ( - .data({{3{ni0lil}}, ni0l0l}), - .o(wire_nl0il_o), - .sel({ni0lll, ni0lli})); - defparam - nl0il.width_data = 4, - nl0il.width_sel = 2; - oper_mux nl0iO - ( - .data({{3{ni0lil}}, ni0l0O}), - .o(wire_nl0iO_o), - .sel({ni0lll, ni0lli})); - defparam - nl0iO.width_data = 4, - nl0iO.width_sel = 2; - oper_mux nl0li - ( - .data({{3{ni0lil}}, ni0lii}), - .o(wire_nl0li_o), - .sel({ni0lll, ni0lli})); - defparam - nl0li.width_data = 4, - nl0li.width_sel = 2; - oper_mux nl10i - ( - .data({ni0lil, ni0l1l, ni0iiO, ni0i1i}), - .o(wire_nl10i_o), - .sel({ni0lll, ni0lli})); - defparam - nl10i.width_data = 4, - nl10i.width_sel = 2; - oper_mux nl10l - ( - .data({ni0lil, ni0l1O, ni0ili, ni0i1l}), - .o(wire_nl10l_o), - .sel({ni0lll, ni0lli})); - defparam - nl10l.width_data = 4, - nl10l.width_sel = 2; - oper_mux nl10O - ( - .data({ni0lil, ni0l0i, ni0ill, ni0i1O}), - .o(wire_nl10O_o), - .sel({ni0lll, ni0lli})); - defparam - nl10O.width_data = 4, - nl10O.width_sel = 2; - oper_mux nl11i - ( - .data({ni0lii, ni0iOl, ni0i0O, ni00Oi}), - .o(wire_nl11i_o), - .sel({ni0lll, ni0lli})); - defparam - nl11i.width_data = 4, - nl11i.width_sel = 2; - oper_mux nl11l - ( - .data({ni0lil, ni0iOO, ni0iii, ni00Ol}), - .o(wire_nl11l_o), - .sel({ni0lll, ni0lli})); - defparam - nl11l.width_data = 4, - nl11l.width_sel = 2; - oper_mux nl11O - ( - .data({ni0lil, ni0l1i, ni0iil, ni00OO}), - .o(wire_nl11O_o), - .sel({ni0lll, ni0lli})); - defparam - nl11O.width_data = 4, - nl11O.width_sel = 2; - oper_mux nl1ii - ( - .data({ni0lil, ni0l0l, ni0ilO, ni0i0i}), - .o(wire_nl1ii_o), - .sel({ni0lll, ni0lli})); - defparam - nl1ii.width_data = 4, - nl1ii.width_sel = 2; - oper_mux nl1il - ( - .data({ni0lil, ni0l0O, ni0iOi, ni0i0l}), - .o(wire_nl1il_o), - .sel({ni0lll, ni0lli})); - defparam - nl1il.width_data = 4, - nl1il.width_sel = 2; - oper_mux nl1iO - ( - .data({ni0lil, ni0lii, ni0iOl, ni0i0O}), - .o(wire_nl1iO_o), - .sel({ni0lll, ni0lli})); - defparam - nl1iO.width_data = 4, - nl1iO.width_sel = 2; - oper_mux nl1li - ( - .data({{2{ni0lil}}, ni0iOO, ni0iii}), - .o(wire_nl1li_o), - .sel({ni0lll, ni0lli})); - defparam - nl1li.width_data = 4, - nl1li.width_sel = 2; - oper_mux nl1ll - ( - .data({{2{ni0lil}}, ni0l1i, ni0iil}), - .o(wire_nl1ll_o), - .sel({ni0lll, ni0lli})); - defparam - nl1ll.width_data = 4, - nl1ll.width_sel = 2; - oper_mux nl1lO - ( - .data({{2{ni0lil}}, ni0l1l, ni0iiO}), - .o(wire_nl1lO_o), - .sel({ni0lll, ni0lli})); - defparam - nl1lO.width_data = 4, - nl1lO.width_sel = 2; - oper_mux nl1Oi - ( - .data({{2{ni0lil}}, ni0l1O, ni0ili}), - .o(wire_nl1Oi_o), - .sel({ni0lll, ni0lli})); - defparam - nl1Oi.width_data = 4, - nl1Oi.width_sel = 2; - oper_mux nl1Ol - ( - .data({{2{ni0lil}}, ni0l0i, ni0ill}), - .o(wire_nl1Ol_o), - .sel({ni0lll, ni0lli})); - defparam - nl1Ol.width_data = 4, - nl1Ol.width_sel = 2; - oper_mux nl1OO - ( - .data({{2{ni0lil}}, ni0l0l, ni0ilO}), - .o(wire_nl1OO_o), - .sel({ni0lll, ni0lli})); - defparam - nl1OO.width_data = 4, - nl1OO.width_sel = 2; - oper_mux nliliO - ( - .data({1'b1, 1'b0, nl1iOl, 1'b0}), - .o(wire_nliliO_o), - .sel({nll1li, nll00i})); - defparam - nliliO.width_data = 4, - nliliO.width_sel = 2; - oper_mux nlilli - ( - .data({{2{1'b0}}, nl1iOO, 1'b0}), - .o(wire_nlilli_o), - .sel({nll1li, nll00i})); - defparam - nlilli.width_data = 4, - nlilli.width_sel = 2; - oper_mux nlilll - ( - .data({{2{1'b0}}, nl1l1i, 1'b0}), - .o(wire_nlilll_o), - .sel({nll1li, nll00i})); - defparam - nlilll.width_data = 4, - nlilll.width_sel = 2; - oper_mux nlillO - ( - .data({{2{1'b0}}, nl1l1l, 1'b0}), - .o(wire_nlillO_o), - .sel({nll1li, nll00i})); - defparam - nlillO.width_data = 4, - nlillO.width_sel = 2; - oper_mux nlilOi - ( - .data({{2{1'b0}}, nl1l1O, 1'b0}), - .o(wire_nlilOi_o), - .sel({nll1li, nll00i})); - defparam - nlilOi.width_data = 4, - nlilOi.width_sel = 2; - oper_mux nlilOl - ( - .data({{2{1'b0}}, nl1l0i, 1'b0}), - .o(wire_nlilOl_o), - .sel({nll1li, nll00i})); - defparam - nlilOl.width_data = 4, - nlilOl.width_sel = 2; - oper_mux nlilOO - ( - .data({{2{1'b0}}, nl1l0l, 1'b0}), - .o(wire_nlilOO_o), - .sel({nll1li, nll00i})); - defparam - nlilOO.width_data = 4, - nlilOO.width_sel = 2; - oper_mux nliO0i - ( - .data({{2{1'b0}}, nl1liO, 1'b0}), - .o(wire_nliO0i_o), - .sel({nll1li, nll00i})); - defparam - nliO0i.width_data = 4, - nliO0i.width_sel = 2; - oper_mux nliO0l - ( - .data({{2{1'b0}}, nl1lli, 1'b0}), - .o(wire_nliO0l_o), - .sel({nll1li, nll00i})); - defparam - nliO0l.width_data = 4, - nliO0l.width_sel = 2; - oper_mux nliO0O - ( - .data({{2{1'b0}}, nl1lll, 1'b0}), - .o(wire_nliO0O_o), - .sel({nll1li, nll00i})); - defparam - nliO0O.width_data = 4, - nliO0O.width_sel = 2; - oper_mux nliO1i - ( - .data({{2{1'b0}}, nl1l0O, 1'b0}), - .o(wire_nliO1i_o), - .sel({nll1li, nll00i})); - defparam - nliO1i.width_data = 4, - nliO1i.width_sel = 2; - oper_mux nliO1l - ( - .data({{2{1'b0}}, nl1lii, 1'b0}), - .o(wire_nliO1l_o), - .sel({nll1li, nll00i})); - defparam - nliO1l.width_data = 4, - nliO1l.width_sel = 2; - oper_mux nliO1O - ( - .data({{2{1'b0}}, nl1lil, 1'b0}), - .o(wire_nliO1O_o), - .sel({nll1li, nll00i})); - defparam - nliO1O.width_data = 4, - nliO1O.width_sel = 2; - oper_mux nliOii - ( - .data({{2{1'b0}}, nl1llO, 1'b0}), - .o(wire_nliOii_o), - .sel({nll1li, nll00i})); - defparam - nliOii.width_data = 4, - nliOii.width_sel = 2; - oper_mux nliOil - ( - .data({{2{1'b0}}, nl1lOi, 1'b0}), - .o(wire_nliOil_o), - .sel({nll1li, nll00i})); - defparam - nliOil.width_data = 4, - nliOil.width_sel = 2; - oper_mux nliOiO - ( - .data({{2{1'b0}}, nl1lOl, 1'b0}), - .o(wire_nliOiO_o), - .sel({nll1li, nll00i})); - defparam - nliOiO.width_data = 4, - nliOiO.width_sel = 2; - oper_mux nliOli - ( - .data({{2{1'b0}}, nl1lOO, 1'b0}), - .o(wire_nliOli_o), - .sel({nll1li, nll00i})); - defparam - nliOli.width_data = 4, - nliOli.width_sel = 2; - oper_mux nliOll - ( - .data({{2{1'b0}}, nl1O1i, 1'b0}), - .o(wire_nliOll_o), - .sel({nll1li, nll00i})); - defparam - nliOll.width_data = 4, - nliOll.width_sel = 2; - oper_mux nliOlO - ( - .data({{2{1'b0}}, nl1O1l, 1'b0}), - .o(wire_nliOlO_o), - .sel({nll1li, nll00i})); - defparam - nliOlO.width_data = 4, - nliOlO.width_sel = 2; - oper_mux nliOOi - ( - .data({{2{1'b0}}, nl1O1O, 1'b0}), - .o(wire_nliOOi_o), - .sel({nll1li, nll00i})); - defparam - nliOOi.width_data = 4, - nliOOi.width_sel = 2; - oper_mux nliOOl - ( - .data({{2{1'b0}}, nl1O0i, 1'b0}), - .o(wire_nliOOl_o), - .sel({nll1li, nll00i})); - defparam - nliOOl.width_data = 4, - nliOOl.width_sel = 2; - oper_mux nliOOO - ( - .data({{2{1'b0}}, nl1O0l, 1'b0}), - .o(wire_nliOOO_o), - .sel({nll1li, nll00i})); - defparam - nliOOO.width_data = 4, - nliOOO.width_sel = 2; - oper_mux nll01i - ( - .data({{31{1'b0}}, 1'b1, {25{1'b0}}, {5{1'b1}}, {2{1'b0}}}), - .o(wire_nll01i_o), - .sel({(nl1ilO & nl1iOi), nillii, nilliO, nilO0i, nilO0l, nillli})); - defparam - nll01i.width_data = 64, - nll01i.width_sel = 6; - oper_mux nll10i - ( - .data({{2{1'b1}}, nl10Oi, 1'b0}), - .o(wire_nll10i_o), - .sel({nll1li, nll00i})); - defparam - nll10i.width_data = 4, - nll10i.width_sel = 2; - oper_mux nll10l - ( - .data({{2{1'b1}}, nl10Ol, 1'b0}), - .o(wire_nll10l_o), - .sel({nll1li, nll00i})); - defparam - nll10l.width_data = 4, - nll10l.width_sel = 2; - oper_mux nll10O - ( - .data({{2{1'b1}}, nl10OO, 1'b0}), - .o(wire_nll10O_o), - .sel({nll1li, nll00i})); - defparam - nll10O.width_data = 4, - nll10O.width_sel = 2; - oper_mux nll11i - ( - .data({{2{1'b0}}, nl1O0O, 1'b0}), - .o(wire_nll11i_o), - .sel({nll1li, nll00i})); - defparam - nll11i.width_data = 4, - nll11i.width_sel = 2; - oper_mux nll11l - ( - .data({{2{1'b1}}, nl10ll, 1'b0}), - .o(wire_nll11l_o), - .sel({nll1li, nll00i})); - defparam - nll11l.width_data = 4, - nll11l.width_sel = 2; - oper_mux nll11O - ( - .data({{2{1'b1}}, nl10lO, 1'b0}), - .o(wire_nll11O_o), - .sel({nll1li, nll00i})); - defparam - nll11O.width_data = 4, - nll11O.width_sel = 2; - oper_mux nll1ii - ( - .data({{2{1'b1}}, nl1i1i, 1'b0}), - .o(wire_nll1ii_o), - .sel({nll1li, nll00i})); - defparam - nll1ii.width_data = 4, - nll1ii.width_sel = 2; - oper_mux nll1il - ( - .data({{2{1'b1}}, nl1i1l, 1'b0}), - .o(wire_nll1il_o), - .sel({nll1li, nll00i})); - defparam - nll1il.width_data = 4, - nll1il.width_sel = 2; - oper_mux nll1iO - ( - .data({{2{1'b1}}, nl1i1O, 1'b0}), - .o(wire_nll1iO_o), - .sel({nll1li, nll00i})); - defparam - nll1iO.width_data = 4, - nll1iO.width_sel = 2; - oper_mux nll1lO - ( - .data({{4{1'b1}}, {3{1'b0}}, 1'b1}), - .o(wire_nll1lO_o), - .sel({n0Ol0O, wire_nll01i_o, nll1ll})); - defparam - nll1lO.width_data = 8, - nll1lO.width_sel = 3; - oper_mux nll1Oi - ( - .data({{3{1'b1}}, 1'b0}), - .o(wire_nll1Oi_o), - .sel({n0Ol0O, wire_nll01i_o})); - defparam - nll1Oi.width_data = 4, - nll1Oi.width_sel = 2; - oper_mux nll1OO - ( - .data({{3{1'b0}}, {2{1'b1}}, {6{1'b0}}, {2{1'b1}}, {6{1'b0}}, {2{1'b1}}, {7{1'b0}}, 1'b1, {3{1'b0}}}), - .o(wire_nll1OO_o), - .sel({niilii, nlOl0l, n0Ol0l, nil0ll, nili0l})); - defparam - nll1OO.width_data = 32, - nll1OO.width_sel = 5; - oper_mux nllOii - ( - .data({{2{1'b0}}, wire_nlO01i_o, wire_nlO01O_o}), - .o(wire_nllOii_o), - .sel({niil1O, niil0i})); - defparam - nllOii.width_data = 4, - nllOii.width_sel = 2; - oper_mux nllOil - ( - .data({{2{1'b0}}, wire_nlO01l_o, wire_nlO00i_o}), - .o(wire_nllOil_o), - .sel({niil1O, niil0i})); - defparam - nllOil.width_data = 4, - nllOil.width_sel = 2; - oper_mux nllOiO - ( - .data({1'b0, wire_nlO01i_o, wire_nlO01O_o, wire_nlO00l_o}), - .o(wire_nllOiO_o), - .sel({niil1O, niil0i})); - defparam - nllOiO.width_data = 4, - nllOiO.width_sel = 2; - oper_mux nllOli - ( - .data({1'b0, wire_nlO01l_o, wire_nlO00i_o, wire_nlO00O_o}), - .o(wire_nllOli_o), - .sel({niil1O, niil0i})); - defparam - nllOli.width_data = 4, - nllOli.width_sel = 2; - oper_mux nllOll - ( - .data({wire_nlO01i_o, wire_nlO01O_o, wire_nlO00l_o, wire_nlO0ii_o}), - .o(wire_nllOll_o), - .sel({niil1O, niil0i})); - defparam - nllOll.width_data = 4, - nllOll.width_sel = 2; - oper_mux nllOlO - ( - .data({wire_nlO01l_o, wire_nlO00i_o, wire_nlO00O_o, wire_nlO0il_o}), - .o(wire_nllOlO_o), - .sel({niil1O, niil0i})); - defparam - nllOlO.width_data = 4, - nllOlO.width_sel = 2; - oper_mux nllOOi - ( - .data({wire_nlO01O_o, wire_nlO00l_o, wire_nlO0ii_o, wire_nlO0iO_o}), - .o(wire_nllOOi_o), - .sel({niil1O, niil0i})); - defparam - nllOOi.width_data = 4, - nllOOi.width_sel = 2; - oper_mux nllOOl - ( - .data({wire_nlO00i_o, wire_nlO00O_o, wire_nlO0il_o, wire_nlO0li_o}), - .o(wire_nllOOl_o), - .sel({niil1O, niil0i})); - defparam - nllOOl.width_data = 4, - nllOOl.width_sel = 2; - oper_mux nllOOO - ( - .data({wire_nlO00l_o, wire_nlO0ii_o, wire_nlO0iO_o, wire_nlO0ll_o}), - .o(wire_nllOOO_o), - .sel({niil1O, niil0i})); - defparam - nllOOO.width_data = 4, - nllOOO.width_sel = 2; - oper_mux nlO00i - ( - .data({{3{1'b0}}, niO0li}), - .o(wire_nlO00i_o), - .sel({niiiOi, niil1i})); - defparam - nlO00i.width_data = 4, - nlO00i.width_sel = 2; - oper_mux nlO00l - ( - .data({{3{1'b0}}, niO0ll}), - .o(wire_nlO00l_o), - .sel({niiiOi, niil1i})); - defparam - nlO00l.width_data = 4, - nlO00l.width_sel = 2; - oper_mux nlO00O - ( - .data({{3{1'b0}}, niO0lO}), - .o(wire_nlO00O_o), - .sel({niiiOi, niil1i})); - defparam - nlO00O.width_data = 4, - nlO00O.width_sel = 2; - oper_mux nlO01i - ( - .data({{3{1'b0}}, niO0ii}), - .o(wire_nlO01i_o), - .sel({niiiOi, niil1i})); - defparam - nlO01i.width_data = 4, - nlO01i.width_sel = 2; - oper_mux nlO01l - ( - .data({{3{1'b0}}, niO0il}), - .o(wire_nlO01l_o), - .sel({niiiOi, niil1i})); - defparam - nlO01l.width_data = 4, - nlO01l.width_sel = 2; - oper_mux nlO01O - ( - .data({{3{1'b0}}, niO0iO}), - .o(wire_nlO01O_o), - .sel({niiiOi, niil1i})); - defparam - nlO01O.width_data = 4, - nlO01O.width_sel = 2; - oper_mux nlO0ii - ( - .data({{3{1'b0}}, niO0Oi}), - .o(wire_nlO0ii_o), - .sel({niiiOi, niil1i})); - defparam - nlO0ii.width_data = 4, - nlO0ii.width_sel = 2; - oper_mux nlO0il - ( - .data({{3{1'b0}}, niO0Ol}), - .o(wire_nlO0il_o), - .sel({niiiOi, niil1i})); - defparam - nlO0il.width_data = 4, - nlO0il.width_sel = 2; - oper_mux nlO0iO - ( - .data({{2{1'b0}}, niO0ii, niO0OO}), - .o(wire_nlO0iO_o), - .sel({niiiOi, niil1i})); - defparam - nlO0iO.width_data = 4, - nlO0iO.width_sel = 2; - oper_mux nlO0li - ( - .data({{2{1'b0}}, niO0il, niOi1i}), - .o(wire_nlO0li_o), - .sel({niiiOi, niil1i})); - defparam - nlO0li.width_data = 4, - nlO0li.width_sel = 2; - oper_mux nlO0ll - ( - .data({{2{1'b0}}, niO0iO, niOi1l}), - .o(wire_nlO0ll_o), - .sel({niiiOi, niil1i})); - defparam - nlO0ll.width_data = 4, - nlO0ll.width_sel = 2; - oper_mux nlO0lO - ( - .data({{2{1'b0}}, niO0li, niOi1O}), - .o(wire_nlO0lO_o), - .sel({niiiOi, niil1i})); - defparam - nlO0lO.width_data = 4, - nlO0lO.width_sel = 2; - oper_mux nlO0Oi - ( - .data({{2{1'b0}}, niO0ll, niOi0i}), - .o(wire_nlO0Oi_o), - .sel({niiiOi, niil1i})); - defparam - nlO0Oi.width_data = 4, - nlO0Oi.width_sel = 2; - oper_mux nlO0Ol - ( - .data({{2{1'b0}}, niO0lO, niOi0l}), - .o(wire_nlO0Ol_o), - .sel({niiiOi, niil1i})); - defparam - nlO0Ol.width_data = 4, - nlO0Ol.width_sel = 2; - oper_mux nlO0OO - ( - .data({{2{1'b0}}, niO0Oi, niOi0O}), - .o(wire_nlO0OO_o), - .sel({niiiOi, niil1i})); - defparam - nlO0OO.width_data = 4, - nlO0OO.width_sel = 2; - oper_mux nlO10i - ( - .data({wire_nlO0iO_o, wire_nlO0ll_o, wire_nlO0Oi_o, wire_nlO0OO_o}), - .o(wire_nlO10i_o), - .sel({niil1O, niil0i})); - defparam - nlO10i.width_data = 4, - nlO10i.width_sel = 2; - oper_mux nlO10l - ( - .data({wire_nlO0li_o, wire_nlO0lO_o, wire_nlO0Ol_o, wire_nlOi1i_o}), - .o(wire_nlO10l_o), - .sel({niil1O, niil0i})); - defparam - nlO10l.width_data = 4, - nlO10l.width_sel = 2; - oper_mux nlO10O - ( - .data({wire_nlO0ll_o, wire_nlO0Oi_o, wire_nlO0OO_o, wire_nlOi1l_o}), - .o(wire_nlO10O_o), - .sel({niil1O, niil0i})); - defparam - nlO10O.width_data = 4, - nlO10O.width_sel = 2; - oper_mux nlO11i - ( - .data({wire_nlO00O_o, wire_nlO0il_o, wire_nlO0li_o, wire_nlO0lO_o}), - .o(wire_nlO11i_o), - .sel({niil1O, niil0i})); - defparam - nlO11i.width_data = 4, - nlO11i.width_sel = 2; - oper_mux nlO11l - ( - .data({wire_nlO0ii_o, wire_nlO0iO_o, wire_nlO0ll_o, wire_nlO0Oi_o}), - .o(wire_nlO11l_o), - .sel({niil1O, niil0i})); - defparam - nlO11l.width_data = 4, - nlO11l.width_sel = 2; - oper_mux nlO11O - ( - .data({wire_nlO0il_o, wire_nlO0li_o, wire_nlO0lO_o, wire_nlO0Ol_o}), - .o(wire_nlO11O_o), - .sel({niil1O, niil0i})); - defparam - nlO11O.width_data = 4, - nlO11O.width_sel = 2; - oper_mux nlO1ii - ( - .data({wire_nlO0lO_o, wire_nlO0Ol_o, wire_nlOi1i_o, wire_nlOi1O_o}), - .o(wire_nlO1ii_o), - .sel({niil1O, niil0i})); - defparam - nlO1ii.width_data = 4, - nlO1ii.width_sel = 2; - oper_mux nlO1il - ( - .data({wire_nlO0Oi_o, wire_nlO0OO_o, wire_nlOi1l_o, wire_nlOi0i_o}), - .o(wire_nlO1il_o), - .sel({niil1O, niil0i})); - defparam - nlO1il.width_data = 4, - nlO1il.width_sel = 2; - oper_mux nlO1iO - ( - .data({wire_nlO0Ol_o, wire_nlOi1i_o, wire_nlOi1O_o, wire_nlOi0l_o}), - .o(wire_nlO1iO_o), - .sel({niil1O, niil0i})); - defparam - nlO1iO.width_data = 4, - nlO1iO.width_sel = 2; - oper_mux nlO1li + oper_mux nllOi ( - .data({wire_nlO0OO_o, wire_nlOi1l_o, wire_nlOi0i_o, wire_nlOi0O_o}), - .o(wire_nlO1li_o), - .sel({niil1O, niil0i})); + .data({wire_nlOOO_o, wire_nlOOl_o, wire_nlOOi_o, wire_nlOlO_o}), + .o(wire_nllOi_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlO1li.width_data = 4, - nlO1li.width_sel = 2; - oper_mux nlO1ll + nllOi.width_data = 4, + nllOi.width_sel = 2; + oper_mux nllOl ( - .data({wire_nlOi1i_o, wire_nlOi1O_o, wire_nlOi0l_o, wire_nlOiii_o}), - .o(wire_nlO1ll_o), - .sel({niil1O, niil0i})); + .data({wire_n11i_o, wire_nlOOO_o, wire_nlOOl_o, wire_nlOOi_o}), + .o(wire_nllOl_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlO1ll.width_data = 4, - nlO1ll.width_sel = 2; - oper_mux nlO1lO + nllOl.width_data = 4, + nllOl.width_sel = 2; + oper_mux nllOO ( - .data({wire_nlOi1l_o, wire_nlOi0i_o, wire_nlOi0O_o, wire_nlOiil_o}), - .o(wire_nlO1lO_o), - .sel({niil1O, niil0i})); + .data({wire_n11l_o, wire_n11i_o, wire_nlOOO_o, wire_nlOOl_o}), + .o(wire_nllOO_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlO1lO.width_data = 4, - nlO1lO.width_sel = 2; - oper_mux nlO1Oi + nllOO.width_data = 4, + nllOO.width_sel = 2; + oper_mux nlO0i ( - .data({wire_nlOi1O_o, wire_nlOi0l_o, wire_nlOiii_o, wire_nlOiiO_o}), - .o(wire_nlO1Oi_o), - .sel({niil1O, niil0i})); + .data({wire_n10O_o, wire_n10l_o, wire_n10i_o, wire_n11O_o}), + .o(wire_nlO0i_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlO1Oi.width_data = 4, - nlO1Oi.width_sel = 2; - oper_mux nlO1Ol + nlO0i.width_data = 4, + nlO0i.width_sel = 2; + oper_mux nlO0l ( - .data({wire_nlOi0i_o, wire_nlOi0O_o, wire_nlOiil_o, wire_nlOili_o}), - .o(wire_nlO1Ol_o), - .sel({niil1O, niil0i})); + .data({wire_n1ii_o, wire_n10O_o, wire_n10l_o, wire_n10i_o}), + .o(wire_nlO0l_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlO1Ol.width_data = 4, - nlO1Ol.width_sel = 2; - oper_mux nlO1OO + nlO0l.width_data = 4, + nlO0l.width_sel = 2; + oper_mux nlO0O ( - .data({wire_nlOi0l_o, wire_nlOiii_o, wire_nlOiiO_o, wire_nlOill_o}), - .o(wire_nlO1OO_o), - .sel({niil1O, niil0i})); + .data({wire_n1il_o, wire_n1ii_o, wire_n10O_o, wire_n10l_o}), + .o(wire_nlO0O_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlO1OO.width_data = 4, - nlO1OO.width_sel = 2; - oper_mux nlOi0i + nlO0O.width_data = 4, + nlO0O.width_sel = 2; + oper_mux nlO1i ( - .data({1'b0, nilOiO, niOi1l, niOili}), - .o(wire_nlOi0i_o), - .sel({niiiOi, niil1i})); + .data({wire_n11O_o, wire_n11l_o, wire_n11i_o, wire_nlOOO_o}), + .o(wire_nlO1i_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlOi0i.width_data = 4, - nlOi0i.width_sel = 2; - oper_mux nlOi0l + nlO1i.width_data = 4, + nlO1i.width_sel = 2; + oper_mux nlO1l ( - .data({1'b0, nilOli, niOi1O, niOill}), - .o(wire_nlOi0l_o), - .sel({niiiOi, niil1i})); + .data({wire_n10i_o, wire_n11O_o, wire_n11l_o, wire_n11i_o}), + .o(wire_nlO1l_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlOi0l.width_data = 4, - nlOi0l.width_sel = 2; - oper_mux nlOi0O + nlO1l.width_data = 4, + nlO1l.width_sel = 2; + oper_mux nlO1O ( - .data({1'b0, nilOll, niOi0i, niOilO}), - .o(wire_nlOi0O_o), - .sel({niiiOi, niil1i})); + .data({wire_n10l_o, wire_n10i_o, wire_n11O_o, wire_n11l_o}), + .o(wire_nlO1O_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlOi0O.width_data = 4, - nlOi0O.width_sel = 2; - oper_mux nlOi1i + nlO1O.width_data = 4, + nlO1O.width_sel = 2; + oper_mux nlOii ( - .data({{2{1'b0}}, niO0Ol, niOiii}), - .o(wire_nlOi1i_o), - .sel({niiiOi, niil1i})); + .data({wire_n1iO_o, wire_n1il_o, wire_n1ii_o, wire_n10O_o}), + .o(wire_nlOii_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlOi1i.width_data = 4, - nlOi1i.width_sel = 2; - oper_mux nlOi1l + nlOii.width_data = 4, + nlOii.width_sel = 2; + oper_mux nlOil ( - .data({1'b0, nilOii, niO0OO, niOiil}), - .o(wire_nlOi1l_o), - .sel({niiiOi, niil1i})); + .data({wire_n1li_o[13], wire_n1iO_o, wire_n1il_o, wire_n1ii_o}), + .o(wire_nlOil_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlOi1l.width_data = 4, - nlOi1l.width_sel = 2; - oper_mux nlOi1O + nlOil.width_data = 4, + nlOil.width_sel = 2; + oper_mux nlOiO ( - .data({1'b0, nilOil, niOi1i, niOiiO}), - .o(wire_nlOi1O_o), - .sel({niiiOi, niil1i})); + .data({{2{wire_n1li_o[13]}}, wire_n1iO_o, wire_n1il_o}), + .o(wire_nlOiO_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlOi1O.width_data = 4, - nlOi1O.width_sel = 2; - oper_mux nlOiii + nlOiO.width_data = 4, + nlOiO.width_sel = 2; + oper_mux nlOli ( - .data({1'b0, nilOlO, niOi0l, niOiOi}), - .o(wire_nlOiii_o), - .sel({niiiOi, niil1i})); + .data({{3{wire_n1li_o[13]}}, wire_n1iO_o}), + .o(wire_nlOli_o), + .sel({wire_nlOll_o[2:1]})); defparam - nlOiii.width_data = 4, - nlOiii.width_sel = 2; - oper_mux nlOiil + nlOli.width_data = 4, + nlOli.width_sel = 2; + oper_mux nlOlO ( - .data({1'b0, nilOOi, niOi0O, niOiOl}), - .o(wire_nlOiil_o), - .sel({niiiOi, niil1i})); + .data({wire_n1li_o[12], wire_n1li_o[8], wire_n1li_o[4], wire_n1li_o[0]}), + .o(wire_nlOlO_o), + .sel({wire_nlOll_o[4:3]})); defparam - nlOiil.width_data = 4, - nlOiil.width_sel = 2; - oper_mux nlOiiO + nlOlO.width_data = 4, + nlOlO.width_sel = 2; + oper_mux nlOOi ( - .data({1'b0, nilOOl, niOiii, niOiOO}), - .o(wire_nlOiiO_o), - .sel({niiiOi, niil1i})); + .data({wire_n1li_o[13], wire_n1li_o[9], wire_n1li_o[5], wire_n1li_o[1]}), + .o(wire_nlOOi_o), + .sel({wire_nlOll_o[4:3]})); defparam - nlOiiO.width_data = 4, - nlOiiO.width_sel = 2; - oper_mux nlOili + nlOOi.width_data = 4, + nlOOi.width_sel = 2; + oper_mux nlOOl ( - .data({niO0ii, nilOOO, niOiil, niOl1i}), - .o(wire_nlOili_o), - .sel({niiiOi, niil1i})); + .data({wire_n1li_o[13], wire_n1li_o[10], wire_n1li_o[6], wire_n1li_o[2]}), + .o(wire_nlOOl_o), + .sel({wire_nlOll_o[4:3]})); defparam - nlOili.width_data = 4, - nlOili.width_sel = 2; - oper_mux nlOill + nlOOl.width_data = 4, + nlOOl.width_sel = 2; + oper_mux nlOOO ( - .data({niO0il, niO11i, niOiiO, niOl1l}), - .o(wire_nlOill_o), - .sel({niiiOi, niil1i})); + .data({wire_n1li_o[13], wire_n1li_o[11], wire_n1li_o[7], wire_n1li_o[3]}), + .o(wire_nlOOO_o), + .sel({wire_nlOll_o[4:3]})); defparam - nlOill.width_data = 4, - nlOill.width_sel = 2; + nlOOO.width_data = 4, + nlOOO.width_sel = 2; assign - n0OilO = ((((((((((~ nlOl0l) & (~ nlOl0i)) & nlOl1O) & nlOl1l) & nlOl1i) & nlOiOO) & nlOiOl) & nlOiOi) & nlOilO) & nllO0O), - n0OiOi = (((((((((((((((((((((((~ nii1OO) & (~ nii1Ol)) & (~ nii1Oi)) & (~ nii1lO)) & (~ nii1ll)) & (~ nii1li)) & (~ nii1iO)) & (~ nii1il)) & (~ nii1ii)) & (~ nii10O)) & (~ nii10l)) & (~ nii10i)) & (~ nii11O)) & (~ nii11l)) & (~ nii11i)) & (~ ni0OOO)) & (~ ni0OOl)) & (~ ni0OOi)) & (~ ni0OlO)) & (~ ni0Oll)) & (~ ni0Oli)) & (~ ni0OiO)) & (~ ni0Oil)), - n0OiOl = (((((((((((((((((((((((~ ni1OOl) & (~ ni1OOi)) & (~ ni1OlO)) & (~ ni1Oll)) & (~ ni1Oli)) & (~ ni1OiO)) & (~ ni1Oil)) & (~ ni1Oii)) & (~ ni1O0O)) & (~ ni1O0l)) & (~ ni1O0i)) & (~ ni1O1O)) & (~ ni1O1l)) & (~ ni1O1i)) & (~ ni1lOO)) & (~ ni1lOl)) & (~ ni1lOi)) & (~ ni1llO)) & (~ ni1lll)) & (~ ni1lli)) & (~ ni1liO)) & (~ ni1lil)) & (~ ni1lii)), - n0OiOO = ((((((((~ nil1Oi) & (~ nil1lO)) & (~ nil1ll)) & (~ nil1li)) & (~ nil1iO)) & (~ nil1il)) & (~ nil1ii)) & (~ nil10O)), - n0Ol0i = ((((((((~ wire_ni_dataout) & (~ wire_nlO_dataout)) & (~ wire_nll_dataout)) & (~ wire_nli_dataout)) & (~ wire_niO_dataout)) & (~ wire_nil_dataout)) & (~ wire_nii_dataout)) & (~ wire_n0O_dataout)), - n0Ol0l = (nil10i & nil01i), - n0Ol0O = ((nillii | nilliO) | ((nilO0i & nilO0l) & nillli)), - n0Ol1i = (((((((nil1Oi & nil1lO) & nil1ll) & nil1li) & nil1iO) & nil1il) & nil1ii) & nil10O), - n0Ol1l = (((((((wire_ni_dataout & wire_nlO_dataout) & wire_nll_dataout) & wire_nli_dataout) & wire_niO_dataout) & wire_nil_dataout) & wire_nii_dataout) & wire_n0O_dataout), - n0Ol1O = (((((~ wire_n10lO_dataout) & niiiOi) & niil1i) & (~ niil1O)) & niil0i), - n0Olii = ((((~ n1iii) & (~ n1i0O)) & (~ n1i0l)) & (~ n1i0i)), - n0Olil = ((((((((~ n1lOl) & (~ n1lOi)) & (~ n1llO)) & (~ n1lll)) & (~ n1lli)) & (~ n1liO)) & (~ n1lil)) & (~ n1lii)), - n0OliO = ((((((((((((((((~ niiilO) & (~ niiill)) & (~ niiili)) & (~ niiiiO)) & (~ niiiil)) & (~ niiiii)) & (~ niii0O)) & (~ niii0l)) & (~ niii0i)) & (~ niii1O)) & (~ niii1l)) & (~ niii1i)) & (~ nii0OO)) & (~ nii0Ol)) & (~ nii0Oi)) & (~ nii0lO)), - n0Olli = 1'b1, - n0Olll = (ni1l1O ^ ni1l0i), - q = {nilO0O, wire_nll1iO_o, wire_nll1il_o, wire_nll1ii_o, wire_nll10O_o, wire_nll10l_o, wire_nll10i_o, wire_nll11O_o, wire_nll11l_o, wire_nll11i_o, wire_nliOOO_o, wire_nliOOl_o, wire_nliOOi_o, wire_nliOlO_o, wire_nliOll_o, wire_nliOli_o, wire_nliOiO_o, wire_nliOil_o, wire_nliOii_o, wire_nliO0O_o, wire_nliO0l_o, wire_nliO0i_o, wire_nliO1O_o, wire_nliO1l_o, wire_nliO1i_o, wire_nlilOO_o, wire_nlilOl_o, wire_nlilOi_o, wire_nlillO_o, wire_nlilll_o, wire_nlilli_o, wire_nliliO_o}; + nlOliO = ((((((((((~ n100i) & (~ n101O)) & (~ n101l)) & (~ n101i)) & (~ n11OO)) & (~ n11Ol)) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & (~ n11li)), + nlOlli = ((((((((((~ wire_nil_dataout) & (~ wire_nii_dataout)) & (~ wire_n0O_dataout)) & (~ wire_n0l_dataout)) & (~ wire_n0i_dataout)) & (~ wire_n1O_dataout)) & (~ wire_n1l_dataout)) & (~ wire_n1i_dataout)) & (~ wire_nlOO_dataout)) & (~ wire_nlOl_dataout)), + nlOlll = ((((n110i & n111O) & n111l) & n111i) & nlOOOO), + nlOllO = (((wire_nl01O_dataout & nlOOii) & n10OO) & n1i1i), + nlOlOi = (((((((~ n0i1i) & (~ n00OO)) & n00Ol) & n00Oi) & n00lO) & n00ll) & n00li), + nlOlOl = (nlOO0O & nlOO1O), + nlOlOO = ((n1O0l | n1O0O) | ((n1Oli & n1Oll) & n1Oii)), + nlOO0i = (((((~ n1l0i) & (~ n1l1O)) & (~ n1l1l)) & (~ n1l1i)) & (~ n1iOO)), + nlOO0l = ((((n1l0i & n1l1O) & n1l1l) & n1l1i) & n1iOO), + nlOO0O = ((~ n1ilO) & n1iOi), + nlOO1i = (nlOO0l & n1O1O), + nlOO1l = (n1ilO & n1O1i), + nlOO1O = ((~ nlOO0l) & (~ nlOO0i)), + nlOOii = ((~ wire_nl00O_dataout) & (~ wire_nl00l_dataout)), + nlOOil = ((((((((~ wire_nl0Ol_o[6]) & (~ wire_nl0Ol_o[7])) & (~ wire_nl0Ol_o[8])) & (~ wire_nl0Ol_o[9])) & (~ wire_nl0Ol_o[10])) & (~ wire_nl0Ol_o[11])) & (~ wire_nl0Ol_o[12])) & (~ wire_nl0Ol_o[13])), + nlOOiO = 1'b1, + nlOOli = (((((~ wire_ni_dataout) & (~ wire_nlO_dataout)) & (~ wire_nll_dataout)) & (~ wire_nli_dataout)) & (~ wire_niO_dataout)), + q = {((~ nlOlOO) & n1O0i), wire_nii0i_o, wire_nii1O_o, wire_nii1l_o, wire_nii1i_o, wire_ni0OO_o, wire_ni0Ol_o, wire_ni0Oi_o, wire_ni0lO_o, wire_ni0ll_o, wire_ni0li_o, wire_ni0iO_o, wire_ni0il_o, wire_ni0ii_o, wire_ni00O_o, wire_ni00l_o}; endmodule //ip_fp_add //synopsys translate_on //VALID FILE diff --git a/ip/ip_fp_add_sim/mentor/msim_setup.tcl b/ip/ip_fp_add_sim/mentor/msim_setup.tcl index f1ebd9b..3cc824c 100644 --- a/ip/ip_fp_add_sim/mentor/msim_setup.tcl +++ b/ip/ip_fp_add_sim/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.04:46:09 +# ACDS 20.1 720 linux 2023.10.21.20:34:02 # ---------------------------------------- # Initialize variables diff --git a/ip/ip_fp_add_sim/synopsys/vcs/vcs_setup.sh b/ip/ip_fp_add_sim/synopsys/vcs/vcs_setup.sh index ed96edc..6ccf6e2 100755 --- a/ip/ip_fp_add_sim/synopsys/vcs/vcs_setup.sh +++ b/ip/ip_fp_add_sim/synopsys/vcs/vcs_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.04:46:09 +# ACDS 20.1 720 linux 2023.10.21.20:34:02 # ---------------------------------------- # vcs - auto-generated simulation script @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.04:46:09 +# ACDS 20.1 720 linux 2023.10.21.20:34:02 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="ip_fp_add" diff --git a/ip/ip_fp_add_sim/synopsys/vcsmx/vcsmx_setup.sh b/ip/ip_fp_add_sim/synopsys/vcsmx/vcsmx_setup.sh index 0e88a36..72d3aea 100755 --- a/ip/ip_fp_add_sim/synopsys/vcsmx/vcsmx_setup.sh +++ b/ip/ip_fp_add_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.04:46:09 +# ACDS 20.1 720 linux 2023.10.21.20:34:02 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,7 +107,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.04:46:09 +# ACDS 20.1 720 linux 2023.10.21.20:34:02 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="ip_fp_add" diff --git a/ip/ip_fp_mul.cmp b/ip/ip_fp_mul.cmp index f2c0a07..21d4c39 100644 --- a/ip/ip_fp_mul.cmp +++ b/ip/ip_fp_mul.cmp @@ -2,9 +2,10 @@ port ( clk : in std_logic := 'X'; -- clk areset : in std_logic := 'X'; -- reset - a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a - b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b - q : out std_logic_vector(31 downto 0) -- q + en : in std_logic_vector(0 downto 0) := (others => 'X'); -- en + a : in std_logic_vector(15 downto 0) := (others => 'X'); -- a + b : in std_logic_vector(15 downto 0) := (others => 'X'); -- b + q : out std_logic_vector(15 downto 0) -- q ); end component ip_fp_mul; diff --git a/ip/ip_fp_mul.qip b/ip/ip_fp_mul.qip index 043d6a2..f6114d9 100644 --- a/ip/ip_fp_mul.qip +++ b/ip/ip_fp_mul.qip @@ -29,20 +29,20 @@ set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COM set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Q09NUEFSRV9mdW5jdGlvbg==::TUlO::TmFtZQ==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Uk9PVFNfZnVuY3Rpb24=::U1FSVA==::TmFtZQ==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZGZ1bmN0aW9u::TVVM::ZGVyaXZlZGZ1bmN0aW9u" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfZm9ybWF0::c2luZ2xl::Rm9ybWF0" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfZXhw::OA==::RXhwb25lbnQ=" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfZXhwX2Rlcml2ZWQ=::OA==::ZnBfZXhwX2Rlcml2ZWQ=" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MjM=::TWFudGlzc2E=" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MjM=::ZnBfbWFuX2Rlcml2ZWQ=" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfZm9ybWF0::Y3VzdG9t::Rm9ybWF0" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfZXhw::NQ==::RXhwb25lbnQ=" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfZXhwX2Rlcml2ZWQ=::NQ==::ZnBfZXhwX2Rlcml2ZWQ=" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MTA=::TWFudGlzc2E=" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MTA=::ZnBfbWFuX2Rlcml2ZWQ=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZXhwb25lbnRfd2lkdGg=::MjM=::RXhwb25lbnQgV2lkdGg=" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MjAw::VGFyZ2V0" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::Mg==::VGFyZ2V0" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MTAw::VGFyZ2V0" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::NA==::VGFyZ2V0" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cGVyZm9ybWFuY2VfZ29hbA==::ZnJlcXVlbmN5::R29hbA==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZQ==::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyBhd2F5IGZyb20gemVybw==::TW9kZQ==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZV9kZXJpdmVk::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyB0byBldmVu::TW9kZQ==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "dXNlX3JvdW5kaW5nX21vZGU=::dHJ1ZQ==::dXNlX3JvdW5kaW5nX21vZGU=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZmFpdGhmdWxfcm91bmRpbmc=::dHJ1ZQ==::UmVsYXggcm91bmRpbmcgdG8gcm91bmQgdXAgb3IgZG93biB0byByZWR1Y2UgcmVzb3VyY2UgdXNhZ2U=" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Z2VuX2VuYWJsZQ==::ZmFsc2U=::R2VuZXJhdGUgYW4gZW5hYmxlIHBvcnQ=" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Z2VuX2VuYWJsZQ==::dHJ1ZQ==::R2VuZXJhdGUgYW4gZW5hYmxlIHBvcnQ=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZGl2aWRlX3R5cGU=::MA==::TWV0aG9k" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "c2VsZWN0X3NpZ25hbF9lbmFibGU=::ZmFsc2U=::VXNlIFNlbGVjdCBTaWduYWw=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "c2NhbGVfYnlfcGk=::ZmFsc2U=::UmVwcmVzZW50IGFuZ2xlIGFzIG11bHRpcGxlIG9mIFBp" @@ -52,8 +52,8 @@ set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COM set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF93aWR0aA==::MzI=::V2lkdGg=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF9mcmFjdGlvbg==::MA==::RnJhY3Rpb24=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF9zaWdu::MQ==::U2lnbg==" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MA==::ZnJlcXVlbmN5X2ZlZWRiYWNr" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::Ng==::bGF0ZW5jeV9mZWVkYmFjaw==" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MTA4::ZnJlcXVlbmN5X2ZlZWRiYWNr" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::Mw==::bGF0ZW5jeV9mZWVkYmFjaw==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Zm9yY2VfZWxhYm9yYXRl::MA==::Zm9yY2VfZWxhYm9yYXRl" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2Zvcm1hdA==::c2luZ2xl::T3V0cHV0IEZvcm1hdA==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cA==::OA==::T3V0cHV0IEV4cG9uZW50" @@ -68,8 +68,8 @@ set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COM set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2hhcmRfZnA=::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "bWFudWFsX2RzcF9wbGFubmluZw==::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "Zm9yY2VSZWdpc3RlcnM=::MTExMQ==::Zm9yY2VSZWdpc3RlcnM=" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0RTUF9wYXJhbQ==::Mg==::TXVsdGlwbGllcw==" -set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::MjQ2::TFVUcw==" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0RTUF9wYXJhbQ==::MQ==::TXVsdGlwbGllcw==" +set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::MTE5::TFVUcw==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX01CSVRfcGFyYW0=::MA==::TWVtb3J5IEJpdHM=" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX01CTE9DS19wYXJhbQ==::MA==::TWVtb3J5IEJsb2Nrcw==" set_global_assignment -entity "ip_fp_mul_0002" -library "ip_fp_mul" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==" diff --git a/ip/ip_fp_mul.v b/ip/ip_fp_mul.v index 9585ce3..22fa2bb 100644 --- a/ip/ip_fp_mul.v +++ b/ip/ip_fp_mul.v @@ -8,14 +8,16 @@ module ip_fp_mul ( input wire clk, // clk.clk input wire areset, // areset.reset - input wire [31:0] a, // a.a - input wire [31:0] b, // b.b - output wire [31:0] q // q.q + input wire [0:0] en, // en.en + input wire [15:0] a, // a.a + input wire [15:0] b, // b.b + output wire [15:0] q // q.q ); ip_fp_mul_0002 ip_fp_mul_inst ( .clk (clk), // clk.clk .areset (areset), // areset.reset + .en (en), // en.en .a (a), // a.a .b (b), // b.b .q (q) // q.q @@ -57,16 +59,16 @@ endmodule // Retrieval info: <generic name="TRIG_function" value="SIN" /> // Retrieval info: <generic name="COMPARE_function" value="MIN" /> // Retrieval info: <generic name="ROOTS_function" value="SQRT" /> -// Retrieval info: <generic name="fp_format" value="single" /> -// Retrieval info: <generic name="fp_exp" value="8" /> -// Retrieval info: <generic name="fp_man" value="23" /> +// Retrieval info: <generic name="fp_format" value="custom" /> +// Retrieval info: <generic name="fp_exp" value="5" /> +// Retrieval info: <generic name="fp_man" value="10" /> // Retrieval info: <generic name="exponent_width" value="23" /> -// Retrieval info: <generic name="frequency_target" value="200" /> -// Retrieval info: <generic name="latency_target" value="2" /> +// Retrieval info: <generic name="frequency_target" value="100" /> +// Retrieval info: <generic name="latency_target" value="4" /> // Retrieval info: <generic name="performance_goal" value="frequency" /> // Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" /> // Retrieval info: <generic name="faithful_rounding" value="true" /> -// Retrieval info: <generic name="gen_enable" value="false" /> +// Retrieval info: <generic name="gen_enable" value="true" /> // Retrieval info: <generic name="divide_type" value="0" /> // Retrieval info: <generic name="select_signal_enable" value="false" /> // Retrieval info: <generic name="scale_by_pi" value="false" /> diff --git a/ip/ip_fp_mul/ip_fp_mul_0002.vhd b/ip/ip_fp_mul/ip_fp_mul_0002.vhd index 456a1b5..582906b 100644 --- a/ip/ip_fp_mul/ip_fp_mul_0002.vhd +++ b/ip/ip_fp_mul/ip_fp_mul_0002.vhd @@ -16,7 +16,7 @@ -- --------------------------------------------------------------------------- -- VHDL created from ip_fp_mul_0002 --- VHDL created on Fri Oct 20 22:55:53 2023 +-- VHDL created on Sat Oct 21 14:27:40 2023 library IEEE; @@ -35,9 +35,10 @@ USE lpm.lpm_components.all; entity ip_fp_mul_0002 is port ( - a : in std_logic_vector(31 downto 0); -- float32_m23 - b : in std_logic_vector(31 downto 0); -- float32_m23 - q : out std_logic_vector(31 downto 0); -- float32_m23 + a : in std_logic_vector(15 downto 0); -- float16_m10 + b : in std_logic_vector(15 downto 0); -- float16_m10 + en : in std_logic_vector(0 downto 0); -- ufix1 + q : out std_logic_vector(15 downto 0); -- float16_m10 clk : in std_logic; areset : in std_logic ); @@ -50,83 +51,77 @@ architecture normal of ip_fp_mul_0002 is signal GND_q : STD_LOGIC_VECTOR (0 downto 0); signal VCC_q : STD_LOGIC_VECTOR (0 downto 0); - signal expX_uid6_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0); - signal expY_uid7_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0); + signal expX_uid6_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0); + signal expY_uid7_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0); signal signX_uid8_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0); signal signY_uid9_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0); - signal cstAllOWE_uid10_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0); - signal cstZeroWF_uid11_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0); - signal cstAllZWE_uid12_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0); - signal frac_x_uid14_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0); + signal cstAllOWE_uid10_fpMulTest_q : STD_LOGIC_VECTOR (4 downto 0); + signal cstZeroWF_uid11_fpMulTest_q : STD_LOGIC_VECTOR (9 downto 0); + signal cstAllZWE_uid12_fpMulTest_q : STD_LOGIC_VECTOR (4 downto 0); + signal frac_x_uid14_fpMulTest_b : STD_LOGIC_VECTOR (9 downto 0); signal excZ_x_uid15_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excZ_x_uid15_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal expXIsMax_uid16_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal expXIsMax_uid16_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsZero_uid17_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsZero_uid17_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal fracXIsNotZero_uid18_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsNotZero_uid18_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal excI_x_uid19_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excI_x_uid19_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excN_x_uid20_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal invExpXIsMax_uid21_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal InvExpXIsZero_uid22_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal excR_x_uid23_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excR_x_uid23_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal frac_y_uid28_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0); + signal frac_y_uid28_fpMulTest_b : STD_LOGIC_VECTOR (9 downto 0); signal excZ_y_uid29_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excZ_y_uid29_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal expXIsMax_uid30_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal expXIsMax_uid30_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsZero_uid31_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsZero_uid31_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal fracXIsNotZero_uid32_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal fracXIsNotZero_uid32_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal excI_y_uid33_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excI_y_uid33_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excN_y_uid34_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal invExpXIsMax_uid35_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal InvExpXIsZero_uid36_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal excR_y_uid37_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excR_y_uid37_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal ofracX_uid40_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0); - signal ofracY_uid43_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0); - signal expSum_uid44_fpMulTest_a : STD_LOGIC_VECTOR (8 downto 0); - signal expSum_uid44_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0); - signal expSum_uid44_fpMulTest_o : STD_LOGIC_VECTOR (8 downto 0); - signal expSum_uid44_fpMulTest_q : STD_LOGIC_VECTOR (8 downto 0); - signal biasInc_uid45_fpMulTest_q : STD_LOGIC_VECTOR (9 downto 0); - signal expSumMBias_uid46_fpMulTest_a : STD_LOGIC_VECTOR (11 downto 0); - signal expSumMBias_uid46_fpMulTest_b : STD_LOGIC_VECTOR (11 downto 0); - signal expSumMBias_uid46_fpMulTest_o : STD_LOGIC_VECTOR (11 downto 0); - signal expSumMBias_uid46_fpMulTest_q : STD_LOGIC_VECTOR (10 downto 0); + signal ofracX_uid40_fpMulTest_q : STD_LOGIC_VECTOR (10 downto 0); + signal ofracY_uid43_fpMulTest_q : STD_LOGIC_VECTOR (10 downto 0); + signal expSum_uid44_fpMulTest_a : STD_LOGIC_VECTOR (5 downto 0); + signal expSum_uid44_fpMulTest_b : STD_LOGIC_VECTOR (5 downto 0); + signal expSum_uid44_fpMulTest_o : STD_LOGIC_VECTOR (5 downto 0); + signal expSum_uid44_fpMulTest_q : STD_LOGIC_VECTOR (5 downto 0); + signal biasInc_uid45_fpMulTest_q : STD_LOGIC_VECTOR (6 downto 0); + signal expSumMBias_uid46_fpMulTest_a : STD_LOGIC_VECTOR (8 downto 0); + signal expSumMBias_uid46_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0); + signal expSumMBias_uid46_fpMulTest_o : STD_LOGIC_VECTOR (8 downto 0); + signal expSumMBias_uid46_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0); signal signR_uid48_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal signR_uid48_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal normalizeBit_uid49_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0); - signal fracRPostNormHigh_uid51_fpMulTest_in : STD_LOGIC_VECTOR (24 downto 0); - signal fracRPostNormHigh_uid51_fpMulTest_b : STD_LOGIC_VECTOR (23 downto 0); - signal fracRPostNormLow_uid52_fpMulTest_in : STD_LOGIC_VECTOR (23 downto 0); - signal fracRPostNormLow_uid52_fpMulTest_b : STD_LOGIC_VECTOR (23 downto 0); + signal fracRPostNormHigh_uid51_fpMulTest_in : STD_LOGIC_VECTOR (11 downto 0); + signal fracRPostNormHigh_uid51_fpMulTest_b : STD_LOGIC_VECTOR (10 downto 0); + signal fracRPostNormLow_uid52_fpMulTest_in : STD_LOGIC_VECTOR (10 downto 0); + signal fracRPostNormLow_uid52_fpMulTest_b : STD_LOGIC_VECTOR (10 downto 0); signal fracRPostNorm_uid53_fpMulTest_s : STD_LOGIC_VECTOR (0 downto 0); - signal fracRPostNorm_uid53_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0); - signal expFracPreRound_uid55_fpMulTest_q : STD_LOGIC_VECTOR (34 downto 0); - signal roundBitAndNormalizationOp_uid57_fpMulTest_q : STD_LOGIC_VECTOR (25 downto 0); - signal expFracRPostRounding_uid58_fpMulTest_a : STD_LOGIC_VECTOR (36 downto 0); - signal expFracRPostRounding_uid58_fpMulTest_b : STD_LOGIC_VECTOR (36 downto 0); - signal expFracRPostRounding_uid58_fpMulTest_o : STD_LOGIC_VECTOR (36 downto 0); - signal expFracRPostRounding_uid58_fpMulTest_q : STD_LOGIC_VECTOR (35 downto 0); - signal fracRPreExc_uid59_fpMulTest_in : STD_LOGIC_VECTOR (23 downto 0); - signal fracRPreExc_uid59_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0); - signal expRPreExcExt_uid60_fpMulTest_b : STD_LOGIC_VECTOR (11 downto 0); - signal expRPreExc_uid61_fpMulTest_in : STD_LOGIC_VECTOR (7 downto 0); - signal expRPreExc_uid61_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0); - signal expUdf_uid62_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0); - signal expUdf_uid62_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0); - signal expUdf_uid62_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0); + signal fracRPostNorm_uid53_fpMulTest_q : STD_LOGIC_VECTOR (10 downto 0); + signal expFracPreRound_uid55_fpMulTest_q : STD_LOGIC_VECTOR (18 downto 0); + signal roundBitAndNormalizationOp_uid57_fpMulTest_q : STD_LOGIC_VECTOR (12 downto 0); + signal expFracRPostRounding_uid58_fpMulTest_a : STD_LOGIC_VECTOR (20 downto 0); + signal expFracRPostRounding_uid58_fpMulTest_b : STD_LOGIC_VECTOR (20 downto 0); + signal expFracRPostRounding_uid58_fpMulTest_o : STD_LOGIC_VECTOR (20 downto 0); + signal expFracRPostRounding_uid58_fpMulTest_q : STD_LOGIC_VECTOR (19 downto 0); + signal fracRPreExc_uid59_fpMulTest_in : STD_LOGIC_VECTOR (10 downto 0); + signal fracRPreExc_uid59_fpMulTest_b : STD_LOGIC_VECTOR (9 downto 0); + signal expRPreExcExt_uid60_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0); + signal expRPreExc_uid61_fpMulTest_in : STD_LOGIC_VECTOR (4 downto 0); + signal expRPreExc_uid61_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0); + signal expUdf_uid62_fpMulTest_a : STD_LOGIC_VECTOR (10 downto 0); + signal expUdf_uid62_fpMulTest_b : STD_LOGIC_VECTOR (10 downto 0); + signal expUdf_uid62_fpMulTest_o : STD_LOGIC_VECTOR (10 downto 0); signal expUdf_uid62_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0); - signal expOvf_uid64_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0); - signal expOvf_uid64_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0); - signal expOvf_uid64_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0); + signal expOvf_uid64_fpMulTest_a : STD_LOGIC_VECTOR (10 downto 0); + signal expOvf_uid64_fpMulTest_b : STD_LOGIC_VECTOR (10 downto 0); + signal expOvf_uid64_fpMulTest_o : STD_LOGIC_VECTOR (10 downto 0); signal expOvf_uid64_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0); signal excXZAndExcYZ_uid65_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excXZAndExcYR_uid66_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); @@ -141,230 +136,200 @@ architecture normal of ip_fp_mul_0002 is signal excYZAndExcXI_uid75_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal excXZAndExcYI_uid76_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal ZeroTimesInf_uid77_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal excRNaN_uid78_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal excRNaN_uid78_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); signal concExc_uid79_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0); signal excREnc_uid80_fpMulTest_q : STD_LOGIC_VECTOR (1 downto 0); - signal oneFracRPostExc2_uid81_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0); + signal oneFracRPostExc2_uid81_fpMulTest_q : STD_LOGIC_VECTOR (9 downto 0); signal fracRPostExc_uid84_fpMulTest_s : STD_LOGIC_VECTOR (1 downto 0); - signal fracRPostExc_uid84_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0); + signal fracRPostExc_uid84_fpMulTest_q : STD_LOGIC_VECTOR (9 downto 0); signal expRPostExc_uid89_fpMulTest_s : STD_LOGIC_VECTOR (1 downto 0); - signal expRPostExc_uid89_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0); + signal expRPostExc_uid89_fpMulTest_q : STD_LOGIC_VECTOR (4 downto 0); signal invExcRNaN_uid90_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal signRPostExc_uid91_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0); signal signRPostExc_uid91_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0); - signal R_uid92_fpMulTest_q : STD_LOGIC_VECTOR (31 downto 0); - signal osig_uid95_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (25 downto 0); + signal R_uid92_fpMulTest_q : STD_LOGIC_VECTOR (15 downto 0); + signal osig_uid95_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (12 downto 0); signal prodXY_uid94_prod_uid47_fpMulTest_cma_reset : std_logic; - type prodXY_uid94_prod_uid47_fpMulTest_cma_a0type is array(NATURAL range <>) of UNSIGNED(23 downto 0); + type prodXY_uid94_prod_uid47_fpMulTest_cma_a0type is array(NATURAL range <>) of UNSIGNED(10 downto 0); signal prodXY_uid94_prod_uid47_fpMulTest_cma_a0 : prodXY_uid94_prod_uid47_fpMulTest_cma_a0type(0 to 0); attribute preserve : boolean; attribute preserve of prodXY_uid94_prod_uid47_fpMulTest_cma_a0 : signal is true; signal prodXY_uid94_prod_uid47_fpMulTest_cma_c0 : prodXY_uid94_prod_uid47_fpMulTest_cma_a0type(0 to 0); attribute preserve of prodXY_uid94_prod_uid47_fpMulTest_cma_c0 : signal is true; - type prodXY_uid94_prod_uid47_fpMulTest_cma_ptype is array(NATURAL range <>) of UNSIGNED(47 downto 0); + type prodXY_uid94_prod_uid47_fpMulTest_cma_ptype is array(NATURAL range <>) of UNSIGNED(21 downto 0); signal prodXY_uid94_prod_uid47_fpMulTest_cma_p : prodXY_uid94_prod_uid47_fpMulTest_cma_ptype(0 to 0); signal prodXY_uid94_prod_uid47_fpMulTest_cma_u : prodXY_uid94_prod_uid47_fpMulTest_cma_ptype(0 to 0); signal prodXY_uid94_prod_uid47_fpMulTest_cma_w : prodXY_uid94_prod_uid47_fpMulTest_cma_ptype(0 to 0); signal prodXY_uid94_prod_uid47_fpMulTest_cma_x : prodXY_uid94_prod_uid47_fpMulTest_cma_ptype(0 to 0); signal prodXY_uid94_prod_uid47_fpMulTest_cma_y : prodXY_uid94_prod_uid47_fpMulTest_cma_ptype(0 to 0); signal prodXY_uid94_prod_uid47_fpMulTest_cma_s : prodXY_uid94_prod_uid47_fpMulTest_cma_ptype(0 to 0); - signal prodXY_uid94_prod_uid47_fpMulTest_cma_qq : STD_LOGIC_VECTOR (47 downto 0); - signal prodXY_uid94_prod_uid47_fpMulTest_cma_q : STD_LOGIC_VECTOR (47 downto 0); + signal prodXY_uid94_prod_uid47_fpMulTest_cma_qq : STD_LOGIC_VECTOR (21 downto 0); + signal prodXY_uid94_prod_uid47_fpMulTest_cma_q : STD_LOGIC_VECTOR (21 downto 0); signal prodXY_uid94_prod_uid47_fpMulTest_cma_ena0 : std_logic; signal prodXY_uid94_prod_uid47_fpMulTest_cma_ena1 : std_logic; - signal redist0_expRPreExc_uid61_fpMulTest_b_2_q : STD_LOGIC_VECTOR (7 downto 0); - signal redist1_expRPreExcExt_uid60_fpMulTest_b_1_q : STD_LOGIC_VECTOR (11 downto 0); - signal redist2_fracRPreExc_uid59_fpMulTest_b_3_q : STD_LOGIC_VECTOR (22 downto 0); - signal redist3_normalizeBit_uid49_fpMulTest_b_1_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist4_signR_uid48_fpMulTest_q_5_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist5_expSum_uid44_fpMulTest_q_2_q : STD_LOGIC_VECTOR (8 downto 0); - signal redist6_excI_y_uid33_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist7_fracXIsZero_uid31_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist8_expXIsMax_uid30_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist9_expXIsMax_uid30_fpMulTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist10_excZ_y_uid29_fpMulTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist11_excZ_y_uid29_fpMulTest_q_5_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist12_excI_x_uid19_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist13_fracXIsZero_uid17_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist14_expXIsMax_uid16_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist15_expXIsMax_uid16_fpMulTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist16_excZ_x_uid15_fpMulTest_q_4_q : STD_LOGIC_VECTOR (0 downto 0); - signal redist17_excZ_x_uid15_fpMulTest_q_5_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist0_expRPreExcExt_uid60_fpMulTest_b_1_q : STD_LOGIC_VECTOR (8 downto 0); + signal redist1_fracRPreExc_uid59_fpMulTest_b_1_q : STD_LOGIC_VECTOR (9 downto 0); + signal redist2_signR_uid48_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist3_fracXIsZero_uid31_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist4_expXIsMax_uid30_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist5_excZ_y_uid29_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist6_fracXIsZero_uid17_fpMulTest_q_3_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist7_expXIsMax_uid16_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist8_excZ_x_uid15_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0); + signal redist9_expY_uid7_fpMulTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); + signal redist10_expX_uid6_fpMulTest_b_1_q : STD_LOGIC_VECTOR (4 downto 0); begin -- frac_x_uid14_fpMulTest(BITSELECT,13)@0 - frac_x_uid14_fpMulTest_b <= a(22 downto 0); + frac_x_uid14_fpMulTest_b <= a(9 downto 0); -- cstZeroWF_uid11_fpMulTest(CONSTANT,10) - cstZeroWF_uid11_fpMulTest_q <= "00000000000000000000000"; + cstZeroWF_uid11_fpMulTest_q <= "0000000000"; -- fracXIsZero_uid17_fpMulTest(LOGICAL,16)@0 + 1 fracXIsZero_uid17_fpMulTest_qi <= "1" WHEN cstZeroWF_uid11_fpMulTest_q = frac_x_uid14_fpMulTest_b ELSE "0"; fracXIsZero_uid17_fpMulTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_qi, xout => fracXIsZero_uid17_fpMulTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_qi, xout => fracXIsZero_uid17_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist13_fracXIsZero_uid17_fpMulTest_q_3(DELAY,110) - redist13_fracXIsZero_uid17_fpMulTest_q_3 : dspba_delay + -- redist6_fracXIsZero_uid17_fpMulTest_q_3(DELAY,103) + redist6_fracXIsZero_uid17_fpMulTest_q_3 : dspba_delay GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_q, xout => redist13_fracXIsZero_uid17_fpMulTest_q_3_q, clk => clk, aclr => areset ); + PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_q, xout => redist6_fracXIsZero_uid17_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); -- cstAllOWE_uid10_fpMulTest(CONSTANT,9) - cstAllOWE_uid10_fpMulTest_q <= "11111111"; + cstAllOWE_uid10_fpMulTest_q <= "11111"; -- expX_uid6_fpMulTest(BITSELECT,5)@0 - expX_uid6_fpMulTest_b <= a(30 downto 23); + expX_uid6_fpMulTest_b <= a(14 downto 10); - -- expXIsMax_uid16_fpMulTest(LOGICAL,15)@0 + 1 - expXIsMax_uid16_fpMulTest_qi <= "1" WHEN expX_uid6_fpMulTest_b = cstAllOWE_uid10_fpMulTest_q ELSE "0"; + -- redist10_expX_uid6_fpMulTest_b_1(DELAY,107) + redist10_expX_uid6_fpMulTest_b_1 : dspba_delay + GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => expX_uid6_fpMulTest_b, xout => redist10_expX_uid6_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + + -- expXIsMax_uid16_fpMulTest(LOGICAL,15)@1 + 1 + expXIsMax_uid16_fpMulTest_qi <= "1" WHEN redist10_expX_uid6_fpMulTest_b_1_q = cstAllOWE_uid10_fpMulTest_q ELSE "0"; expXIsMax_uid16_fpMulTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expXIsMax_uid16_fpMulTest_qi, xout => expXIsMax_uid16_fpMulTest_q, clk => clk, aclr => areset ); - - -- redist14_expXIsMax_uid16_fpMulTest_q_3(DELAY,111) - redist14_expXIsMax_uid16_fpMulTest_q_3 : dspba_delay - GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => expXIsMax_uid16_fpMulTest_q, xout => redist14_expXIsMax_uid16_fpMulTest_q_3_q, clk => clk, aclr => areset ); + PORT MAP ( xin => expXIsMax_uid16_fpMulTest_qi, xout => expXIsMax_uid16_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excI_x_uid19_fpMulTest(LOGICAL,18)@3 + 1 - excI_x_uid19_fpMulTest_qi <= redist14_expXIsMax_uid16_fpMulTest_q_3_q and redist13_fracXIsZero_uid17_fpMulTest_q_3_q; - excI_x_uid19_fpMulTest_delay : dspba_delay + -- redist7_expXIsMax_uid16_fpMulTest_q_2(DELAY,104) + redist7_expXIsMax_uid16_fpMulTest_q_2 : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excI_x_uid19_fpMulTest_qi, xout => excI_x_uid19_fpMulTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => expXIsMax_uid16_fpMulTest_q, xout => redist7_expXIsMax_uid16_fpMulTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); + + -- excI_x_uid19_fpMulTest(LOGICAL,18)@3 + excI_x_uid19_fpMulTest_q <= redist7_expXIsMax_uid16_fpMulTest_q_2_q and redist6_fracXIsZero_uid17_fpMulTest_q_3_q; -- cstAllZWE_uid12_fpMulTest(CONSTANT,11) - cstAllZWE_uid12_fpMulTest_q <= "00000000"; + cstAllZWE_uid12_fpMulTest_q <= "00000"; -- expY_uid7_fpMulTest(BITSELECT,6)@0 - expY_uid7_fpMulTest_b <= b(30 downto 23); + expY_uid7_fpMulTest_b <= b(14 downto 10); - -- excZ_y_uid29_fpMulTest(LOGICAL,28)@0 + 1 - excZ_y_uid29_fpMulTest_qi <= "1" WHEN expY_uid7_fpMulTest_b = cstAllZWE_uid12_fpMulTest_q ELSE "0"; + -- redist9_expY_uid7_fpMulTest_b_1(DELAY,106) + redist9_expY_uid7_fpMulTest_b_1 : dspba_delay + GENERIC MAP ( width => 5, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => expY_uid7_fpMulTest_b, xout => redist9_expY_uid7_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); + + -- excZ_y_uid29_fpMulTest(LOGICAL,28)@1 + 1 + excZ_y_uid29_fpMulTest_qi <= "1" WHEN redist9_expY_uid7_fpMulTest_b_1_q = cstAllZWE_uid12_fpMulTest_q ELSE "0"; excZ_y_uid29_fpMulTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excZ_y_uid29_fpMulTest_qi, xout => excZ_y_uid29_fpMulTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => excZ_y_uid29_fpMulTest_qi, xout => excZ_y_uid29_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist10_excZ_y_uid29_fpMulTest_q_4(DELAY,107) - redist10_excZ_y_uid29_fpMulTest_q_4 : dspba_delay - GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) - PORT MAP ( xin => excZ_y_uid29_fpMulTest_q, xout => redist10_excZ_y_uid29_fpMulTest_q_4_q, clk => clk, aclr => areset ); + -- redist5_excZ_y_uid29_fpMulTest_q_2(DELAY,102) + redist5_excZ_y_uid29_fpMulTest_q_2 : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excZ_y_uid29_fpMulTest_q, xout => redist5_excZ_y_uid29_fpMulTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); - -- excYZAndExcXI_uid75_fpMulTest(LOGICAL,74)@4 - excYZAndExcXI_uid75_fpMulTest_q <= redist10_excZ_y_uid29_fpMulTest_q_4_q and excI_x_uid19_fpMulTest_q; + -- excYZAndExcXI_uid75_fpMulTest(LOGICAL,74)@3 + excYZAndExcXI_uid75_fpMulTest_q <= redist5_excZ_y_uid29_fpMulTest_q_2_q and excI_x_uid19_fpMulTest_q; -- frac_y_uid28_fpMulTest(BITSELECT,27)@0 - frac_y_uid28_fpMulTest_b <= b(22 downto 0); + frac_y_uid28_fpMulTest_b <= b(9 downto 0); -- fracXIsZero_uid31_fpMulTest(LOGICAL,30)@0 + 1 fracXIsZero_uid31_fpMulTest_qi <= "1" WHEN cstZeroWF_uid11_fpMulTest_q = frac_y_uid28_fpMulTest_b ELSE "0"; fracXIsZero_uid31_fpMulTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_qi, xout => fracXIsZero_uid31_fpMulTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_qi, xout => fracXIsZero_uid31_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist7_fracXIsZero_uid31_fpMulTest_q_3(DELAY,104) - redist7_fracXIsZero_uid31_fpMulTest_q_3 : dspba_delay + -- redist3_fracXIsZero_uid31_fpMulTest_q_3(DELAY,100) + redist3_fracXIsZero_uid31_fpMulTest_q_3 : dspba_delay GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_q, xout => redist7_fracXIsZero_uid31_fpMulTest_q_3_q, clk => clk, aclr => areset ); + PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_q, xout => redist3_fracXIsZero_uid31_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); - -- expXIsMax_uid30_fpMulTest(LOGICAL,29)@0 + 1 - expXIsMax_uid30_fpMulTest_qi <= "1" WHEN expY_uid7_fpMulTest_b = cstAllOWE_uid10_fpMulTest_q ELSE "0"; + -- expXIsMax_uid30_fpMulTest(LOGICAL,29)@1 + 1 + expXIsMax_uid30_fpMulTest_qi <= "1" WHEN redist9_expY_uid7_fpMulTest_b_1_q = cstAllOWE_uid10_fpMulTest_q ELSE "0"; expXIsMax_uid30_fpMulTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expXIsMax_uid30_fpMulTest_qi, xout => expXIsMax_uid30_fpMulTest_q, clk => clk, aclr => areset ); - - -- redist8_expXIsMax_uid30_fpMulTest_q_3(DELAY,105) - redist8_expXIsMax_uid30_fpMulTest_q_3 : dspba_delay - GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => expXIsMax_uid30_fpMulTest_q, xout => redist8_expXIsMax_uid30_fpMulTest_q_3_q, clk => clk, aclr => areset ); + PORT MAP ( xin => expXIsMax_uid30_fpMulTest_qi, xout => expXIsMax_uid30_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- excI_y_uid33_fpMulTest(LOGICAL,32)@3 + 1 - excI_y_uid33_fpMulTest_qi <= redist8_expXIsMax_uid30_fpMulTest_q_3_q and redist7_fracXIsZero_uid31_fpMulTest_q_3_q; - excI_y_uid33_fpMulTest_delay : dspba_delay + -- redist4_expXIsMax_uid30_fpMulTest_q_2(DELAY,101) + redist4_expXIsMax_uid30_fpMulTest_q_2 : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excI_y_uid33_fpMulTest_qi, xout => excI_y_uid33_fpMulTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => expXIsMax_uid30_fpMulTest_q, xout => redist4_expXIsMax_uid30_fpMulTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); - -- excZ_x_uid15_fpMulTest(LOGICAL,14)@0 + 1 - excZ_x_uid15_fpMulTest_qi <= "1" WHEN expX_uid6_fpMulTest_b = cstAllZWE_uid12_fpMulTest_q ELSE "0"; + -- excI_y_uid33_fpMulTest(LOGICAL,32)@3 + excI_y_uid33_fpMulTest_q <= redist4_expXIsMax_uid30_fpMulTest_q_2_q and redist3_fracXIsZero_uid31_fpMulTest_q_3_q; + + -- excZ_x_uid15_fpMulTest(LOGICAL,14)@1 + 1 + excZ_x_uid15_fpMulTest_qi <= "1" WHEN redist10_expX_uid6_fpMulTest_b_1_q = cstAllZWE_uid12_fpMulTest_q ELSE "0"; excZ_x_uid15_fpMulTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excZ_x_uid15_fpMulTest_qi, xout => excZ_x_uid15_fpMulTest_q, clk => clk, aclr => areset ); + PORT MAP ( xin => excZ_x_uid15_fpMulTest_qi, xout => excZ_x_uid15_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- redist16_excZ_x_uid15_fpMulTest_q_4(DELAY,113) - redist16_excZ_x_uid15_fpMulTest_q_4 : dspba_delay - GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) - PORT MAP ( xin => excZ_x_uid15_fpMulTest_q, xout => redist16_excZ_x_uid15_fpMulTest_q_4_q, clk => clk, aclr => areset ); + -- redist8_excZ_x_uid15_fpMulTest_q_2(DELAY,105) + redist8_excZ_x_uid15_fpMulTest_q_2 : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => excZ_x_uid15_fpMulTest_q, xout => redist8_excZ_x_uid15_fpMulTest_q_2_q, ena => en(0), clk => clk, aclr => areset ); - -- excXZAndExcYI_uid76_fpMulTest(LOGICAL,75)@4 - excXZAndExcYI_uid76_fpMulTest_q <= redist16_excZ_x_uid15_fpMulTest_q_4_q and excI_y_uid33_fpMulTest_q; + -- excXZAndExcYI_uid76_fpMulTest(LOGICAL,75)@3 + excXZAndExcYI_uid76_fpMulTest_q <= redist8_excZ_x_uid15_fpMulTest_q_2_q and excI_y_uid33_fpMulTest_q; - -- ZeroTimesInf_uid77_fpMulTest(LOGICAL,76)@4 + -- ZeroTimesInf_uid77_fpMulTest(LOGICAL,76)@3 ZeroTimesInf_uid77_fpMulTest_q <= excXZAndExcYI_uid76_fpMulTest_q or excYZAndExcXI_uid75_fpMulTest_q; - -- fracXIsNotZero_uid32_fpMulTest(LOGICAL,31)@3 + 1 - fracXIsNotZero_uid32_fpMulTest_qi <= not (redist7_fracXIsZero_uid31_fpMulTest_q_3_q); - fracXIsNotZero_uid32_fpMulTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsNotZero_uid32_fpMulTest_qi, xout => fracXIsNotZero_uid32_fpMulTest_q, clk => clk, aclr => areset ); - - -- redist9_expXIsMax_uid30_fpMulTest_q_4(DELAY,106) - redist9_expXIsMax_uid30_fpMulTest_q_4 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => redist8_expXIsMax_uid30_fpMulTest_q_3_q, xout => redist9_expXIsMax_uid30_fpMulTest_q_4_q, clk => clk, aclr => areset ); - - -- excN_y_uid34_fpMulTest(LOGICAL,33)@4 - excN_y_uid34_fpMulTest_q <= redist9_expXIsMax_uid30_fpMulTest_q_4_q and fracXIsNotZero_uid32_fpMulTest_q; + -- fracXIsNotZero_uid32_fpMulTest(LOGICAL,31)@3 + fracXIsNotZero_uid32_fpMulTest_q <= not (redist3_fracXIsZero_uid31_fpMulTest_q_3_q); - -- fracXIsNotZero_uid18_fpMulTest(LOGICAL,17)@3 + 1 - fracXIsNotZero_uid18_fpMulTest_qi <= not (redist13_fracXIsZero_uid17_fpMulTest_q_3_q); - fracXIsNotZero_uid18_fpMulTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracXIsNotZero_uid18_fpMulTest_qi, xout => fracXIsNotZero_uid18_fpMulTest_q, clk => clk, aclr => areset ); + -- excN_y_uid34_fpMulTest(LOGICAL,33)@3 + excN_y_uid34_fpMulTest_q <= redist4_expXIsMax_uid30_fpMulTest_q_2_q and fracXIsNotZero_uid32_fpMulTest_q; - -- redist15_expXIsMax_uid16_fpMulTest_q_4(DELAY,112) - redist15_expXIsMax_uid16_fpMulTest_q_4 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => redist14_expXIsMax_uid16_fpMulTest_q_3_q, xout => redist15_expXIsMax_uid16_fpMulTest_q_4_q, clk => clk, aclr => areset ); + -- fracXIsNotZero_uid18_fpMulTest(LOGICAL,17)@3 + fracXIsNotZero_uid18_fpMulTest_q <= not (redist6_fracXIsZero_uid17_fpMulTest_q_3_q); - -- excN_x_uid20_fpMulTest(LOGICAL,19)@4 - excN_x_uid20_fpMulTest_q <= redist15_expXIsMax_uid16_fpMulTest_q_4_q and fracXIsNotZero_uid18_fpMulTest_q; + -- excN_x_uid20_fpMulTest(LOGICAL,19)@3 + excN_x_uid20_fpMulTest_q <= redist7_expXIsMax_uid16_fpMulTest_q_2_q and fracXIsNotZero_uid18_fpMulTest_q; - -- excRNaN_uid78_fpMulTest(LOGICAL,77)@4 + 1 - excRNaN_uid78_fpMulTest_qi <= excN_x_uid20_fpMulTest_q or excN_y_uid34_fpMulTest_q or ZeroTimesInf_uid77_fpMulTest_q; - excRNaN_uid78_fpMulTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excRNaN_uid78_fpMulTest_qi, xout => excRNaN_uid78_fpMulTest_q, clk => clk, aclr => areset ); + -- excRNaN_uid78_fpMulTest(LOGICAL,77)@3 + excRNaN_uid78_fpMulTest_q <= excN_x_uid20_fpMulTest_q or excN_y_uid34_fpMulTest_q or ZeroTimesInf_uid77_fpMulTest_q; - -- invExcRNaN_uid90_fpMulTest(LOGICAL,89)@5 + -- invExcRNaN_uid90_fpMulTest(LOGICAL,89)@3 invExcRNaN_uid90_fpMulTest_q <= not (excRNaN_uid78_fpMulTest_q); -- signY_uid9_fpMulTest(BITSELECT,8)@0 - signY_uid9_fpMulTest_b <= STD_LOGIC_VECTOR(b(31 downto 31)); + signY_uid9_fpMulTest_b <= STD_LOGIC_VECTOR(b(15 downto 15)); -- signX_uid8_fpMulTest(BITSELECT,7)@0 - signX_uid8_fpMulTest_b <= STD_LOGIC_VECTOR(a(31 downto 31)); + signX_uid8_fpMulTest_b <= STD_LOGIC_VECTOR(a(15 downto 15)); -- signR_uid48_fpMulTest(LOGICAL,47)@0 + 1 signR_uid48_fpMulTest_qi <= signX_uid8_fpMulTest_b xor signY_uid9_fpMulTest_b; signR_uid48_fpMulTest_delay : dspba_delay GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => signR_uid48_fpMulTest_qi, xout => signR_uid48_fpMulTest_q, clk => clk, aclr => areset ); - - -- redist4_signR_uid48_fpMulTest_q_5(DELAY,101) - redist4_signR_uid48_fpMulTest_q_5 : dspba_delay - GENERIC MAP ( width => 1, depth => 4, reset_kind => "ASYNC" ) - PORT MAP ( xin => signR_uid48_fpMulTest_q, xout => redist4_signR_uid48_fpMulTest_q_5_q, clk => clk, aclr => areset ); + PORT MAP ( xin => signR_uid48_fpMulTest_qi, xout => signR_uid48_fpMulTest_q, ena => en(0), clk => clk, aclr => areset ); - -- VCC(CONSTANT,1) - VCC_q <= "1"; + -- redist2_signR_uid48_fpMulTest_q_3(DELAY,99) + redist2_signR_uid48_fpMulTest_q_3 : dspba_delay + GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) + PORT MAP ( xin => signR_uid48_fpMulTest_q, xout => redist2_signR_uid48_fpMulTest_q_3_q, ena => en(0), clk => clk, aclr => areset ); - -- signRPostExc_uid91_fpMulTest(LOGICAL,90)@5 + 1 - signRPostExc_uid91_fpMulTest_qi <= redist4_signR_uid48_fpMulTest_q_5_q and invExcRNaN_uid90_fpMulTest_q; - signRPostExc_uid91_fpMulTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => signRPostExc_uid91_fpMulTest_qi, xout => signRPostExc_uid91_fpMulTest_q, clk => clk, aclr => areset ); + -- signRPostExc_uid91_fpMulTest(LOGICAL,90)@3 + signRPostExc_uid91_fpMulTest_q <= redist2_signR_uid48_fpMulTest_q_3_q and invExcRNaN_uid90_fpMulTest_q; -- GND(CONSTANT,0) GND_q <= "0"; @@ -377,10 +342,10 @@ begin -- prodXY_uid94_prod_uid47_fpMulTest_cma(CHAINMULTADD,96)@0 + 2 prodXY_uid94_prod_uid47_fpMulTest_cma_reset <= areset; - prodXY_uid94_prod_uid47_fpMulTest_cma_ena0 <= '1'; + prodXY_uid94_prod_uid47_fpMulTest_cma_ena0 <= en(0); prodXY_uid94_prod_uid47_fpMulTest_cma_ena1 <= prodXY_uid94_prod_uid47_fpMulTest_cma_ena0; prodXY_uid94_prod_uid47_fpMulTest_cma_p(0) <= prodXY_uid94_prod_uid47_fpMulTest_cma_a0(0) * prodXY_uid94_prod_uid47_fpMulTest_cma_c0(0); - prodXY_uid94_prod_uid47_fpMulTest_cma_u(0) <= RESIZE(prodXY_uid94_prod_uid47_fpMulTest_cma_p(0),48); + prodXY_uid94_prod_uid47_fpMulTest_cma_u(0) <= RESIZE(prodXY_uid94_prod_uid47_fpMulTest_cma_p(0),22); prodXY_uid94_prod_uid47_fpMulTest_cma_w(0) <= prodXY_uid94_prod_uid47_fpMulTest_cma_u(0); prodXY_uid94_prod_uid47_fpMulTest_cma_x(0) <= prodXY_uid94_prod_uid47_fpMulTest_cma_w(0); prodXY_uid94_prod_uid47_fpMulTest_cma_y(0) <= prodXY_uid94_prod_uid47_fpMulTest_cma_x(0); @@ -391,8 +356,8 @@ begin prodXY_uid94_prod_uid47_fpMulTest_cma_c0 <= (others => (others => '0')); ELSIF (clk'EVENT AND clk = '1') THEN IF (prodXY_uid94_prod_uid47_fpMulTest_cma_ena0 = '1') THEN - prodXY_uid94_prod_uid47_fpMulTest_cma_a0(0) <= RESIZE(UNSIGNED(ofracX_uid40_fpMulTest_q),24); - prodXY_uid94_prod_uid47_fpMulTest_cma_c0(0) <= RESIZE(UNSIGNED(ofracY_uid43_fpMulTest_q),24); + prodXY_uid94_prod_uid47_fpMulTest_cma_a0(0) <= RESIZE(UNSIGNED(ofracX_uid40_fpMulTest_q),11); + prodXY_uid94_prod_uid47_fpMulTest_cma_c0(0) <= RESIZE(UNSIGNED(ofracY_uid43_fpMulTest_q),11); END IF; END IF; END PROCESS; @@ -407,238 +372,175 @@ begin END IF; END PROCESS; prodXY_uid94_prod_uid47_fpMulTest_cma_delay : dspba_delay - GENERIC MAP ( width => 48, depth => 0, reset_kind => "ASYNC" ) - PORT MAP ( xin => STD_LOGIC_VECTOR(prodXY_uid94_prod_uid47_fpMulTest_cma_s(0)(47 downto 0)), xout => prodXY_uid94_prod_uid47_fpMulTest_cma_qq, clk => clk, aclr => areset ); - prodXY_uid94_prod_uid47_fpMulTest_cma_q <= STD_LOGIC_VECTOR(prodXY_uid94_prod_uid47_fpMulTest_cma_qq(47 downto 0)); + GENERIC MAP ( width => 22, depth => 0, reset_kind => "ASYNC" ) + PORT MAP ( xin => STD_LOGIC_VECTOR(prodXY_uid94_prod_uid47_fpMulTest_cma_s(0)(21 downto 0)), xout => prodXY_uid94_prod_uid47_fpMulTest_cma_qq, ena => en(0), clk => clk, aclr => areset ); + prodXY_uid94_prod_uid47_fpMulTest_cma_q <= STD_LOGIC_VECTOR(prodXY_uid94_prod_uid47_fpMulTest_cma_qq(21 downto 0)); -- osig_uid95_prod_uid47_fpMulTest(BITSELECT,94)@2 - osig_uid95_prod_uid47_fpMulTest_b <= prodXY_uid94_prod_uid47_fpMulTest_cma_q(47 downto 22); + osig_uid95_prod_uid47_fpMulTest_b <= prodXY_uid94_prod_uid47_fpMulTest_cma_q(21 downto 9); -- normalizeBit_uid49_fpMulTest(BITSELECT,48)@2 - normalizeBit_uid49_fpMulTest_b <= STD_LOGIC_VECTOR(osig_uid95_prod_uid47_fpMulTest_b(25 downto 25)); + normalizeBit_uid49_fpMulTest_b <= STD_LOGIC_VECTOR(osig_uid95_prod_uid47_fpMulTest_b(12 downto 12)); - -- redist3_normalizeBit_uid49_fpMulTest_b_1(DELAY,100) - redist3_normalizeBit_uid49_fpMulTest_b_1 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => normalizeBit_uid49_fpMulTest_b, xout => redist3_normalizeBit_uid49_fpMulTest_b_1_q, clk => clk, aclr => areset ); + -- VCC(CONSTANT,1) + VCC_q <= "1"; - -- roundBitAndNormalizationOp_uid57_fpMulTest(BITJOIN,56)@3 - roundBitAndNormalizationOp_uid57_fpMulTest_q <= GND_q & redist3_normalizeBit_uid49_fpMulTest_b_1_q & cstZeroWF_uid11_fpMulTest_q & VCC_q; + -- roundBitAndNormalizationOp_uid57_fpMulTest(BITJOIN,56)@2 + roundBitAndNormalizationOp_uid57_fpMulTest_q <= GND_q & normalizeBit_uid49_fpMulTest_b & cstZeroWF_uid11_fpMulTest_q & VCC_q; -- biasInc_uid45_fpMulTest(CONSTANT,44) - biasInc_uid45_fpMulTest_q <= "0001111111"; + biasInc_uid45_fpMulTest_q <= "0001111"; - -- expSum_uid44_fpMulTest(ADD,43)@0 + 1 - expSum_uid44_fpMulTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpMulTest_b); - expSum_uid44_fpMulTest_b <= STD_LOGIC_VECTOR("0" & expY_uid7_fpMulTest_b); + -- expSum_uid44_fpMulTest(ADD,43)@1 + 1 + expSum_uid44_fpMulTest_a <= STD_LOGIC_VECTOR("0" & redist10_expX_uid6_fpMulTest_b_1_q); + expSum_uid44_fpMulTest_b <= STD_LOGIC_VECTOR("0" & redist9_expY_uid7_fpMulTest_b_1_q); expSum_uid44_fpMulTest_clkproc: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSum_uid44_fpMulTest_o <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN - expSum_uid44_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid44_fpMulTest_a) + UNSIGNED(expSum_uid44_fpMulTest_b)); + IF (en = "1") THEN + expSum_uid44_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid44_fpMulTest_a) + UNSIGNED(expSum_uid44_fpMulTest_b)); + END IF; END IF; END PROCESS; - expSum_uid44_fpMulTest_q <= expSum_uid44_fpMulTest_o(8 downto 0); + expSum_uid44_fpMulTest_q <= expSum_uid44_fpMulTest_o(5 downto 0); - -- redist5_expSum_uid44_fpMulTest_q_2(DELAY,102) - redist5_expSum_uid44_fpMulTest_q_2 : dspba_delay - GENERIC MAP ( width => 9, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expSum_uid44_fpMulTest_q, xout => redist5_expSum_uid44_fpMulTest_q_2_q, clk => clk, aclr => areset ); - - -- expSumMBias_uid46_fpMulTest(SUB,45)@2 + 1 - expSumMBias_uid46_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("000" & redist5_expSum_uid44_fpMulTest_q_2_q)); - expSumMBias_uid46_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid45_fpMulTest_q(9)) & biasInc_uid45_fpMulTest_q)); - expSumMBias_uid46_fpMulTest_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - expSumMBias_uid46_fpMulTest_o <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - expSumMBias_uid46_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid46_fpMulTest_a) - SIGNED(expSumMBias_uid46_fpMulTest_b)); - END IF; - END PROCESS; - expSumMBias_uid46_fpMulTest_q <= expSumMBias_uid46_fpMulTest_o(10 downto 0); + -- expSumMBias_uid46_fpMulTest(SUB,45)@2 + expSumMBias_uid46_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("000" & expSum_uid44_fpMulTest_q)); + expSumMBias_uid46_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((8 downto 7 => biasInc_uid45_fpMulTest_q(6)) & biasInc_uid45_fpMulTest_q)); + expSumMBias_uid46_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid46_fpMulTest_a) - SIGNED(expSumMBias_uid46_fpMulTest_b)); + expSumMBias_uid46_fpMulTest_q <= expSumMBias_uid46_fpMulTest_o(7 downto 0); -- fracRPostNormHigh_uid51_fpMulTest(BITSELECT,50)@2 - fracRPostNormHigh_uid51_fpMulTest_in <= osig_uid95_prod_uid47_fpMulTest_b(24 downto 0); - fracRPostNormHigh_uid51_fpMulTest_b <= fracRPostNormHigh_uid51_fpMulTest_in(24 downto 1); + fracRPostNormHigh_uid51_fpMulTest_in <= osig_uid95_prod_uid47_fpMulTest_b(11 downto 0); + fracRPostNormHigh_uid51_fpMulTest_b <= fracRPostNormHigh_uid51_fpMulTest_in(11 downto 1); -- fracRPostNormLow_uid52_fpMulTest(BITSELECT,51)@2 - fracRPostNormLow_uid52_fpMulTest_in <= osig_uid95_prod_uid47_fpMulTest_b(23 downto 0); - fracRPostNormLow_uid52_fpMulTest_b <= fracRPostNormLow_uid52_fpMulTest_in(23 downto 0); + fracRPostNormLow_uid52_fpMulTest_in <= osig_uid95_prod_uid47_fpMulTest_b(10 downto 0); + fracRPostNormLow_uid52_fpMulTest_b <= fracRPostNormLow_uid52_fpMulTest_in(10 downto 0); - -- fracRPostNorm_uid53_fpMulTest(MUX,52)@2 + 1 + -- fracRPostNorm_uid53_fpMulTest(MUX,52)@2 fracRPostNorm_uid53_fpMulTest_s <= normalizeBit_uid49_fpMulTest_b; - fracRPostNorm_uid53_fpMulTest_clkproc: PROCESS (clk, areset) + fracRPostNorm_uid53_fpMulTest_combproc: PROCESS (fracRPostNorm_uid53_fpMulTest_s, en, fracRPostNormLow_uid52_fpMulTest_b, fracRPostNormHigh_uid51_fpMulTest_b) BEGIN - IF (areset = '1') THEN - fracRPostNorm_uid53_fpMulTest_q <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - CASE (fracRPostNorm_uid53_fpMulTest_s) IS - WHEN "0" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormLow_uid52_fpMulTest_b; - WHEN "1" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormHigh_uid51_fpMulTest_b; - WHEN OTHERS => fracRPostNorm_uid53_fpMulTest_q <= (others => '0'); - END CASE; - END IF; + CASE (fracRPostNorm_uid53_fpMulTest_s) IS + WHEN "0" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormLow_uid52_fpMulTest_b; + WHEN "1" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormHigh_uid51_fpMulTest_b; + WHEN OTHERS => fracRPostNorm_uid53_fpMulTest_q <= (others => '0'); + END CASE; END PROCESS; - -- expFracPreRound_uid55_fpMulTest(BITJOIN,54)@3 + -- expFracPreRound_uid55_fpMulTest(BITJOIN,54)@2 expFracPreRound_uid55_fpMulTest_q <= expSumMBias_uid46_fpMulTest_q & fracRPostNorm_uid53_fpMulTest_q; - -- expFracRPostRounding_uid58_fpMulTest(ADD,57)@3 - expFracRPostRounding_uid58_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((36 downto 35 => expFracPreRound_uid55_fpMulTest_q(34)) & expFracPreRound_uid55_fpMulTest_q)); - expFracRPostRounding_uid58_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("00000000000" & roundBitAndNormalizationOp_uid57_fpMulTest_q)); + -- expFracRPostRounding_uid58_fpMulTest(ADD,57)@2 + expFracRPostRounding_uid58_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((20 downto 19 => expFracPreRound_uid55_fpMulTest_q(18)) & expFracPreRound_uid55_fpMulTest_q)); + expFracRPostRounding_uid58_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("00000000" & roundBitAndNormalizationOp_uid57_fpMulTest_q)); expFracRPostRounding_uid58_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid58_fpMulTest_a) + SIGNED(expFracRPostRounding_uid58_fpMulTest_b)); - expFracRPostRounding_uid58_fpMulTest_q <= expFracRPostRounding_uid58_fpMulTest_o(35 downto 0); - - -- expRPreExcExt_uid60_fpMulTest(BITSELECT,59)@3 - expRPreExcExt_uid60_fpMulTest_b <= STD_LOGIC_VECTOR(expFracRPostRounding_uid58_fpMulTest_q(35 downto 24)); + expFracRPostRounding_uid58_fpMulTest_q <= expFracRPostRounding_uid58_fpMulTest_o(19 downto 0); - -- redist1_expRPreExcExt_uid60_fpMulTest_b_1(DELAY,98) - redist1_expRPreExcExt_uid60_fpMulTest_b_1 : dspba_delay - GENERIC MAP ( width => 12, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => expRPreExcExt_uid60_fpMulTest_b, xout => redist1_expRPreExcExt_uid60_fpMulTest_b_1_q, clk => clk, aclr => areset ); + -- expRPreExcExt_uid60_fpMulTest(BITSELECT,59)@2 + expRPreExcExt_uid60_fpMulTest_b <= STD_LOGIC_VECTOR(expFracRPostRounding_uid58_fpMulTest_q(19 downto 11)); - -- expRPreExc_uid61_fpMulTest(BITSELECT,60)@4 - expRPreExc_uid61_fpMulTest_in <= redist1_expRPreExcExt_uid60_fpMulTest_b_1_q(7 downto 0); - expRPreExc_uid61_fpMulTest_b <= expRPreExc_uid61_fpMulTest_in(7 downto 0); + -- redist0_expRPreExcExt_uid60_fpMulTest_b_1(DELAY,97) + redist0_expRPreExcExt_uid60_fpMulTest_b_1 : dspba_delay + GENERIC MAP ( width => 9, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => expRPreExcExt_uid60_fpMulTest_b, xout => redist0_expRPreExcExt_uid60_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); - -- redist0_expRPreExc_uid61_fpMulTest_b_2(DELAY,97) - redist0_expRPreExc_uid61_fpMulTest_b_2 : dspba_delay - GENERIC MAP ( width => 8, depth => 2, reset_kind => "ASYNC" ) - PORT MAP ( xin => expRPreExc_uid61_fpMulTest_b, xout => redist0_expRPreExc_uid61_fpMulTest_b_2_q, clk => clk, aclr => areset ); + -- expRPreExc_uid61_fpMulTest(BITSELECT,60)@3 + expRPreExc_uid61_fpMulTest_in <= redist0_expRPreExcExt_uid60_fpMulTest_b_1_q(4 downto 0); + expRPreExc_uid61_fpMulTest_b <= expRPreExc_uid61_fpMulTest_in(4 downto 0); - -- expOvf_uid64_fpMulTest(COMPARE,63)@4 + 1 - expOvf_uid64_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 12 => redist1_expRPreExcExt_uid60_fpMulTest_b_1_q(11)) & redist1_expRPreExcExt_uid60_fpMulTest_b_1_q)); + -- expOvf_uid64_fpMulTest(COMPARE,63)@3 + expOvf_uid64_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist0_expRPreExcExt_uid60_fpMulTest_b_1_q(8)) & redist0_expRPreExcExt_uid60_fpMulTest_b_1_q)); expOvf_uid64_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("000000" & cstAllOWE_uid10_fpMulTest_q)); - expOvf_uid64_fpMulTest_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - expOvf_uid64_fpMulTest_o <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - expOvf_uid64_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid64_fpMulTest_a) - SIGNED(expOvf_uid64_fpMulTest_b)); - END IF; - END PROCESS; - expOvf_uid64_fpMulTest_n(0) <= not (expOvf_uid64_fpMulTest_o(13)); + expOvf_uid64_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid64_fpMulTest_a) - SIGNED(expOvf_uid64_fpMulTest_b)); + expOvf_uid64_fpMulTest_n(0) <= not (expOvf_uid64_fpMulTest_o(10)); - -- invExpXIsMax_uid35_fpMulTest(LOGICAL,34)@4 - invExpXIsMax_uid35_fpMulTest_q <= not (redist9_expXIsMax_uid30_fpMulTest_q_4_q); + -- invExpXIsMax_uid35_fpMulTest(LOGICAL,34)@3 + invExpXIsMax_uid35_fpMulTest_q <= not (redist4_expXIsMax_uid30_fpMulTest_q_2_q); - -- InvExpXIsZero_uid36_fpMulTest(LOGICAL,35)@4 - InvExpXIsZero_uid36_fpMulTest_q <= not (redist10_excZ_y_uid29_fpMulTest_q_4_q); + -- InvExpXIsZero_uid36_fpMulTest(LOGICAL,35)@3 + InvExpXIsZero_uid36_fpMulTest_q <= not (redist5_excZ_y_uid29_fpMulTest_q_2_q); - -- excR_y_uid37_fpMulTest(LOGICAL,36)@4 + 1 - excR_y_uid37_fpMulTest_qi <= InvExpXIsZero_uid36_fpMulTest_q and invExpXIsMax_uid35_fpMulTest_q; - excR_y_uid37_fpMulTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excR_y_uid37_fpMulTest_qi, xout => excR_y_uid37_fpMulTest_q, clk => clk, aclr => areset ); + -- excR_y_uid37_fpMulTest(LOGICAL,36)@3 + excR_y_uid37_fpMulTest_q <= InvExpXIsZero_uid36_fpMulTest_q and invExpXIsMax_uid35_fpMulTest_q; - -- invExpXIsMax_uid21_fpMulTest(LOGICAL,20)@4 - invExpXIsMax_uid21_fpMulTest_q <= not (redist15_expXIsMax_uid16_fpMulTest_q_4_q); + -- invExpXIsMax_uid21_fpMulTest(LOGICAL,20)@3 + invExpXIsMax_uid21_fpMulTest_q <= not (redist7_expXIsMax_uid16_fpMulTest_q_2_q); - -- InvExpXIsZero_uid22_fpMulTest(LOGICAL,21)@4 - InvExpXIsZero_uid22_fpMulTest_q <= not (redist16_excZ_x_uid15_fpMulTest_q_4_q); + -- InvExpXIsZero_uid22_fpMulTest(LOGICAL,21)@3 + InvExpXIsZero_uid22_fpMulTest_q <= not (redist8_excZ_x_uid15_fpMulTest_q_2_q); - -- excR_x_uid23_fpMulTest(LOGICAL,22)@4 + 1 - excR_x_uid23_fpMulTest_qi <= InvExpXIsZero_uid22_fpMulTest_q and invExpXIsMax_uid21_fpMulTest_q; - excR_x_uid23_fpMulTest_delay : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excR_x_uid23_fpMulTest_qi, xout => excR_x_uid23_fpMulTest_q, clk => clk, aclr => areset ); + -- excR_x_uid23_fpMulTest(LOGICAL,22)@3 + excR_x_uid23_fpMulTest_q <= InvExpXIsZero_uid22_fpMulTest_q and invExpXIsMax_uid21_fpMulTest_q; - -- ExcROvfAndInReg_uid73_fpMulTest(LOGICAL,72)@5 + -- ExcROvfAndInReg_uid73_fpMulTest(LOGICAL,72)@3 ExcROvfAndInReg_uid73_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expOvf_uid64_fpMulTest_n; - -- redist12_excI_x_uid19_fpMulTest_q_2(DELAY,109) - redist12_excI_x_uid19_fpMulTest_q_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excI_x_uid19_fpMulTest_q, xout => redist12_excI_x_uid19_fpMulTest_q_2_q, clk => clk, aclr => areset ); + -- excYRAndExcXI_uid72_fpMulTest(LOGICAL,71)@3 + excYRAndExcXI_uid72_fpMulTest_q <= excR_y_uid37_fpMulTest_q and excI_x_uid19_fpMulTest_q; - -- excYRAndExcXI_uid72_fpMulTest(LOGICAL,71)@5 - excYRAndExcXI_uid72_fpMulTest_q <= excR_y_uid37_fpMulTest_q and redist12_excI_x_uid19_fpMulTest_q_2_q; + -- excXRAndExcYI_uid71_fpMulTest(LOGICAL,70)@3 + excXRAndExcYI_uid71_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excI_y_uid33_fpMulTest_q; - -- redist6_excI_y_uid33_fpMulTest_q_2(DELAY,103) - redist6_excI_y_uid33_fpMulTest_q_2 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => excI_y_uid33_fpMulTest_q, xout => redist6_excI_y_uid33_fpMulTest_q_2_q, clk => clk, aclr => areset ); + -- excXIAndExcYI_uid70_fpMulTest(LOGICAL,69)@3 + excXIAndExcYI_uid70_fpMulTest_q <= excI_x_uid19_fpMulTest_q and excI_y_uid33_fpMulTest_q; - -- excXRAndExcYI_uid71_fpMulTest(LOGICAL,70)@5 - excXRAndExcYI_uid71_fpMulTest_q <= excR_x_uid23_fpMulTest_q and redist6_excI_y_uid33_fpMulTest_q_2_q; - - -- excXIAndExcYI_uid70_fpMulTest(LOGICAL,69)@5 - excXIAndExcYI_uid70_fpMulTest_q <= redist12_excI_x_uid19_fpMulTest_q_2_q and redist6_excI_y_uid33_fpMulTest_q_2_q; - - -- excRInf_uid74_fpMulTest(LOGICAL,73)@5 + -- excRInf_uid74_fpMulTest(LOGICAL,73)@3 excRInf_uid74_fpMulTest_q <= excXIAndExcYI_uid70_fpMulTest_q or excXRAndExcYI_uid71_fpMulTest_q or excYRAndExcXI_uid72_fpMulTest_q or ExcROvfAndInReg_uid73_fpMulTest_q; - -- expUdf_uid62_fpMulTest(COMPARE,61)@4 + 1 - expUdf_uid62_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0000000000000" & GND_q)); - expUdf_uid62_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 12 => redist1_expRPreExcExt_uid60_fpMulTest_b_1_q(11)) & redist1_expRPreExcExt_uid60_fpMulTest_b_1_q)); - expUdf_uid62_fpMulTest_clkproc: PROCESS (clk, areset) - BEGIN - IF (areset = '1') THEN - expUdf_uid62_fpMulTest_o <= (others => '0'); - ELSIF (clk'EVENT AND clk = '1') THEN - expUdf_uid62_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid62_fpMulTest_a) - SIGNED(expUdf_uid62_fpMulTest_b)); - END IF; - END PROCESS; - expUdf_uid62_fpMulTest_n(0) <= not (expUdf_uid62_fpMulTest_o(13)); + -- expUdf_uid62_fpMulTest(COMPARE,61)@3 + expUdf_uid62_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0000000000" & GND_q)); + expUdf_uid62_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist0_expRPreExcExt_uid60_fpMulTest_b_1_q(8)) & redist0_expRPreExcExt_uid60_fpMulTest_b_1_q)); + expUdf_uid62_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid62_fpMulTest_a) - SIGNED(expUdf_uid62_fpMulTest_b)); + expUdf_uid62_fpMulTest_n(0) <= not (expUdf_uid62_fpMulTest_o(10)); - -- excZC3_uid68_fpMulTest(LOGICAL,67)@5 + -- excZC3_uid68_fpMulTest(LOGICAL,67)@3 excZC3_uid68_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expUdf_uid62_fpMulTest_n; - -- redist11_excZ_y_uid29_fpMulTest_q_5(DELAY,108) - redist11_excZ_y_uid29_fpMulTest_q_5 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => redist10_excZ_y_uid29_fpMulTest_q_4_q, xout => redist11_excZ_y_uid29_fpMulTest_q_5_q, clk => clk, aclr => areset ); + -- excYZAndExcXR_uid67_fpMulTest(LOGICAL,66)@3 + excYZAndExcXR_uid67_fpMulTest_q <= redist5_excZ_y_uid29_fpMulTest_q_2_q and excR_x_uid23_fpMulTest_q; - -- excYZAndExcXR_uid67_fpMulTest(LOGICAL,66)@5 - excYZAndExcXR_uid67_fpMulTest_q <= redist11_excZ_y_uid29_fpMulTest_q_5_q and excR_x_uid23_fpMulTest_q; + -- excXZAndExcYR_uid66_fpMulTest(LOGICAL,65)@3 + excXZAndExcYR_uid66_fpMulTest_q <= redist8_excZ_x_uid15_fpMulTest_q_2_q and excR_y_uid37_fpMulTest_q; - -- redist17_excZ_x_uid15_fpMulTest_q_5(DELAY,114) - redist17_excZ_x_uid15_fpMulTest_q_5 : dspba_delay - GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) - PORT MAP ( xin => redist16_excZ_x_uid15_fpMulTest_q_4_q, xout => redist17_excZ_x_uid15_fpMulTest_q_5_q, clk => clk, aclr => areset ); - - -- excXZAndExcYR_uid66_fpMulTest(LOGICAL,65)@5 - excXZAndExcYR_uid66_fpMulTest_q <= redist17_excZ_x_uid15_fpMulTest_q_5_q and excR_y_uid37_fpMulTest_q; + -- excXZAndExcYZ_uid65_fpMulTest(LOGICAL,64)@3 + excXZAndExcYZ_uid65_fpMulTest_q <= redist8_excZ_x_uid15_fpMulTest_q_2_q and redist5_excZ_y_uid29_fpMulTest_q_2_q; - -- excXZAndExcYZ_uid65_fpMulTest(LOGICAL,64)@5 - excXZAndExcYZ_uid65_fpMulTest_q <= redist17_excZ_x_uid15_fpMulTest_q_5_q and redist11_excZ_y_uid29_fpMulTest_q_5_q; - - -- excRZero_uid69_fpMulTest(LOGICAL,68)@5 + -- excRZero_uid69_fpMulTest(LOGICAL,68)@3 excRZero_uid69_fpMulTest_q <= excXZAndExcYZ_uid65_fpMulTest_q or excXZAndExcYR_uid66_fpMulTest_q or excYZAndExcXR_uid67_fpMulTest_q or excZC3_uid68_fpMulTest_q; - -- concExc_uid79_fpMulTest(BITJOIN,78)@5 + -- concExc_uid79_fpMulTest(BITJOIN,78)@3 concExc_uid79_fpMulTest_q <= excRNaN_uid78_fpMulTest_q & excRInf_uid74_fpMulTest_q & excRZero_uid69_fpMulTest_q; - -- excREnc_uid80_fpMulTest(LOOKUP,79)@5 + 1 - excREnc_uid80_fpMulTest_clkproc: PROCESS (clk, areset) + -- excREnc_uid80_fpMulTest(LOOKUP,79)@3 + excREnc_uid80_fpMulTest_combproc: PROCESS (concExc_uid79_fpMulTest_q) BEGIN - IF (areset = '1') THEN - excREnc_uid80_fpMulTest_q <= "01"; - ELSIF (clk'EVENT AND clk = '1') THEN - CASE (concExc_uid79_fpMulTest_q) IS - WHEN "000" => excREnc_uid80_fpMulTest_q <= "01"; - WHEN "001" => excREnc_uid80_fpMulTest_q <= "00"; - WHEN "010" => excREnc_uid80_fpMulTest_q <= "10"; - WHEN "011" => excREnc_uid80_fpMulTest_q <= "00"; - WHEN "100" => excREnc_uid80_fpMulTest_q <= "11"; - WHEN "101" => excREnc_uid80_fpMulTest_q <= "00"; - WHEN "110" => excREnc_uid80_fpMulTest_q <= "00"; - WHEN "111" => excREnc_uid80_fpMulTest_q <= "00"; - WHEN OTHERS => -- unreachable - excREnc_uid80_fpMulTest_q <= (others => '-'); - END CASE; - END IF; + -- Begin reserved scope level + CASE (concExc_uid79_fpMulTest_q) IS + WHEN "000" => excREnc_uid80_fpMulTest_q <= "01"; + WHEN "001" => excREnc_uid80_fpMulTest_q <= "00"; + WHEN "010" => excREnc_uid80_fpMulTest_q <= "10"; + WHEN "011" => excREnc_uid80_fpMulTest_q <= "00"; + WHEN "100" => excREnc_uid80_fpMulTest_q <= "11"; + WHEN "101" => excREnc_uid80_fpMulTest_q <= "00"; + WHEN "110" => excREnc_uid80_fpMulTest_q <= "00"; + WHEN "111" => excREnc_uid80_fpMulTest_q <= "00"; + WHEN OTHERS => -- unreachable + excREnc_uid80_fpMulTest_q <= (others => '-'); + END CASE; + -- End reserved scope level END PROCESS; - -- expRPostExc_uid89_fpMulTest(MUX,88)@6 + -- expRPostExc_uid89_fpMulTest(MUX,88)@3 expRPostExc_uid89_fpMulTest_s <= excREnc_uid80_fpMulTest_q; - expRPostExc_uid89_fpMulTest_combproc: PROCESS (expRPostExc_uid89_fpMulTest_s, cstAllZWE_uid12_fpMulTest_q, redist0_expRPreExc_uid61_fpMulTest_b_2_q, cstAllOWE_uid10_fpMulTest_q) + expRPostExc_uid89_fpMulTest_combproc: PROCESS (expRPostExc_uid89_fpMulTest_s, en, cstAllZWE_uid12_fpMulTest_q, expRPreExc_uid61_fpMulTest_b, cstAllOWE_uid10_fpMulTest_q) BEGIN CASE (expRPostExc_uid89_fpMulTest_s) IS WHEN "00" => expRPostExc_uid89_fpMulTest_q <= cstAllZWE_uid12_fpMulTest_q; - WHEN "01" => expRPostExc_uid89_fpMulTest_q <= redist0_expRPreExc_uid61_fpMulTest_b_2_q; + WHEN "01" => expRPostExc_uid89_fpMulTest_q <= expRPreExc_uid61_fpMulTest_b; WHEN "10" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q; WHEN "11" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q; WHEN OTHERS => expRPostExc_uid89_fpMulTest_q <= (others => '0'); @@ -646,34 +548,34 @@ begin END PROCESS; -- oneFracRPostExc2_uid81_fpMulTest(CONSTANT,80) - oneFracRPostExc2_uid81_fpMulTest_q <= "00000000000000000000001"; + oneFracRPostExc2_uid81_fpMulTest_q <= "0000000001"; - -- fracRPreExc_uid59_fpMulTest(BITSELECT,58)@3 - fracRPreExc_uid59_fpMulTest_in <= expFracRPostRounding_uid58_fpMulTest_q(23 downto 0); - fracRPreExc_uid59_fpMulTest_b <= fracRPreExc_uid59_fpMulTest_in(23 downto 1); + -- fracRPreExc_uid59_fpMulTest(BITSELECT,58)@2 + fracRPreExc_uid59_fpMulTest_in <= expFracRPostRounding_uid58_fpMulTest_q(10 downto 0); + fracRPreExc_uid59_fpMulTest_b <= fracRPreExc_uid59_fpMulTest_in(10 downto 1); - -- redist2_fracRPreExc_uid59_fpMulTest_b_3(DELAY,99) - redist2_fracRPreExc_uid59_fpMulTest_b_3 : dspba_delay - GENERIC MAP ( width => 23, depth => 3, reset_kind => "ASYNC" ) - PORT MAP ( xin => fracRPreExc_uid59_fpMulTest_b, xout => redist2_fracRPreExc_uid59_fpMulTest_b_3_q, clk => clk, aclr => areset ); + -- redist1_fracRPreExc_uid59_fpMulTest_b_1(DELAY,98) + redist1_fracRPreExc_uid59_fpMulTest_b_1 : dspba_delay + GENERIC MAP ( width => 10, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => fracRPreExc_uid59_fpMulTest_b, xout => redist1_fracRPreExc_uid59_fpMulTest_b_1_q, ena => en(0), clk => clk, aclr => areset ); - -- fracRPostExc_uid84_fpMulTest(MUX,83)@6 + -- fracRPostExc_uid84_fpMulTest(MUX,83)@3 fracRPostExc_uid84_fpMulTest_s <= excREnc_uid80_fpMulTest_q; - fracRPostExc_uid84_fpMulTest_combproc: PROCESS (fracRPostExc_uid84_fpMulTest_s, cstZeroWF_uid11_fpMulTest_q, redist2_fracRPreExc_uid59_fpMulTest_b_3_q, oneFracRPostExc2_uid81_fpMulTest_q) + fracRPostExc_uid84_fpMulTest_combproc: PROCESS (fracRPostExc_uid84_fpMulTest_s, en, cstZeroWF_uid11_fpMulTest_q, redist1_fracRPreExc_uid59_fpMulTest_b_1_q, oneFracRPostExc2_uid81_fpMulTest_q) BEGIN CASE (fracRPostExc_uid84_fpMulTest_s) IS WHEN "00" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q; - WHEN "01" => fracRPostExc_uid84_fpMulTest_q <= redist2_fracRPreExc_uid59_fpMulTest_b_3_q; + WHEN "01" => fracRPostExc_uid84_fpMulTest_q <= redist1_fracRPreExc_uid59_fpMulTest_b_1_q; WHEN "10" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q; WHEN "11" => fracRPostExc_uid84_fpMulTest_q <= oneFracRPostExc2_uid81_fpMulTest_q; WHEN OTHERS => fracRPostExc_uid84_fpMulTest_q <= (others => '0'); END CASE; END PROCESS; - -- R_uid92_fpMulTest(BITJOIN,91)@6 + -- R_uid92_fpMulTest(BITJOIN,91)@3 R_uid92_fpMulTest_q <= signRPostExc_uid91_fpMulTest_q & expRPostExc_uid89_fpMulTest_q & fracRPostExc_uid84_fpMulTest_q; - -- xOut(GPOUT,4)@6 + -- xOut(GPOUT,4)@3 q <= R_uid92_fpMulTest_q; END normal; diff --git a/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl b/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl index 14027e6..ed471bb 100644 --- a/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl +++ b/ip/ip_fp_mul_sim/aldec/rivierapro_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.04:56:13 +# ACDS 20.1 720 linux 2023.10.21.20:27:56 # ---------------------------------------- # Auto-generated simulation script rivierapro_setup.tcl # ---------------------------------------- diff --git a/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh b/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh index 11435a9..e4268b4 100755 --- a/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh +++ b/ip/ip_fp_mul_sim/cadence/ncsim_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.04:56:13 +# ACDS 20.1 720 linux 2023.10.21.20:27:56 # ---------------------------------------- # ncsim - auto-generated simulation script @@ -106,7 +106,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.04:56:13 +# ACDS 20.1 720 linux 2023.10.21.20:27:56 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="ip_fp_mul" diff --git a/ip/ip_fp_mul_sim/ip_fp_mul.vo b/ip/ip_fp_mul_sim/ip_fp_mul.vo index bc00f70..a9b9007 100644 --- a/ip/ip_fp_mul_sim/ip_fp_mul.vo +++ b/ip/ip_fp_mul_sim/ip_fp_mul.vo @@ -27,7 +27,7 @@ //synopsys translate_off -//synthesis_resources = lut 268 mux21 24 oper_add 5 oper_mult 1 oper_mux 33 +//synthesis_resources = lut 87 mux21 11 oper_add 5 oper_mult 1 oper_mux 17 `timescale 1 ps / 1 ps module ip_fp_mul ( @@ -35,1558 +35,662 @@ module ip_fp_mul areset, b, clk, + en, q) /* synthesis synthesis_clearbox=1 */; - input [31:0] a; + input [15:0] a; input areset; - input [31:0] b; + input [15:0] b; input clk; - output [31:0] q; + input [0:0] en; + output [15:0] q; - reg n00i; - reg n00l; - reg n00O; - reg n01i; - reg n01l; - reg n01O; reg n0ii; reg n0il; reg n0iO; reg n0li; reg n0ll; - reg n0lO; reg n0Oi; reg n0Ol; reg n0OO; - reg n100i; - reg n100l; - reg n100O; - reg n101i; - reg n101l; - reg n101O; - reg n10i; - reg n10ii; - reg n10il; - reg n10iO; - reg n10l; - reg n10li; - reg n10ll; - reg n10lO; - reg n10O; - reg n10Oi; - reg n10Ol; - reg n10OO; - reg n110i; - reg n110l; - reg n110O; - reg n111i; - reg n111l; - reg n111O; - reg n11i; - reg n11ii; - reg n11il; - reg n11iO; - reg n11l; - reg n11li; - reg n11ll; - reg n11lO; - reg n11O; - reg n11Oi; - reg n11Ol; - reg n11OO; reg n1i; - reg n1i0i; - reg n1i0l; - reg n1i0O; - reg n1i1i; - reg n1i1l; - reg n1i1O; - reg n1ii; - reg n1iii; - reg n1iil; - reg n1iiO; - reg n1il; - reg n1ili; - reg n1ill; - reg n1ilO; - reg n1iO; - reg n1iOi; - reg n1iOl; - reg n1iOO; - reg n1l0i; - reg n1l0l; - reg n1l0O; - reg n1l1i; - reg n1l1l; - reg n1l1O; - reg n1li; - reg n1lii; - reg n1lil; - reg n1liO; - reg n1ll; - reg n1lli; - reg n1lll; - reg n1lO; reg n1O; - reg n1Oi; - reg n1Ol; - reg n1OO; + reg ni00i; + reg ni00l; + reg ni00O; reg ni0i; + reg ni0ii; + reg ni0il; + reg ni0iO; reg ni0l; + reg ni0li; + reg ni0ll; + reg ni0lO; reg ni0O; + reg ni0Oi; + reg ni0Ol; + reg ni0OO; reg ni1i; reg ni1l; reg ni1O; + reg nii0i; + reg nii0l; + reg nii0O; + reg nii1i; + reg nii1l; + reg nii1O; reg niii; + reg niiii; + reg niiil; + reg niiiO; reg niil; + reg niili; + reg niill; reg niilO; reg niiO; reg niiOi; + reg niiOl; + reg niiOO; + reg nil0i; + reg nil0l; + reg nil0O; + reg nil1i; + reg nil1l; + reg nil1O; reg nili; + reg nilii; + reg nilil; + reg niliO; reg nill; reg nilli; + reg nilll; + reg nillO; reg nilO; + reg nilOi; + reg nilOl; + reg nilOO; + reg niO0i; + reg niO1i; + reg niO1l; + reg niO1O; reg niOi; - reg niOii; reg niOl; - reg niOli; - reg niOll; - reg niOlO; reg niOO; - reg niOOi; - reg niOOl; - reg niOOO; - reg nl01i; - reg nl01l; - reg nl01O; reg nl0i; reg nl0l; reg nl0O; - reg nl10i; - reg nl10l; - reg nl10O; - reg nl11i; - reg nl11l; - reg nl11O; reg nl1i; - reg nl1ii; - reg nl1il; - reg nl1iO; reg nl1l; - reg nl1li; - reg nl1ll; - reg nl1lO; reg nl1O; - reg nl1Oi; - reg nl1Ol; - reg nl1OO; reg nlii; reg nlil; reg nliO; - reg nliOi; - reg nliOl; - reg nliOO; - reg nll0i; - reg nll0l; - reg nll0O; - reg nll1i; - reg nll1l; - reg nll1O; reg nlli; - reg nllii; - reg nllil; reg nlll; - reg nllli; - reg nllll; - reg nlllO; reg nllO; - reg nllO0i; - reg nllO0l; - reg nllO0O; - reg nllO1i; - reg nllO1l; - reg nllO1O; - reg nllOi; - reg nllOii; - reg nllOil; - reg nllOiO; - reg nllOl; - reg nllOli; - reg nllOll; - reg nllOlO; - reg nllOO; - reg nllOOi; - reg nllOOl; - reg nllOOO; - reg nlO00i; - reg nlO00l; - reg nlO00O; - reg nlO01i; - reg nlO01l; - reg nlO01O; - reg nlO0i; - reg nlO0ii; - reg nlO0il; - reg nlO0iO; - reg nlO0l; - reg nlO0li; - reg nlO0ll; - reg nlO0lO; - reg nlO0O; - reg nlO0Oi; - reg nlO0Ol; - reg nlO0OO; - reg nlO10i; - reg nlO10l; - reg nlO10O; - reg nlO11i; - reg nlO11l; - reg nlO11O; - reg nlO1i; - reg nlO1ii; - reg nlO1il; - reg nlO1iO; - reg nlO1l; - reg nlO1li; - reg nlO1ll; - reg nlO1lO; - reg nlO1Oi; - reg nlO1Ol; - reg nlO1OO; reg nlOi; - reg nlOi0i; - reg nlOi0l; - reg nlOi0O; - reg nlOi1i; - reg nlOi1l; - reg nlOi1O; - reg nlOii; - reg nlOiii; - reg nlOiil; - reg nlOiiO; - reg nlOil; - reg nlOili; - reg nlOill; - reg nlOilO; - reg nlOiO; - reg nlOiOi; - reg nlOiOl; - reg nlOiOO; reg nlOl; - reg nlOl0i; - reg nlOl0l; - reg nlOl0O; - reg nlOl1i; - reg nlOl1l; - reg nlOl1O; - reg nlOli; - reg nlOlii; - reg nlOlil; - reg nlOliO; - reg nlOll; - reg nlOlli; - reg nlOlll; - reg nlOllO; reg nlOlO; - reg nlOlOi; - reg nlOlOl; - reg nlOlOO; reg nlOO; - reg nlOO0i; - reg nlOO0l; - reg nlOO0O; - reg nlOO1i; - reg nlOO1l; - reg nlOO1O; - reg nlOOi; - reg nlOOii; - reg nlOOil; - reg nlOOiO; - reg nlOOl; - reg nlOOli; - reg nlOOll; - reg nlOOlO; - reg nlOOO; - reg nlOOOi; - reg nlOOOl; - reg nlOOOO; - reg niliO; - wire wire_nl00i_dataout; - wire wire_nl00l_dataout; - wire wire_nl00O_dataout; - wire wire_nl0ii_dataout; - wire wire_nl0il_dataout; - wire wire_nl0iO_dataout; - wire wire_nl0li_dataout; - wire wire_nl0ll_dataout; - wire wire_nl0lO_dataout; - wire wire_nl0Oi_dataout; - wire wire_nl0Ol_dataout; - wire wire_nl0OO_dataout; - wire wire_nli0i_dataout; - wire wire_nli0l_dataout; - wire wire_nli0O_dataout; - wire wire_nli1i_dataout; - wire wire_nli1l_dataout; - wire wire_nli1O_dataout; - wire wire_nliii_dataout; - wire wire_nliil_dataout; - wire wire_nliiO_dataout; - wire wire_nlili_dataout; - wire wire_nlill_dataout; - wire wire_nlilO_dataout; - wire [14:0] wire_nilll_o; - wire [14:0] wire_niOil_o; - wire [36:0] wire_niOiO_o; - wire [12:0] wire_nlliO_o; - wire [8:0] wire_nlO1O_o; - wire [47:0] wire_n0i_o; - wire wire_ni00i_o; - wire wire_ni00l_o; - wire wire_ni00O_o; - wire wire_ni01i_o; - wire wire_ni01l_o; - wire wire_ni01O_o; - wire wire_ni0ii_o; - wire wire_ni0il_o; - wire wire_ni0iO_o; - wire wire_ni0li_o; - wire wire_ni0ll_o; - wire wire_ni0lO_o; - wire wire_ni0Oi_o; - wire wire_ni0Ol_o; - wire wire_ni0OO_o; - wire wire_ni1ll_o; - wire wire_ni1lO_o; - wire wire_ni1Oi_o; - wire wire_ni1Ol_o; - wire wire_ni1OO_o; - wire wire_nii0i_o; - wire wire_nii0l_o; - wire wire_nii0O_o; - wire wire_nii1i_o; - wire wire_nii1l_o; - wire wire_nii1O_o; - wire wire_niiii_o; - wire wire_niiil_o; - wire wire_niiiO_o; - wire wire_niili_o; - wire wire_niill_o; - wire wire_niiOl_o; - wire wire_niiOO_o; - wire nlll0i; - wire nlll0l; - wire nlll0O; - wire nlllii; - wire nlllil; - wire nllliO; - wire nlllli; - wire nlllll; - wire nllllO; - wire nlllOl; + wire wire_n1l_ENA; + wire wire_n00i_dataout; + wire wire_n00l_dataout; + wire wire_n01i_dataout; + wire wire_n01l_dataout; + wire wire_n01O_dataout; + wire wire_n1li_dataout; + wire wire_n1ll_dataout; + wire wire_n1lO_dataout; + wire wire_n1Oi_dataout; + wire wire_n1Ol_dataout; + wire wire_n1OO_dataout; + wire [9:0] wire_n00O_o; + wire [5:0] wire_n0lO_o; + wire [11:0] wire_n1il_o; + wire [20:0] wire_n1iO_o; + wire [11:0] wire_nlOll_o; + wire [21:0] wire_n0i_o; + wire wire_nll0i_o; + wire wire_nll0l_o; + wire wire_nll0O_o; + wire wire_nll1l_o; + wire wire_nll1O_o; + wire wire_nllii_o; + wire wire_nllil_o; + wire wire_nlliO_o; + wire wire_nllli_o; + wire wire_nllll_o; + wire wire_nlllO_o; + wire wire_nllOi_o; + wire wire_nllOl_o; + wire wire_nllOO_o; + wire wire_nlO1i_o; + wire wire_nlO1l_o; + wire wire_nlO1O_o; + wire ni01i; + wire ni10i; + wire ni10l; + wire ni10O; + wire ni11l; + wire ni11O; + wire ni1ii; + wire ni1il; + wire ni1iO; + wire ni1li; + wire ni1ll; + wire ni1lO; + wire ni1Oi; + wire ni1Ol; + wire ni1OO; initial begin - n00i = 0; - n00l = 0; - n00O = 0; - n01i = 0; - n01l = 0; - n01O = 0; n0ii = 0; n0il = 0; n0iO = 0; n0li = 0; n0ll = 0; - n0lO = 0; n0Oi = 0; n0Ol = 0; n0OO = 0; - n100i = 0; - n100l = 0; - n100O = 0; - n101i = 0; - n101l = 0; - n101O = 0; - n10i = 0; - n10ii = 0; - n10il = 0; - n10iO = 0; - n10l = 0; - n10li = 0; - n10ll = 0; - n10lO = 0; - n10O = 0; - n10Oi = 0; - n10Ol = 0; - n10OO = 0; - n110i = 0; - n110l = 0; - n110O = 0; - n111i = 0; - n111l = 0; - n111O = 0; - n11i = 0; - n11ii = 0; - n11il = 0; - n11iO = 0; - n11l = 0; - n11li = 0; - n11ll = 0; - n11lO = 0; - n11O = 0; - n11Oi = 0; - n11Ol = 0; - n11OO = 0; n1i = 0; - n1i0i = 0; - n1i0l = 0; - n1i0O = 0; - n1i1i = 0; - n1i1l = 0; - n1i1O = 0; - n1ii = 0; - n1iii = 0; - n1iil = 0; - n1iiO = 0; - n1il = 0; - n1ili = 0; - n1ill = 0; - n1ilO = 0; - n1iO = 0; - n1iOi = 0; - n1iOl = 0; - n1iOO = 0; - n1l0i = 0; - n1l0l = 0; - n1l0O = 0; - n1l1i = 0; - n1l1l = 0; - n1l1O = 0; - n1li = 0; - n1lii = 0; - n1lil = 0; - n1liO = 0; - n1ll = 0; - n1lli = 0; - n1lll = 0; - n1lO = 0; n1O = 0; - n1Oi = 0; - n1Ol = 0; - n1OO = 0; + ni00i = 0; + ni00l = 0; + ni00O = 0; ni0i = 0; + ni0ii = 0; + ni0il = 0; + ni0iO = 0; ni0l = 0; + ni0li = 0; + ni0ll = 0; + ni0lO = 0; ni0O = 0; + ni0Oi = 0; + ni0Ol = 0; + ni0OO = 0; ni1i = 0; ni1l = 0; ni1O = 0; + nii0i = 0; + nii0l = 0; + nii0O = 0; + nii1i = 0; + nii1l = 0; + nii1O = 0; niii = 0; + niiii = 0; + niiil = 0; + niiiO = 0; niil = 0; + niili = 0; + niill = 0; niilO = 0; niiO = 0; niiOi = 0; + niiOl = 0; + niiOO = 0; + nil0i = 0; + nil0l = 0; + nil0O = 0; + nil1i = 0; + nil1l = 0; + nil1O = 0; nili = 0; + nilii = 0; + nilil = 0; + niliO = 0; nill = 0; nilli = 0; + nilll = 0; + nillO = 0; nilO = 0; + nilOi = 0; + nilOl = 0; + nilOO = 0; + niO0i = 0; + niO1i = 0; + niO1l = 0; + niO1O = 0; niOi = 0; - niOii = 0; niOl = 0; - niOli = 0; - niOll = 0; - niOlO = 0; niOO = 0; - niOOi = 0; - niOOl = 0; - niOOO = 0; - nl01i = 0; - nl01l = 0; - nl01O = 0; nl0i = 0; nl0l = 0; nl0O = 0; - nl10i = 0; - nl10l = 0; - nl10O = 0; - nl11i = 0; - nl11l = 0; - nl11O = 0; nl1i = 0; - nl1ii = 0; - nl1il = 0; - nl1iO = 0; nl1l = 0; - nl1li = 0; - nl1ll = 0; - nl1lO = 0; nl1O = 0; - nl1Oi = 0; - nl1Ol = 0; - nl1OO = 0; nlii = 0; nlil = 0; nliO = 0; - nliOi = 0; - nliOl = 0; - nliOO = 0; - nll0i = 0; - nll0l = 0; - nll0O = 0; - nll1i = 0; - nll1l = 0; - nll1O = 0; nlli = 0; - nllii = 0; - nllil = 0; nlll = 0; - nllli = 0; - nllll = 0; - nlllO = 0; nllO = 0; - nllO0i = 0; - nllO0l = 0; - nllO0O = 0; - nllO1i = 0; - nllO1l = 0; - nllO1O = 0; - nllOi = 0; - nllOii = 0; - nllOil = 0; - nllOiO = 0; - nllOl = 0; - nllOli = 0; - nllOll = 0; - nllOlO = 0; - nllOO = 0; - nllOOi = 0; - nllOOl = 0; - nllOOO = 0; - nlO00i = 0; - nlO00l = 0; - nlO00O = 0; - nlO01i = 0; - nlO01l = 0; - nlO01O = 0; - nlO0i = 0; - nlO0ii = 0; - nlO0il = 0; - nlO0iO = 0; - nlO0l = 0; - nlO0li = 0; - nlO0ll = 0; - nlO0lO = 0; - nlO0O = 0; - nlO0Oi = 0; - nlO0Ol = 0; - nlO0OO = 0; - nlO10i = 0; - nlO10l = 0; - nlO10O = 0; - nlO11i = 0; - nlO11l = 0; - nlO11O = 0; - nlO1i = 0; - nlO1ii = 0; - nlO1il = 0; - nlO1iO = 0; - nlO1l = 0; - nlO1li = 0; - nlO1ll = 0; - nlO1lO = 0; - nlO1Oi = 0; - nlO1Ol = 0; - nlO1OO = 0; nlOi = 0; - nlOi0i = 0; - nlOi0l = 0; - nlOi0O = 0; - nlOi1i = 0; - nlOi1l = 0; - nlOi1O = 0; - nlOii = 0; - nlOiii = 0; - nlOiil = 0; - nlOiiO = 0; - nlOil = 0; - nlOili = 0; - nlOill = 0; - nlOilO = 0; - nlOiO = 0; - nlOiOi = 0; - nlOiOl = 0; - nlOiOO = 0; nlOl = 0; - nlOl0i = 0; - nlOl0l = 0; - nlOl0O = 0; - nlOl1i = 0; - nlOl1l = 0; - nlOl1O = 0; - nlOli = 0; - nlOlii = 0; - nlOlil = 0; - nlOliO = 0; - nlOll = 0; - nlOlli = 0; - nlOlll = 0; - nlOllO = 0; nlOlO = 0; - nlOlOi = 0; - nlOlOl = 0; - nlOlOO = 0; nlOO = 0; - nlOO0i = 0; - nlOO0l = 0; - nlOO0O = 0; - nlOO1i = 0; - nlOO1l = 0; - nlOO1O = 0; - nlOOi = 0; - nlOOii = 0; - nlOOil = 0; - nlOOiO = 0; - nlOOl = 0; - nlOOli = 0; - nlOOll = 0; - nlOOlO = 0; - nlOOO = 0; - nlOOOi = 0; - nlOOOl = 0; - nlOOOO = 0; end always @ ( posedge clk or posedge areset) begin if (areset == 1'b1) begin - n00i <= 0; - n00l <= 0; - n00O <= 0; - n01i <= 0; - n01l <= 0; - n01O <= 0; n0ii <= 0; n0il <= 0; n0iO <= 0; n0li <= 0; n0ll <= 0; - n0lO <= 0; n0Oi <= 0; n0Ol <= 0; n0OO <= 0; - n100i <= 0; - n100l <= 0; - n100O <= 0; - n101i <= 0; - n101l <= 0; - n101O <= 0; - n10i <= 0; - n10ii <= 0; - n10il <= 0; - n10iO <= 0; - n10l <= 0; - n10li <= 0; - n10ll <= 0; - n10lO <= 0; - n10O <= 0; - n10Oi <= 0; - n10Ol <= 0; - n10OO <= 0; - n110i <= 0; - n110l <= 0; - n110O <= 0; - n111i <= 0; - n111l <= 0; - n111O <= 0; - n11i <= 0; - n11ii <= 0; - n11il <= 0; - n11iO <= 0; - n11l <= 0; - n11li <= 0; - n11ll <= 0; - n11lO <= 0; - n11O <= 0; - n11Oi <= 0; - n11Ol <= 0; - n11OO <= 0; n1i <= 0; - n1i0i <= 0; - n1i0l <= 0; - n1i0O <= 0; - n1i1i <= 0; - n1i1l <= 0; - n1i1O <= 0; - n1ii <= 0; - n1iii <= 0; - n1iil <= 0; - n1iiO <= 0; - n1il <= 0; - n1ili <= 0; - n1ill <= 0; - n1ilO <= 0; - n1iO <= 0; - n1iOi <= 0; - n1iOl <= 0; - n1iOO <= 0; - n1l0i <= 0; - n1l0l <= 0; - n1l0O <= 0; - n1l1i <= 0; - n1l1l <= 0; - n1l1O <= 0; - n1li <= 0; - n1lii <= 0; - n1lil <= 0; - n1liO <= 0; - n1ll <= 0; - n1lli <= 0; - n1lll <= 0; - n1lO <= 0; n1O <= 0; - n1Oi <= 0; - n1Ol <= 0; - n1OO <= 0; + ni00i <= 0; + ni00l <= 0; + ni00O <= 0; ni0i <= 0; + ni0ii <= 0; + ni0il <= 0; + ni0iO <= 0; ni0l <= 0; + ni0li <= 0; + ni0ll <= 0; + ni0lO <= 0; ni0O <= 0; + ni0Oi <= 0; + ni0Ol <= 0; + ni0OO <= 0; ni1i <= 0; ni1l <= 0; ni1O <= 0; + nii0i <= 0; + nii0l <= 0; + nii0O <= 0; + nii1i <= 0; + nii1l <= 0; + nii1O <= 0; niii <= 0; + niiii <= 0; + niiil <= 0; + niiiO <= 0; niil <= 0; + niili <= 0; + niill <= 0; niilO <= 0; niiO <= 0; niiOi <= 0; + niiOl <= 0; + niiOO <= 0; + nil0i <= 0; + nil0l <= 0; + nil0O <= 0; + nil1i <= 0; + nil1l <= 0; + nil1O <= 0; nili <= 0; + nilii <= 0; + nilil <= 0; + niliO <= 0; nill <= 0; nilli <= 0; + nilll <= 0; + nillO <= 0; nilO <= 0; + nilOi <= 0; + nilOl <= 0; + nilOO <= 0; + niO0i <= 0; + niO1i <= 0; + niO1l <= 0; + niO1O <= 0; niOi <= 0; - niOii <= 0; niOl <= 0; - niOli <= 0; - niOll <= 0; - niOlO <= 0; niOO <= 0; - niOOi <= 0; - niOOl <= 0; - niOOO <= 0; - nl01i <= 0; - nl01l <= 0; - nl01O <= 0; nl0i <= 0; nl0l <= 0; nl0O <= 0; - nl10i <= 0; - nl10l <= 0; - nl10O <= 0; - nl11i <= 0; - nl11l <= 0; - nl11O <= 0; nl1i <= 0; - nl1ii <= 0; - nl1il <= 0; - nl1iO <= 0; nl1l <= 0; - nl1li <= 0; - nl1ll <= 0; - nl1lO <= 0; nl1O <= 0; - nl1Oi <= 0; - nl1Ol <= 0; - nl1OO <= 0; nlii <= 0; nlil <= 0; nliO <= 0; - nliOi <= 0; - nliOl <= 0; - nliOO <= 0; - nll0i <= 0; - nll0l <= 0; - nll0O <= 0; - nll1i <= 0; - nll1l <= 0; - nll1O <= 0; nlli <= 0; - nllii <= 0; - nllil <= 0; nlll <= 0; - nllli <= 0; - nllll <= 0; - nlllO <= 0; nllO <= 0; - nllO0i <= 0; - nllO0l <= 0; - nllO0O <= 0; - nllO1i <= 0; - nllO1l <= 0; - nllO1O <= 0; - nllOi <= 0; - nllOii <= 0; - nllOil <= 0; - nllOiO <= 0; - nllOl <= 0; - nllOli <= 0; - nllOll <= 0; - nllOlO <= 0; - nllOO <= 0; - nllOOi <= 0; - nllOOl <= 0; - nllOOO <= 0; - nlO00i <= 0; - nlO00l <= 0; - nlO00O <= 0; - nlO01i <= 0; - nlO01l <= 0; - nlO01O <= 0; - nlO0i <= 0; - nlO0ii <= 0; - nlO0il <= 0; - nlO0iO <= 0; - nlO0l <= 0; - nlO0li <= 0; - nlO0ll <= 0; - nlO0lO <= 0; - nlO0O <= 0; - nlO0Oi <= 0; - nlO0Ol <= 0; - nlO0OO <= 0; - nlO10i <= 0; - nlO10l <= 0; - nlO10O <= 0; - nlO11i <= 0; - nlO11l <= 0; - nlO11O <= 0; - nlO1i <= 0; - nlO1ii <= 0; - nlO1il <= 0; - nlO1iO <= 0; - nlO1l <= 0; - nlO1li <= 0; - nlO1ll <= 0; - nlO1lO <= 0; - nlO1Oi <= 0; - nlO1Ol <= 0; - nlO1OO <= 0; nlOi <= 0; - nlOi0i <= 0; - nlOi0l <= 0; - nlOi0O <= 0; - nlOi1i <= 0; - nlOi1l <= 0; - nlOi1O <= 0; - nlOii <= 0; - nlOiii <= 0; - nlOiil <= 0; - nlOiiO <= 0; - nlOil <= 0; - nlOili <= 0; - nlOill <= 0; - nlOilO <= 0; - nlOiO <= 0; - nlOiOi <= 0; - nlOiOl <= 0; - nlOiOO <= 0; nlOl <= 0; - nlOl0i <= 0; - nlOl0l <= 0; - nlOl0O <= 0; - nlOl1i <= 0; - nlOl1l <= 0; - nlOl1O <= 0; - nlOli <= 0; - nlOlii <= 0; - nlOlil <= 0; - nlOliO <= 0; - nlOll <= 0; - nlOlli <= 0; - nlOlll <= 0; - nlOllO <= 0; nlOlO <= 0; - nlOlOi <= 0; - nlOlOl <= 0; - nlOlOO <= 0; nlOO <= 0; - nlOO0i <= 0; - nlOO0l <= 0; - nlOO0O <= 0; - nlOO1i <= 0; - nlOO1l <= 0; - nlOO1O <= 0; - nlOOi <= 0; - nlOOii <= 0; - nlOOil <= 0; - nlOOiO <= 0; - nlOOl <= 0; - nlOOli <= 0; - nlOOll <= 0; - nlOOlO <= 0; - nlOOO <= 0; - nlOOOi <= 0; - nlOOOl <= 0; - nlOOOO <= 0; end - else + else if (wire_n1l_ENA == 1'b1) begin - n00i <= b[4]; - n00l <= b[5]; - n00O <= b[6]; - n01i <= b[1]; - n01l <= b[2]; - n01O <= b[3]; - n0ii <= b[7]; - n0il <= b[8]; - n0iO <= b[9]; - n0li <= b[10]; - n0ll <= b[11]; - n0lO <= b[12]; - n0Oi <= b[13]; - n0Ol <= b[14]; - n0OO <= b[15]; - n100i <= n1ilO; - n100l <= n1iOi; - n100O <= n1iOl; - n101i <= n1iiO; - n101l <= n1ili; - n101O <= n1ill; - n10i <= wire_n0i_o[37]; - n10ii <= n1iOO; - n10il <= n1l1i; - n10iO <= n1l1l; - n10l <= wire_n0i_o[38]; - n10li <= n1l1O; - n10ll <= n1l0i; - n10lO <= n1l0l; - n10O <= wire_n0i_o[39]; - n10Oi <= n1l0O; - n10Ol <= n1lii; - n10OO <= n1lil; - n110i <= n10lO; - n110l <= n10Oi; - n110O <= n10Ol; - n111i <= n10iO; - n111l <= n10li; - n111O <= n10ll; - n11i <= wire_n0i_o[34]; - n11ii <= n10OO; - n11il <= n1i1i; - n11iO <= n1i1l; - n11l <= wire_n0i_o[35]; - n11li <= n1i1O; - n11ll <= n1i0i; - n11lO <= n1i0l; - n11O <= wire_n0i_o[36]; - n11Oi <= n1i0O; - n11Ol <= n1iii; - n11OO <= n1iil; - n1i <= a[22]; - n1i0i <= wire_niOiO_o[1]; - n1i0l <= wire_niOiO_o[2]; - n1i0O <= wire_niOiO_o[3]; - n1i1i <= n1liO; - n1i1l <= n1lli; - n1i1O <= n1lll; - n1ii <= wire_n0i_o[40]; - n1iii <= wire_niOiO_o[4]; - n1iil <= wire_niOiO_o[5]; - n1iiO <= wire_niOiO_o[6]; - n1il <= wire_n0i_o[41]; - n1ili <= wire_niOiO_o[7]; - n1ill <= wire_niOiO_o[8]; - n1ilO <= wire_niOiO_o[9]; - n1iO <= wire_n0i_o[42]; - n1iOi <= wire_niOiO_o[10]; - n1iOl <= wire_niOiO_o[11]; - n1iOO <= wire_niOiO_o[12]; - n1l0i <= wire_niOiO_o[16]; - n1l0l <= wire_niOiO_o[17]; - n1l0O <= wire_niOiO_o[18]; - n1l1i <= wire_niOiO_o[13]; - n1l1l <= wire_niOiO_o[14]; - n1l1O <= wire_niOiO_o[15]; - n1li <= wire_n0i_o[43]; - n1lii <= wire_niOiO_o[19]; - n1lil <= wire_niOiO_o[20]; - n1liO <= wire_niOiO_o[21]; - n1ll <= wire_n0i_o[44]; - n1lli <= wire_niOiO_o[22]; - n1lll <= wire_niOiO_o[23]; - n1lO <= wire_n0i_o[45]; - n1O <= nlllOl; - n1Oi <= wire_n0i_o[46]; - n1Ol <= wire_n0i_o[47]; - n1OO <= b[0]; - ni0i <= b[19]; - ni0l <= b[20]; - ni0O <= b[21]; - ni1i <= b[16]; - ni1l <= b[17]; - ni1O <= b[18]; - niii <= b[22]; - niil <= nlllOl; - niilO <= wire_niiOO_o; - niiO <= a[0]; - niiOi <= wire_nilll_o[14]; - nili <= a[1]; - nill <= a[2]; - nilli <= wire_niOil_o[14]; - nilO <= a[3]; - niOi <= a[4]; - niOii <= wire_nl00i_dataout; - niOl <= a[5]; - niOli <= wire_nl00l_dataout; - niOll <= wire_nl00O_dataout; - niOlO <= wire_nl0ii_dataout; - niOO <= a[6]; - niOOi <= wire_nl0il_dataout; - niOOl <= wire_nl0iO_dataout; - niOOO <= wire_nl0li_dataout; - nl01i <= wire_nlill_dataout; - nl01l <= wire_nlilO_dataout; - nl01O <= wire_nlliO_o[1]; - nl0i <= a[10]; - nl0l <= a[11]; - nl0O <= a[12]; - nl10i <= wire_nl0Ol_dataout; - nl10l <= wire_nl0OO_dataout; - nl10O <= wire_nli1i_dataout; - nl11i <= wire_nl0ll_dataout; - nl11l <= wire_nl0lO_dataout; - nl11O <= wire_nl0Oi_dataout; - nl1i <= a[7]; - nl1ii <= wire_nli1l_dataout; - nl1il <= wire_nli1O_dataout; - nl1iO <= wire_nli0i_dataout; - nl1l <= a[8]; - nl1li <= wire_nli0l_dataout; - nl1ll <= wire_nli0O_dataout; - nl1lO <= wire_nliii_dataout; - nl1O <= a[9]; - nl1Oi <= wire_nliil_dataout; - nl1Ol <= wire_nliiO_dataout; - nl1OO <= wire_nlili_dataout; - nlii <= a[13]; - nlil <= a[14]; - nliO <= a[15]; - nliOi <= wire_nlliO_o[2]; - nliOl <= wire_nlliO_o[3]; - nliOO <= wire_nlliO_o[4]; - nll0i <= wire_nlliO_o[8]; - nll0l <= wire_nlliO_o[9]; - nll0O <= wire_nlliO_o[10]; - nll1i <= wire_nlliO_o[5]; - nll1l <= wire_nlliO_o[6]; - nll1O <= wire_nlliO_o[7]; - nlli <= a[16]; - nllii <= wire_nlliO_o[11]; - nllil <= wire_nlO1O_o[0]; - nlll <= a[17]; - nllli <= wire_nlO1O_o[1]; - nllll <= wire_nlO1O_o[2]; - nlllO <= wire_nlO1O_o[3]; - nllO <= a[18]; - nllO0i <= nlllil; - nllO0l <= nllO0O; - nllO0O <= nllO0i; - nllO1i <= nllliO; - nllO1l <= nllO1O; - nllO1O <= nllO1i; - nllOi <= wire_nlO1O_o[4]; - nllOii <= (nllO1l & nllO0l); - nllOil <= nlllii; - nllOiO <= nllOli; - nllOl <= wire_nlO1O_o[5]; - nllOli <= nllOll; - nllOll <= nllOil; - nllOlO <= nlll0O; - nllOO <= wire_nlO1O_o[6]; - nllOOi <= nllOOl; - nllOOl <= nllOlO; - nllOOO <= nlll0l; - nlO00i <= n1Ol; - nlO00l <= nllil; - nlO00O <= nllli; - nlO01i <= nlO01l; - nlO01l <= nlO1Oi; - nlO01O <= ((~ nlO1lO) & nlO1Ol); - nlO0i <= wire_n0i_o[22]; - nlO0ii <= nllll; - nlO0il <= nlllO; - nlO0iO <= nllOi; - nlO0l <= wire_n0i_o[23]; - nlO0li <= nllOl; - nlO0ll <= nllOO; - nlO0lO <= nlO1i; - nlO0O <= wire_n0i_o[24]; - nlO0Oi <= nlO1l; - nlO0Ol <= wire_niOiO_o[24]; - nlO0OO <= wire_niOiO_o[25]; - nlO10i <= nlll0i; - nlO10l <= nlO10O; - nlO10O <= nlO1ii; - nlO11i <= nlO11l; - nlO11l <= nllOOO; - nlO11O <= (nllOOi & nlO11i); - nlO1i <= wire_nlO1O_o[7]; - nlO1ii <= nlO10i; - nlO1il <= (~ nllOOi); - nlO1iO <= nlO11i; - nlO1l <= wire_nlO1O_o[8]; - nlO1li <= (~ nllO1l); - nlO1ll <= nllO0l; - nlO1lO <= (((nllOii & nllOiO) | (nlO11O & nlO10l)) | ((nlO1il & nlO1iO) | (nlO1li & nlO1ll))); - nlO1Oi <= (a[31] ^ b[31]); - nlO1Ol <= nlO1OO; - nlO1OO <= nlO01i; - nlOi <= a[19]; - nlOi0i <= wire_niOiO_o[29]; - nlOi0l <= wire_niOiO_o[30]; - nlOi0O <= wire_niOiO_o[31]; - nlOi1i <= wire_niOiO_o[26]; - nlOi1l <= wire_niOiO_o[27]; - nlOi1O <= wire_niOiO_o[28]; - nlOii <= wire_n0i_o[25]; - nlOiii <= wire_niOiO_o[32]; - nlOiil <= wire_niOiO_o[33]; - nlOiiO <= wire_niOiO_o[34]; - nlOil <= wire_n0i_o[26]; - nlOili <= wire_niOiO_o[35]; - nlOill <= nlOl0i; - nlOilO <= nlOl0l; - nlOiO <= wire_n0i_o[27]; - nlOiOi <= nlOl0O; - nlOiOl <= nlOlii; - nlOiOO <= nlOlil; - nlOl <= a[20]; - nlOl0i <= nlO0Ol; - nlOl0l <= nlO0OO; - nlOl0O <= nlOi1i; - nlOl1i <= nlOliO; - nlOl1l <= nlOlli; - nlOl1O <= nlOlll; - nlOli <= wire_n0i_o[28]; - nlOlii <= nlOi1l; - nlOlil <= nlOi1O; - nlOliO <= nlOi0i; - nlOll <= wire_n0i_o[29]; - nlOlli <= nlOi0l; - nlOlll <= nlOi0O; - nlOllO <= ((~ nllOiO) & (~ nlO1iO)); - nlOlO <= wire_n0i_o[30]; - nlOlOi <= ((~ nlO10l) & (~ nlO1ll)); - nlOlOl <= nllOii; - nlOlOO <= nlO11O; - nlOO <= a[21]; - nlOO0i <= n11lO; - nlOO0l <= n11Oi; - nlOO0O <= n11Ol; - nlOO1i <= nllOiO; - nlOO1l <= nlO10l; - nlOO1O <= n11ll; - nlOOi <= wire_n0i_o[31]; - nlOOii <= n11OO; - nlOOil <= n101i; - nlOOiO <= n101l; - nlOOl <= wire_n0i_o[32]; - nlOOli <= n101O; - nlOOll <= n100i; - nlOOlO <= n100l; - nlOOO <= wire_n0i_o[33]; - nlOOOi <= n100O; - nlOOOl <= n10ii; - nlOOOO <= n10il; + n0ii <= wire_n0lO_o[1]; + n0il <= wire_n0lO_o[2]; + n0iO <= wire_n0lO_o[3]; + n0li <= wire_n0lO_o[4]; + n0ll <= wire_n0lO_o[5]; + n0Oi <= wire_n0i_o[9]; + n0Ol <= wire_n0i_o[10]; + n0OO <= wire_n0i_o[11]; + n1i <= a[9]; + n1O <= ni1Oi; + ni00i <= ni1ii; + ni00l <= ni00O; + ni00O <= ni00i; + ni0i <= wire_n0i_o[15]; + ni0ii <= a[10]; + ni0il <= a[11]; + ni0iO <= a[12]; + ni0l <= wire_n0i_o[16]; + ni0li <= a[13]; + ni0ll <= a[14]; + ni0lO <= ni10O; + ni0O <= wire_n0i_o[17]; + ni0Oi <= ni0lO; + ni0Ol <= b[10]; + ni0OO <= b[11]; + ni1i <= wire_n0i_o[12]; + ni1l <= wire_n0i_o[13]; + ni1O <= wire_n0i_o[14]; + nii0i <= ni10l; + nii0l <= nii0i; + nii0O <= ni10i; + nii1i <= b[12]; + nii1l <= b[13]; + nii1O <= b[14]; + niii <= wire_n0i_o[18]; + niiii <= niiil; + niiil <= nii0O; + niiiO <= ni11O; + niil <= wire_n0i_o[19]; + niili <= niiiO; + niill <= ni11l; + niilO <= niill; + niiO <= wire_n0i_o[20]; + niiOi <= (a[15] ^ b[15]); + niiOl <= niiOO; + niiOO <= niiOi; + nil0i <= wire_n1iO_o[14]; + nil0l <= wire_n1iO_o[15]; + nil0O <= wire_n1iO_o[16]; + nil1i <= wire_n1iO_o[11]; + nil1l <= wire_n1iO_o[12]; + nil1O <= wire_n1iO_o[13]; + nili <= wire_n0i_o[21]; + nilii <= wire_n1iO_o[17]; + nilil <= wire_n1iO_o[18]; + niliO <= wire_n1iO_o[19]; + nill <= b[0]; + nilli <= wire_n1iO_o[1]; + nilll <= wire_n1iO_o[2]; + nillO <= wire_n1iO_o[3]; + nilO <= b[1]; + nilOi <= wire_n1iO_o[4]; + nilOl <= wire_n1iO_o[5]; + nilOO <= wire_n1iO_o[6]; + niO0i <= wire_n1iO_o[10]; + niO1i <= wire_n1iO_o[7]; + niO1l <= wire_n1iO_o[8]; + niO1O <= wire_n1iO_o[9]; + niOi <= b[2]; + niOl <= b[3]; + niOO <= b[4]; + nl0i <= b[8]; + nl0l <= b[9]; + nl0O <= ni1Oi; + nl1i <= b[5]; + nl1l <= b[6]; + nl1O <= b[7]; + nlii <= a[0]; + nlil <= a[1]; + nliO <= a[2]; + nlli <= a[3]; + nlll <= a[4]; + nllO <= a[5]; + nlOi <= a[6]; + nlOl <= a[7]; + nlOlO <= wire_n0lO_o[0]; + nlOO <= a[8]; end end - initial - begin - niliO = 0; - end - always @ ( posedge clk or posedge areset) - begin - if (areset == 1'b1) - begin - niliO <= 1; - end - else - begin - niliO <= wire_niiOl_o; - end - end - event niliO_event; - initial - #1 ->niliO_event; - always @(niliO_event) - niliO <= 1; - assign wire_nl00i_dataout = ((~ n1Ol) === 1'b1) ? nlO0i : nlO0l; - assign wire_nl00l_dataout = ((~ n1Ol) === 1'b1) ? nlO0l : nlO0O; - assign wire_nl00O_dataout = ((~ n1Ol) === 1'b1) ? nlO0O : nlOii; - assign wire_nl0ii_dataout = ((~ n1Ol) === 1'b1) ? nlOii : nlOil; - assign wire_nl0il_dataout = ((~ n1Ol) === 1'b1) ? nlOil : nlOiO; - assign wire_nl0iO_dataout = ((~ n1Ol) === 1'b1) ? nlOiO : nlOli; - assign wire_nl0li_dataout = ((~ n1Ol) === 1'b1) ? nlOli : nlOll; - assign wire_nl0ll_dataout = ((~ n1Ol) === 1'b1) ? nlOll : nlOlO; - assign wire_nl0lO_dataout = ((~ n1Ol) === 1'b1) ? nlOlO : nlOOi; - assign wire_nl0Oi_dataout = ((~ n1Ol) === 1'b1) ? nlOOi : nlOOl; - assign wire_nl0Ol_dataout = ((~ n1Ol) === 1'b1) ? nlOOl : nlOOO; - assign wire_nl0OO_dataout = ((~ n1Ol) === 1'b1) ? nlOOO : n11i; - assign wire_nli0i_dataout = ((~ n1Ol) === 1'b1) ? n10i : n10l; - assign wire_nli0l_dataout = ((~ n1Ol) === 1'b1) ? n10l : n10O; - assign wire_nli0O_dataout = ((~ n1Ol) === 1'b1) ? n10O : n1ii; - assign wire_nli1i_dataout = ((~ n1Ol) === 1'b1) ? n11i : n11l; - assign wire_nli1l_dataout = ((~ n1Ol) === 1'b1) ? n11l : n11O; - assign wire_nli1O_dataout = ((~ n1Ol) === 1'b1) ? n11O : n10i; - assign wire_nliii_dataout = ((~ n1Ol) === 1'b1) ? n1ii : n1il; - assign wire_nliil_dataout = ((~ n1Ol) === 1'b1) ? n1il : n1iO; - assign wire_nliiO_dataout = ((~ n1Ol) === 1'b1) ? n1iO : n1li; - assign wire_nlili_dataout = ((~ n1Ol) === 1'b1) ? n1li : n1ll; - assign wire_nlill_dataout = ((~ n1Ol) === 1'b1) ? n1ll : n1lO; - assign wire_nlilO_dataout = ((~ n1Ol) === 1'b1) ? n1lO : n1Oi; - oper_add nilll - ( - .a({{3{(~ nlOili)}}, (~ nlOiiO), (~ nlOiil), (~ nlOiii), (~ nlOi0O), (~ nlOi0l), (~ nlOi0i), (~ nlOi1O), (~ nlOi1l), (~ nlOi1i), (~ nlO0OO), (~ nlO0Ol), 1'b1}), - .b({{14{1'b0}}, 1'b1}), + assign + wire_n1l_ENA = en[0]; + assign wire_n00i_dataout = ((~ nili) === 1'b1) ? niii : niil; + assign wire_n00l_dataout = ((~ nili) === 1'b1) ? niil : niiO; + assign wire_n01i_dataout = ((~ nili) === 1'b1) ? ni0i : ni0l; + assign wire_n01l_dataout = ((~ nili) === 1'b1) ? ni0l : ni0O; + assign wire_n01O_dataout = ((~ nili) === 1'b1) ? ni0O : niii; + assign wire_n1li_dataout = ((~ nili) === 1'b1) ? n0Oi : n0Ol; + assign wire_n1ll_dataout = ((~ nili) === 1'b1) ? n0Ol : n0OO; + assign wire_n1lO_dataout = ((~ nili) === 1'b1) ? n0OO : ni1i; + assign wire_n1Oi_dataout = ((~ nili) === 1'b1) ? ni1i : ni1l; + assign wire_n1Ol_dataout = ((~ nili) === 1'b1) ? ni1l : ni1O; + assign wire_n1OO_dataout = ((~ nili) === 1'b1) ? ni1O : ni0i; + oper_add n00O + ( + .a({{3{1'b0}}, n0ll, n0li, n0iO, n0il, n0ii, nlOlO, 1'b1}), + .b({{5{1'b1}}, {4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), - .o(wire_nilll_o)); + .o(wire_n00O_o)); defparam - nilll.sgate_representation = 0, - nilll.width_a = 15, - nilll.width_b = 15, - nilll.width_o = 15; - oper_add niOil + n00O.sgate_representation = 0, + n00O.width_a = 10, + n00O.width_b = 10, + n00O.width_o = 10; + oper_add n0lO ( - .a({{3{nlOili}}, nlOiiO, nlOiil, nlOiii, nlOi0O, nlOi0l, nlOi0i, nlOi1O, nlOi1l, nlOi1i, nlO0OO, nlO0Ol, 1'b1}), - .b({{6{1'b1}}, {8{1'b0}}, 1'b1}), + .a({1'b0, ni0ll, ni0li, ni0iO, ni0il, ni0ii}), + .b({1'b0, nii1O, nii1l, nii1i, ni0OO, ni0Ol}), .cin(1'b0), .cout(), - .o(wire_niOil_o)); + .o(wire_n0lO_o)); defparam - niOil.sgate_representation = 0, - niOil.width_a = 15, - niOil.width_b = 15, - niOil.width_o = 15; - oper_add niOiO + n0lO.sgate_representation = 0, + n0lO.width_a = 6, + n0lO.width_b = 6, + n0lO.width_o = 6; + oper_add n1il ( - .a({{3{nllii}}, nll0O, nll0l, nll0i, nll1O, nll1l, nll1i, nliOO, nliOl, nliOi, nl01O, nl01l, nl01i, nl1OO, nl1Ol, nl1Oi, nl1lO, nl1ll, nl1li, nl1iO, nl1il, nl1ii, nl10O, nl10l, nl10i, nl11O, nl11l, nl11i, niOOO, niOOl, niOOi, niOlO, niOll, niOli, niOii}), - .b({{12{1'b0}}, nlO00i, {23{1'b0}}, 1'b1}), + .a({{3{niliO}}, nilil, nilii, nil0O, nil0l, nil0i, nil1O, nil1l, nil1i, 1'b1}), + .b({{6{1'b1}}, {5{1'b0}}, 1'b1}), .cin(1'b0), .cout(), - .o(wire_niOiO_o)); + .o(wire_n1il_o)); defparam - niOiO.sgate_representation = 0, - niOiO.width_a = 37, - niOiO.width_b = 37, - niOiO.width_o = 37; - oper_add nlliO + n1il.sgate_representation = 0, + n1il.width_a = 12, + n1il.width_b = 12, + n1il.width_o = 12; + oper_add n1iO ( - .a({{3{1'b0}}, nlO0Oi, nlO0lO, nlO0ll, nlO0li, nlO0iO, nlO0il, nlO0ii, nlO00O, nlO00l, 1'b1}), - .b({{5{1'b1}}, {7{1'b0}}, 1'b1}), + .a({{2{wire_n00O_o[8]}}, wire_n00O_o[8:1], wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout, wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout, wire_n1ll_dataout, wire_n1li_dataout}), + .b({{9{1'b0}}, nili, {10{1'b0}}, 1'b1}), .cin(1'b0), .cout(), - .o(wire_nlliO_o)); + .o(wire_n1iO_o)); defparam - nlliO.sgate_representation = 0, - nlliO.width_a = 13, - nlliO.width_b = 13, - nlliO.width_o = 13; - oper_add nlO1O + n1iO.sgate_representation = 0, + n1iO.width_a = 21, + n1iO.width_b = 21, + n1iO.width_o = 21; + oper_add nlOll ( - .a({1'b0, a[30:23]}), - .b({1'b0, b[30:23]}), + .a({{3{(~ niliO)}}, (~ nilil), (~ nilii), (~ nil0O), (~ nil0l), (~ nil0i), (~ nil1O), (~ nil1l), (~ nil1i), 1'b1}), + .b({{11{1'b0}}, 1'b1}), .cin(1'b0), .cout(), - .o(wire_nlO1O_o)); + .o(wire_nlOll_o)); defparam - nlO1O.sgate_representation = 0, - nlO1O.width_a = 9, - nlO1O.width_b = 9, - nlO1O.width_o = 9; + nlOll.sgate_representation = 0, + nlOll.width_a = 12, + nlOll.width_b = 12, + nlOll.width_o = 12; oper_mult n0i ( - .a({n1O, n1i, nlOO, nlOl, nlOi, nllO, nlll, nlli, nliO, nlil, nlii, nl0O, nl0l, nl0i, nl1O, nl1l, nl1i, niOO, niOl, niOi, nilO, nill, nili, niiO}), - .b({niil, niii, ni0O, ni0l, ni0i, ni1O, ni1l, ni1i, n0OO, n0Ol, n0Oi, n0lO, n0ll, n0li, n0iO, n0il, n0ii, n00O, n00l, n00i, n01O, n01l, n01i, n1OO}), + .a({n1O, n1i, nlOO, nlOl, nlOi, nllO, nlll, nlli, nliO, nlil, nlii}), + .b({nl0O, nl0l, nl0i, nl1O, nl1l, nl1i, niOO, niOl, niOi, nilO, nill}), .o(wire_n0i_o)); defparam n0i.sgate_representation = 0, - n0i.width_a = 24, - n0i.width_b = 24, - n0i.width_o = 48; - oper_mux ni00i - ( - .data({{2{1'b0}}, nlOOll, 1'b0}), - .o(wire_ni00i_o), - .sel({niilO, niliO})); - defparam - ni00i.width_data = 4, - ni00i.width_sel = 2; - oper_mux ni00l - ( - .data({{2{1'b0}}, nlOOlO, 1'b0}), - .o(wire_ni00l_o), - .sel({niilO, niliO})); - defparam - ni00l.width_data = 4, - ni00l.width_sel = 2; - oper_mux ni00O - ( - .data({{2{1'b0}}, nlOOOi, 1'b0}), - .o(wire_ni00O_o), - .sel({niilO, niliO})); - defparam - ni00O.width_data = 4, - ni00O.width_sel = 2; - oper_mux ni01i - ( - .data({{2{1'b0}}, nlOOil, 1'b0}), - .o(wire_ni01i_o), - .sel({niilO, niliO})); - defparam - ni01i.width_data = 4, - ni01i.width_sel = 2; - oper_mux ni01l - ( - .data({{2{1'b0}}, nlOOiO, 1'b0}), - .o(wire_ni01l_o), - .sel({niilO, niliO})); - defparam - ni01l.width_data = 4, - ni01l.width_sel = 2; - oper_mux ni01O - ( - .data({{2{1'b0}}, nlOOli, 1'b0}), - .o(wire_ni01O_o), - .sel({niilO, niliO})); - defparam - ni01O.width_data = 4, - ni01O.width_sel = 2; - oper_mux ni0ii - ( - .data({{2{1'b0}}, nlOOOl, 1'b0}), - .o(wire_ni0ii_o), - .sel({niilO, niliO})); - defparam - ni0ii.width_data = 4, - ni0ii.width_sel = 2; - oper_mux ni0il - ( - .data({{2{1'b0}}, nlOOOO, 1'b0}), - .o(wire_ni0il_o), - .sel({niilO, niliO})); - defparam - ni0il.width_data = 4, - ni0il.width_sel = 2; - oper_mux ni0iO - ( - .data({{2{1'b0}}, n111i, 1'b0}), - .o(wire_ni0iO_o), - .sel({niilO, niliO})); - defparam - ni0iO.width_data = 4, - ni0iO.width_sel = 2; - oper_mux ni0li - ( - .data({{2{1'b0}}, n111l, 1'b0}), - .o(wire_ni0li_o), - .sel({niilO, niliO})); - defparam - ni0li.width_data = 4, - ni0li.width_sel = 2; - oper_mux ni0ll - ( - .data({{2{1'b0}}, n111O, 1'b0}), - .o(wire_ni0ll_o), - .sel({niilO, niliO})); - defparam - ni0ll.width_data = 4, - ni0ll.width_sel = 2; - oper_mux ni0lO - ( - .data({{2{1'b0}}, n110i, 1'b0}), - .o(wire_ni0lO_o), - .sel({niilO, niliO})); - defparam - ni0lO.width_data = 4, - ni0lO.width_sel = 2; - oper_mux ni0Oi - ( - .data({{2{1'b0}}, n110l, 1'b0}), - .o(wire_ni0Oi_o), - .sel({niilO, niliO})); - defparam - ni0Oi.width_data = 4, - ni0Oi.width_sel = 2; - oper_mux ni0Ol - ( - .data({{2{1'b0}}, n110O, 1'b0}), - .o(wire_ni0Ol_o), - .sel({niilO, niliO})); - defparam - ni0Ol.width_data = 4, - ni0Ol.width_sel = 2; - oper_mux ni0OO - ( - .data({{2{1'b0}}, n11ii, 1'b0}), - .o(wire_ni0OO_o), - .sel({niilO, niliO})); - defparam - ni0OO.width_data = 4, - ni0OO.width_sel = 2; - oper_mux ni1ll - ( - .data({1'b1, 1'b0, nlOO1O, 1'b0}), - .o(wire_ni1ll_o), - .sel({niilO, niliO})); - defparam - ni1ll.width_data = 4, - ni1ll.width_sel = 2; - oper_mux ni1lO + n0i.width_a = 11, + n0i.width_b = 11, + n0i.width_o = 22; + oper_mux nll0i ( - .data({{2{1'b0}}, nlOO0i, 1'b0}), - .o(wire_ni1lO_o), - .sel({niilO, niliO})); + .data({{2{1'b0}}, nillO, 1'b0}), + .o(wire_nll0i_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - ni1lO.width_data = 4, - ni1lO.width_sel = 2; - oper_mux ni1Oi + nll0i.width_data = 4, + nll0i.width_sel = 2; + oper_mux nll0l ( - .data({{2{1'b0}}, nlOO0l, 1'b0}), - .o(wire_ni1Oi_o), - .sel({niilO, niliO})); + .data({{2{1'b0}}, nilOi, 1'b0}), + .o(wire_nll0l_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - ni1Oi.width_data = 4, - ni1Oi.width_sel = 2; - oper_mux ni1Ol + nll0l.width_data = 4, + nll0l.width_sel = 2; + oper_mux nll0O ( - .data({{2{1'b0}}, nlOO0O, 1'b0}), - .o(wire_ni1Ol_o), - .sel({niilO, niliO})); + .data({{2{1'b0}}, nilOl, 1'b0}), + .o(wire_nll0O_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - ni1Ol.width_data = 4, - ni1Ol.width_sel = 2; - oper_mux ni1OO + nll0O.width_data = 4, + nll0O.width_sel = 2; + oper_mux nll1l ( - .data({{2{1'b0}}, nlOOii, 1'b0}), - .o(wire_ni1OO_o), - .sel({niilO, niliO})); + .data({1'b1, 1'b0, nilli, 1'b0}), + .o(wire_nll1l_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - ni1OO.width_data = 4, - ni1OO.width_sel = 2; - oper_mux nii0i + nll1l.width_data = 4, + nll1l.width_sel = 2; + oper_mux nll1O ( - .data({{2{1'b1}}, nlOill, 1'b0}), - .o(wire_nii0i_o), - .sel({niilO, niliO})); + .data({{2{1'b0}}, nilll, 1'b0}), + .o(wire_nll1O_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - nii0i.width_data = 4, - nii0i.width_sel = 2; - oper_mux nii0l + nll1O.width_data = 4, + nll1O.width_sel = 2; + oper_mux nllii ( - .data({{2{1'b1}}, nlOilO, 1'b0}), - .o(wire_nii0l_o), - .sel({niilO, niliO})); + .data({{2{1'b0}}, nilOO, 1'b0}), + .o(wire_nllii_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - nii0l.width_data = 4, - nii0l.width_sel = 2; - oper_mux nii0O + nllii.width_data = 4, + nllii.width_sel = 2; + oper_mux nllil ( - .data({{2{1'b1}}, nlOiOi, 1'b0}), - .o(wire_nii0O_o), - .sel({niilO, niliO})); + .data({{2{1'b0}}, niO1i, 1'b0}), + .o(wire_nllil_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - nii0O.width_data = 4, - nii0O.width_sel = 2; - oper_mux nii1i + nllil.width_data = 4, + nllil.width_sel = 2; + oper_mux nlliO ( - .data({{2{1'b0}}, n11il, 1'b0}), - .o(wire_nii1i_o), - .sel({niilO, niliO})); + .data({{2{1'b0}}, niO1l, 1'b0}), + .o(wire_nlliO_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - nii1i.width_data = 4, - nii1i.width_sel = 2; - oper_mux nii1l + nlliO.width_data = 4, + nlliO.width_sel = 2; + oper_mux nllli ( - .data({{2{1'b0}}, n11iO, 1'b0}), - .o(wire_nii1l_o), - .sel({niilO, niliO})); + .data({{2{1'b0}}, niO1O, 1'b0}), + .o(wire_nllli_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - nii1l.width_data = 4, - nii1l.width_sel = 2; - oper_mux nii1O + nllli.width_data = 4, + nllli.width_sel = 2; + oper_mux nllll ( - .data({{2{1'b0}}, n11li, 1'b0}), - .o(wire_nii1O_o), - .sel({niilO, niliO})); + .data({{2{1'b0}}, niO0i, 1'b0}), + .o(wire_nllll_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - nii1O.width_data = 4, - nii1O.width_sel = 2; - oper_mux niiii + nllll.width_data = 4, + nllll.width_sel = 2; + oper_mux nlllO ( - .data({{2{1'b1}}, nlOiOl, 1'b0}), - .o(wire_niiii_o), - .sel({niilO, niliO})); + .data({{2{1'b1}}, nil1i, 1'b0}), + .o(wire_nlllO_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - niiii.width_data = 4, - niiii.width_sel = 2; - oper_mux niiil + nlllO.width_data = 4, + nlllO.width_sel = 2; + oper_mux nllOi ( - .data({{2{1'b1}}, nlOiOO, 1'b0}), - .o(wire_niiil_o), - .sel({niilO, niliO})); + .data({{2{1'b1}}, nil1l, 1'b0}), + .o(wire_nllOi_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - niiil.width_data = 4, - niiil.width_sel = 2; - oper_mux niiiO + nllOi.width_data = 4, + nllOi.width_sel = 2; + oper_mux nllOl ( - .data({{2{1'b1}}, nlOl1i, 1'b0}), - .o(wire_niiiO_o), - .sel({niilO, niliO})); + .data({{2{1'b1}}, nil1O, 1'b0}), + .o(wire_nllOl_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - niiiO.width_data = 4, - niiiO.width_sel = 2; - oper_mux niili + nllOl.width_data = 4, + nllOl.width_sel = 2; + oper_mux nllOO ( - .data({{2{1'b1}}, nlOl1l, 1'b0}), - .o(wire_niili_o), - .sel({niilO, niliO})); + .data({{2{1'b1}}, nil0i, 1'b0}), + .o(wire_nllOO_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - niili.width_data = 4, - niili.width_sel = 2; - oper_mux niill + nllOO.width_data = 4, + nllOO.width_sel = 2; + oper_mux nlO1i ( - .data({{2{1'b1}}, nlOl1O, 1'b0}), - .o(wire_niill_o), - .sel({niilO, niliO})); + .data({{2{1'b1}}, nil0l, 1'b0}), + .o(wire_nlO1i_o), + .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam - niill.width_data = 4, - niill.width_sel = 2; - oper_mux niiOl + nlO1i.width_data = 4, + nlO1i.width_sel = 2; + oper_mux nlO1l ( .data({{3{1'b0}}, 1'b1}), - .o(wire_niiOl_o), - .sel({nlllll, nlllli})); + .o(wire_nlO1l_o), + .sel({ni1iO, ni1il})); defparam - niiOl.width_data = 4, - niiOl.width_sel = 2; - oper_mux niiOO + nlO1l.width_data = 4, + nlO1l.width_sel = 2; + oper_mux nlO1O ( .data({{3{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}}), - .o(wire_niiOO_o), - .sel({nlO1lO, nlllll, nlllli})); + .o(wire_nlO1O_o), + .sel({ni1Ol, ni1iO, ni1il})); defparam - niiOO.width_data = 8, - niiOO.width_sel = 3; + nlO1O.width_data = 8, + nlO1O.width_sel = 3; assign - nlll0i = ((((((((~ a[23]) & (~ a[24])) & (~ a[25])) & (~ a[26])) & (~ a[27])) & (~ a[28])) & (~ a[29])) & (~ a[30])), - nlll0l = (((((((b[23] & b[24]) & b[25]) & b[26]) & b[27]) & b[28]) & b[29]) & b[30]), - nlll0O = (((((((((((((((((((((((~ b[0]) & (~ b[1])) & (~ b[2])) & (~ b[3])) & (~ b[4])) & (~ b[5])) & (~ b[6])) & (~ b[7])) & (~ b[8])) & (~ b[9])) & (~ b[10])) & (~ b[11])) & (~ b[12])) & (~ b[13])) & (~ b[14])) & (~ b[15])) & (~ b[16])) & (~ b[17])) & (~ b[18])) & (~ b[19])) & (~ b[20])) & (~ b[21])) & (~ b[22])), - nlllii = ((((((((~ b[23]) & (~ b[24])) & (~ b[25])) & (~ b[26])) & (~ b[27])) & (~ b[28])) & (~ b[29])) & (~ b[30])), - nlllil = (((((((a[23] & a[24]) & a[25]) & a[26]) & a[27]) & a[28]) & a[29]) & a[30]), - nllliO = (((((((((((((((((((((((~ a[0]) & (~ a[1])) & (~ a[2])) & (~ a[3])) & (~ a[4])) & (~ a[5])) & (~ a[6])) & (~ a[7])) & (~ a[8])) & (~ a[9])) & (~ a[10])) & (~ a[11])) & (~ a[12])) & (~ a[13])) & (~ a[14])) & (~ a[15])) & (~ a[16])) & (~ a[17])) & (~ a[18])) & (~ a[19])) & (~ a[20])) & (~ a[21])) & (~ a[22])), - nlllli = ((nllllO & (~ niiOi)) | ((nlOlOi & nlOO1i) | ((nlOllO & nlOO1l) | (nlOO1i & nlOO1l)))), - nlllll = ((nllllO & (~ nilli)) | ((nlOllO & nlOlOl) | ((nlOlOi & nlOlOO) | (nlOlOl & nlOlOO)))), - nllllO = (nlOllO & nlOlOi), - nlllOl = 1'b1, - q = {nlO01O, wire_niill_o, wire_niili_o, wire_niiiO_o, wire_niiil_o, wire_niiii_o, wire_nii0O_o, wire_nii0l_o, wire_nii0i_o, wire_nii1O_o, wire_nii1l_o, wire_nii1i_o, wire_ni0OO_o, wire_ni0Ol_o, wire_ni0Oi_o, wire_ni0lO_o, wire_ni0ll_o, wire_ni0li_o, wire_ni0iO_o, wire_ni0il_o, wire_ni0ii_o, wire_ni00O_o, wire_ni00l_o, wire_ni00i_o, wire_ni01O_o, wire_ni01l_o, wire_ni01i_o, wire_ni1OO_o, wire_ni1Ol_o, wire_ni1Oi_o, wire_ni1lO_o, wire_ni1ll_o}; + ni01i = (ni00l & ni0Oi), + ni10i = ((((((((((~ b[0]) & (~ b[1])) & (~ b[2])) & (~ b[3])) & (~ b[4])) & (~ b[5])) & (~ b[6])) & (~ b[7])) & (~ b[8])) & (~ b[9])), + ni10l = (((((~ nii1O) & (~ nii1l)) & (~ nii1i)) & (~ ni0OO)) & (~ ni0Ol)), + ni10O = ((((ni0ll & ni0li) & ni0iO) & ni0il) & ni0ii), + ni11l = (((((~ ni0ll) & (~ ni0li)) & (~ ni0iO)) & (~ ni0il)) & (~ ni0ii)), + ni11O = ((((nii1O & nii1l) & nii1i) & ni0OO) & ni0Ol), + ni1ii = ((((((((((~ a[0]) & (~ a[1])) & (~ a[2])) & (~ a[3])) & (~ a[4])) & (~ a[5])) & (~ a[6])) & (~ a[7])) & (~ a[8])) & (~ a[9])), + ni1il = ((ni1li & (~ wire_nlOll_o[11])) | ((ni1ll & nii0l) | ((ni1lO & niilO) | (nii0l & niilO)))), + ni1iO = (((~ wire_n1il_o[11]) & ni1li) | ((ni01i & ni1lO) | ((ni1OO & ni1ll) | (ni01i & ni1OO)))), + ni1li = (ni1lO & ni1ll), + ni1ll = ((~ ni0Oi) & (~ niilO)), + ni1lO = ((~ nii0l) & (~ niili)), + ni1Oi = 1'b1, + ni1Ol = (((ni01i & nii0l) | (ni1OO & niilO)) | (((~ niiii) & niili) | ((~ ni00l) & ni0Oi))), + ni1OO = (niiii & niili), + q = {((~ ni1Ol) & niiOl), wire_nlO1i_o, wire_nllOO_o, wire_nllOl_o, wire_nllOi_o, wire_nlllO_o, wire_nllll_o, wire_nllli_o, wire_nlliO_o, wire_nllil_o, wire_nllii_o, wire_nll0O_o, wire_nll0l_o, wire_nll0i_o, wire_nll1O_o, wire_nll1l_o}; endmodule //ip_fp_mul //synopsys translate_on //VALID FILE diff --git a/ip/ip_fp_mul_sim/mentor/msim_setup.tcl b/ip/ip_fp_mul_sim/mentor/msim_setup.tcl index 490a369..14c829b 100644 --- a/ip/ip_fp_mul_sim/mentor/msim_setup.tcl +++ b/ip/ip_fp_mul_sim/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.04:56:13 +# ACDS 20.1 720 linux 2023.10.21.20:27:56 # ---------------------------------------- # Initialize variables diff --git a/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh b/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh index 05b6a3c..6bf2ad9 100755 --- a/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh +++ b/ip/ip_fp_mul_sim/synopsys/vcs/vcs_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.04:56:13 +# ACDS 20.1 720 linux 2023.10.21.20:27:56 # ---------------------------------------- # vcs - auto-generated simulation script @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.04:56:13 +# ACDS 20.1 720 linux 2023.10.21.20:27:56 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="ip_fp_mul" diff --git a/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh b/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh index 6dbe5b1..8f56686 100755 --- a/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh +++ b/ip/ip_fp_mul_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 20.1 720 linux 2023.10.21.04:56:13 +# ACDS 20.1 720 linux 2023.10.21.20:27:56 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,7 +107,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.04:56:13 +# ACDS 20.1 720 linux 2023.10.21.20:27:56 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="ip_fp_mul" diff --git a/rtl/gfx/fp_add.sv b/rtl/gfx/fp_add.sv index 7f7e2c6..6cf4874 100644 --- a/rtl/gfx/fp_add.sv +++ b/rtl/gfx/fp_add.sv @@ -21,6 +21,7 @@ module fp_add `ifndef VERILATOR ip_fp_add ip_add ( + .en(1), .areset(0), .* ); diff --git a/rtl/gfx/fp_mul.sv b/rtl/gfx/fp_mul.sv index c2f4e2a..c5aa56a 100644 --- a/rtl/gfx/fp_mul.sv +++ b/rtl/gfx/fp_mul.sv @@ -21,6 +21,7 @@ module fp_mul `ifndef VERILATOR ip_fp_mul ip_mul ( + .en(1), .areset(0), .* ); diff --git a/rtl/gfx/gfx.sv b/rtl/gfx/gfx.sv index ab2bcce..ec2fb13 100644 --- a/rtl/gfx/gfx.sv +++ b/rtl/gfx/gfx.sv @@ -12,10 +12,13 @@ module gfx output logic[31:0] cmd_readdata ); + fp readdata, writedata; mat4 a, b, q, hold_q; logic start, done; - assign cmd_readdata = hold_q[cmd_address[3:2]][cmd_address[1:0]]; + assign readdata = hold_q[cmd_address[3:2]][cmd_address[1:0]]; + assign writedata = cmd_writedata[`FLOAT_BITS - 1:0]; + assign cmd_readdata = {{($bits(cmd_readdata) - `FLOAT_BITS){1'b0}}, readdata}; mat_mat_mul mul ( @@ -25,9 +28,9 @@ module gfx always_ff @(posedge clk) begin if (cmd_write) begin if (cmd_address[4]) - a[cmd_address[3:2]][cmd_address[1:0]] <= cmd_writedata; + a[cmd_address[3:2]][cmd_address[1:0]] <= writedata; else - b[cmd_address[3:2]][cmd_address[1:0]] <= cmd_writedata; + b[cmd_address[3:2]][cmd_address[1:0]] <= writedata; end if (done) diff --git a/rtl/gfx/gfx_defs.sv b/rtl/gfx/gfx_defs.sv index e52f243..d01822a 100644 --- a/rtl/gfx/gfx_defs.sv +++ b/rtl/gfx/gfx_defs.sv @@ -1,14 +1,16 @@ `ifndef GFX_DEFS_SV `define GFX_DEFS_SV -`define FP_ADD_STAGES 13 -`define FP_MUL_STAGES 6 - +`define FLOAT_BITS 16 `define FLOATS_PER_VEC 4 `define VECS_PER_MAT 4 -typedef logic[31:0] fp; -typedef fp vec4[`FLOATS_PER_VEC]; -typedef vec4 mat4[`VECS_PER_MAT]; +// Target de 100MHz con float16, rounding aproximado +`define FP_ADD_STAGES 4 // ~325 LUTs +`define FP_MUL_STAGES 3 // ~119 LUTs ~1 bloque DSP + +typedef logic[`FLOAT_BITS - 1:0] fp; +typedef fp vec4[`FLOATS_PER_VEC]; +typedef vec4 mat4[`VECS_PER_MAT]; `endif |