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authorAlejandro Soto <alejandro@34project.org>2022-12-20 16:16:08 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-21 04:16:46 -0600
commitd2fc80b6d8b4a64efa00c8458ae94f6b44ddf6be (patch)
tree8f9b3b81b36cb3b4deda5eebfd0de2ddc4f7e0ed /tb
parent42bbf5619d9ec4437abf8277d5a458257c3076f0 (diff)
Fix clock/reset timing in single-step, dsp_mul
Diffstat (limited to 'tb')
-rw-r--r--tb/dsp_mul.sv4
1 files changed, 2 insertions, 2 deletions
diff --git a/tb/dsp_mul.sv b/tb/dsp_mul.sv
index d6fcb6a..a46518c 100644
--- a/tb/dsp_mul.sv
+++ b/tb/dsp_mul.sv
@@ -26,8 +26,8 @@ module dsp_mul
2'b11: product = $signed(ext_a) * $signed(ext_b);
endcase
- always @(posedge clock0 or negedge aclr0)
- if(!aclr0) begin
+ always @(posedge clock0 or posedge aclr0)
+ if(aclr0) begin
result <= {64{1'bx}};
hold_a <= {32{1'bx}};
hold_b <= {32{1'bx}};