From d2fc80b6d8b4a64efa00c8458ae94f6b44ddf6be Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Tue, 20 Dec 2022 16:16:08 -0600
Subject: Fix clock/reset timing in single-step, dsp_mul

---
 tb/dsp_mul.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tb')

diff --git a/tb/dsp_mul.sv b/tb/dsp_mul.sv
index d6fcb6a..a46518c 100644
--- a/tb/dsp_mul.sv
+++ b/tb/dsp_mul.sv
@@ -26,8 +26,8 @@ module dsp_mul
 			2'b11: product = $signed(ext_a) * $signed(ext_b);
 		endcase
 
-	always @(posedge clock0 or negedge aclr0)
-		if(!aclr0) begin
+	always @(posedge clock0 or posedge aclr0)
+		if(aclr0) begin
 			result <= {64{1'bx}};
 			hold_a <= {32{1'bx}};
 			hold_b <= {32{1'bx}};
-- 
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