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| author | Alejandro Soto <alejandro@34project.org> | 2022-11-14 21:10:40 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-14 21:10:40 -0600 |
| commit | 6fb3849e73b797d4610a2b782127f927dec0c9c9 (patch) | |
| tree | 9d17de8907d860b795761e0644f17d0fd33106de /tb/sim | |
| parent | cad870295dfb741d5c24c25016c5bba878bc37e5 (diff) | |
Implement VGA simulation
Diffstat (limited to 'tb/sim')
| -rwxr-xr-x | tb/sim/sim.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tb/sim/sim.py b/tb/sim/sim.py index bef1b73..0c8b023 100755 --- a/tb/sim/sim.py +++ b/tb/sim/sim.py @@ -249,7 +249,7 @@ mem_dumps = module_get('mem_dumps', []) if init := module_get('init'): init() -exec_args = [verilated, '--cycles', str(cycles), '--dump-regs'] +exec_args = [verilated, '--headless', '--cycles', str(cycles), '--dump-regs'] for rng in mem_dumps: length = rng.stop - rng.start |