From 6fb3849e73b797d4610a2b782127f927dec0c9c9 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 14 Nov 2022 21:10:40 -0600 Subject: Implement VGA simulation --- tb/sim/sim.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tb/sim') diff --git a/tb/sim/sim.py b/tb/sim/sim.py index bef1b73..0c8b023 100755 --- a/tb/sim/sim.py +++ b/tb/sim/sim.py @@ -249,7 +249,7 @@ mem_dumps = module_get('mem_dumps', []) if init := module_get('init'): init() -exec_args = [verilated, '--cycles', str(cycles), '--dump-regs'] +exec_args = [verilated, '--headless', '--cycles', str(cycles), '--dump-regs'] for rng in mem_dumps: length = rng.stop - rng.start -- cgit v1.2.3