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| author | Alejandro Soto <alejandro@34project.org> | 2022-12-07 20:59:22 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-07 20:59:22 -0600 |
| commit | d6fff0eb1ce867192d30babb839fc09c30049f0b (patch) | |
| tree | 9d3b5fab4ccaae51d8f5b44a2b5610507b13638e /tb/sim | |
| parent | d8d687ad8052809f66c0b5a36d4ca74d0a3b202c (diff) | |
Fix register-indirect shifts
Diffstat (limited to '')
| -rw-r--r-- | tb/sim/shifts.S | 3 | ||||
| -rw-r--r-- | tb/sim/shifts.py | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/tb/sim/shifts.S b/tb/sim/shifts.S index 68ef3f8..6209157 100644 --- a/tb/sim/shifts.S +++ b/tb/sim/shifts.S @@ -14,4 +14,7 @@ reset: # tmp = 0 # r2 = r0 = 00015000 eor r2, r0, r2, asr #7 + ldr r4, =(512 << 20) + ldr r5, =#60 + lsr r4, r4, r5 mov pc, lr diff --git a/tb/sim/shifts.py b/tb/sim/shifts.py index 38f24a2..9923124 100644 --- a/tb/sim/shifts.py +++ b/tb/sim/shifts.py @@ -2,3 +2,4 @@ def final(): assert_reg(r0, 0x00015000) assert_reg(r2, 0x00015000) assert_reg(r3, 0xaaa9fd55) + assert_reg(r4, 0) |