From d6fff0eb1ce867192d30babb839fc09c30049f0b Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 7 Dec 2022 20:59:22 -0600 Subject: Fix register-indirect shifts --- tb/sim/shifts.S | 3 +++ tb/sim/shifts.py | 1 + 2 files changed, 4 insertions(+) (limited to 'tb/sim') diff --git a/tb/sim/shifts.S b/tb/sim/shifts.S index 68ef3f8..6209157 100644 --- a/tb/sim/shifts.S +++ b/tb/sim/shifts.S @@ -14,4 +14,7 @@ reset: # tmp = 0 # r2 = r0 = 00015000 eor r2, r0, r2, asr #7 + ldr r4, =(512 << 20) + ldr r5, =#60 + lsr r4, r4, r5 mov pc, lr diff --git a/tb/sim/shifts.py b/tb/sim/shifts.py index 38f24a2..9923124 100644 --- a/tb/sim/shifts.py +++ b/tb/sim/shifts.py @@ -2,3 +2,4 @@ def final(): assert_reg(r0, 0x00015000) assert_reg(r2, 0x00015000) assert_reg(r3, 0xaaa9fd55) + assert_reg(r4, 0) -- cgit v1.2.3