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authorAlejandro Soto <alejandro@34project.org>2024-05-18 17:48:27 -0600
committerAlejandro Soto <alejandro@34project.org>2024-05-24 05:58:41 -0600
commit40bd702015f3a09f5c4d1ad30439b1ea186d7484 (patch)
tree69cd56673073604e4c39b15c8b823325f65b169a /target/w3d_de1soc/intc.sv
parent8f3163b78f75a0080c9c031617045ca19f1f6e97 (diff)
target/w3d_de1soc: initial commit
Diffstat (limited to 'target/w3d_de1soc/intc.sv')
-rw-r--r--target/w3d_de1soc/intc.sv30
1 files changed, 30 insertions, 0 deletions
diff --git a/target/w3d_de1soc/intc.sv b/target/w3d_de1soc/intc.sv
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+++ b/target/w3d_de1soc/intc.sv
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+module intc
+(
+ input logic clk,
+ rst_n,
+
+ input logic irq_timer,
+ irq_jtaguart,
+
+ input logic avl_address,
+ avl_read,
+ avl_write,
+ input logic[31:0] avl_writedata,
+
+ output logic avl_irq,
+ output logic[31:0] avl_readdata
+);
+
+ logic[31:0] status, mask;
+
+ assign status = {30'b0, irq_jtaguart, irq_timer} & mask;
+ assign avl_irq = |status;
+ assign avl_readdata = avl_address ? mask : status;
+
+ always @(posedge clk or negedge rst_n)
+ if(!rst_n)
+ mask <= 0;
+ else if(avl_write && avl_address)
+ mask <= avl_writedata;
+
+endmodule