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authorAlejandro Soto <alejandro@34project.org>2022-12-10 19:18:21 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-16 16:27:19 -0600
commit6fee344b754464b1fd17f7c0429e6597e51dc74d (patch)
treea31913d054bbf83772fa29e256be750092256d8f /sim/sim.py
parent6b163a88179ac3073d22622be4991f332529c8bd (diff)
Implement hardware virtual memory
Diffstat (limited to '')
-rwxr-xr-xsim/sim.py13
1 files changed, 10 insertions, 3 deletions
diff --git a/sim/sim.py b/sim/sim.py
index 491ac43..b4e0882 100755
--- a/sim/sim.py
+++ b/sim/sim.py
@@ -85,10 +85,14 @@ def recv_mem_dump():
elif line == '=== end-mem ===':
break
- base, data = line.split()
- dumped.append((int(base, 16) << 2, bytes.fromhex(data)))
+ try:
+ base, data = line.split()
+ dumped.append((int(base, 16) << 2, bytes.fromhex(data)))
+ except ValueError:
+ while_running()
+ print(f'{COLOR_BLUE}{line}{COLOR_RESET}')
-def read_mem(base, length):
+def read_mem(base, length, *, may_fail = False):
fragments = []
i = 0
@@ -97,6 +101,9 @@ def read_mem(base, length):
recv_mem_dump()
while length > 0:
+ if i >= len(dumped) and may_fail:
+ return None
+
assert i < len(dumped), f'memory at 0x{base:08x} not dumped'
start, data = dumped[i]
delta = base - start