From 6fee344b754464b1fd17f7c0429e6597e51dc74d Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 10 Dec 2022 19:18:21 -0600 Subject: Implement hardware virtual memory --- sim/sim.py | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'sim/sim.py') diff --git a/sim/sim.py b/sim/sim.py index 491ac43..b4e0882 100755 --- a/sim/sim.py +++ b/sim/sim.py @@ -85,10 +85,14 @@ def recv_mem_dump(): elif line == '=== end-mem ===': break - base, data = line.split() - dumped.append((int(base, 16) << 2, bytes.fromhex(data))) + try: + base, data = line.split() + dumped.append((int(base, 16) << 2, bytes.fromhex(data))) + except ValueError: + while_running() + print(f'{COLOR_BLUE}{line}{COLOR_RESET}') -def read_mem(base, length): +def read_mem(base, length, *, may_fail = False): fragments = [] i = 0 @@ -97,6 +101,9 @@ def read_mem(base, length): recv_mem_dump() while length > 0: + if i >= len(dumped) and may_fail: + return None + assert i < len(dumped), f'memory at 0x{base:08x} not dumped' start, data = dumped[i] delta = base - start -- cgit v1.2.3