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authorAlejandro Soto <alejandro@34project.org>2024-05-23 20:12:02 -0600
committerAlejandro Soto <alejandro@34project.org>2024-05-24 05:58:44 -0600
commita1ec7165962d86794b4d1939b1e6096e068cf854 (patch)
tree6a8770236152cdbb62f6d68f51dfdd4527ea481b /rtl
parent2008c2d4b4a7b4d1373d0b04db8ef775bb4b68ab (diff)
rtl/gfx: fix double AXI ready response in scheduler
Diffstat (limited to 'rtl')
-rw-r--r--rtl/gfx/gfx_sched.sv4
-rw-r--r--rtl/picorv32/picorv32.v2
2 files changed, 3 insertions, 3 deletions
diff --git a/rtl/gfx/gfx_sched.sv b/rtl/gfx/gfx_sched.sv
index dd6ca91..ce26c9d 100644
--- a/rtl/gfx/gfx_sched.sv
+++ b/rtl/gfx/gfx_sched.sv
@@ -10,8 +10,6 @@ import gfx::*;
input irq_lines irq
);
- // verilator tracing_off
-
logic axi_ready, axi_valid, bram_ready, bram_read, bram_write, bram_write_next,
mem_instr, mem_la_read, mem_la_write, mem_ready, mem_valid, select_bram;
@@ -132,7 +130,7 @@ import gfx::*;
bram_ready <= 0;
bram_write <= 0;
end else begin
- axi_valid <= ~select_bram | (axi_valid & ~axi_ready);
+ axi_valid <= ~select_bram | (mem_valid & axi_valid & ~axi_ready);
bram_read <= mem_la_read & select_bram;
bram_write <= bram_write_next;
bram_ready <= bram_read | bram_write_next;
diff --git a/rtl/picorv32/picorv32.v b/rtl/picorv32/picorv32.v
index e4ef08a..58d4ac9 100644
--- a/rtl/picorv32/picorv32.v
+++ b/rtl/picorv32/picorv32.v
@@ -158,6 +158,8 @@ module picorv32 #(
output reg trace_valid,
output reg [35:0] trace_data
);
+ // verilator tracing_off
+
localparam integer irq_timer = 0;
localparam integer irq_ebreak = 1;
localparam integer irq_buserror = 2;