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authorAlejandro Soto <alejandro@34project.org>2024-02-13 12:14:31 -0600
committerAlejandro Soto <alejandro@34project.org>2024-02-20 11:11:18 -0600
commit827c40829903d5b870f47ab2f389792ed10211bd (patch)
tree2a696fcb41118e8115585a9e2d79ec60294a6584 /rtl
parent9bf55b70a85e5c12e9cfd0b8c7e1eaf1c05a6c1c (diff)
rtl/core/control: don't shift branch history registers inside loops
Diffstat (limited to 'rtl')
-rw-r--r--rtl/core/core_control_issue.sv2
1 files changed, 1 insertions, 1 deletions
diff --git a/rtl/core/core_control_issue.sv b/rtl/core/core_control_issue.sv
index 5bd03e1..606d0b8 100644
--- a/rtl/core/core_control_issue.sv
+++ b/rtl/core/core_control_issue.sv
@@ -68,7 +68,7 @@ module core_control_issue
pc_visible <= next_pc_visible;
`ifdef VERILATOR
- if(insn_pc != pc && insn_pc != pc + 1) begin
+ if(insn_pc != pc && insn_pc != pc + 1 && bh0 != {pc, 2'b00}) begin
bh0 <= {pc, 2'b00};
bh1 <= bh0;
bh2 <= bh1;