diff options
| author | Alejandro Soto <alejandro@34project.org> | 2024-05-16 01:08:04 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-05-24 05:58:19 -0600 |
| commit | b21c321a059e11edeece1c90d97776bb0716d7a0 (patch) | |
| tree | cb7c3e6c2a5f6fd153c3b01d61040a2c901e0ba8 /rtl/wb2axip/migsdram.v | |
| parent | a6c23ba92d0c2cad9862de1cb11c19b4e06fc0e6 (diff) | |
rtl: fix quartus errors: parser, synthesis, fitter
Diffstat (limited to 'rtl/wb2axip/migsdram.v')
| -rw-r--r-- | rtl/wb2axip/migsdram.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/rtl/wb2axip/migsdram.v b/rtl/wb2axip/migsdram.v index c1671c8..d4153c2 100644 --- a/rtl/wb2axip/migsdram.v +++ b/rtl/wb2axip/migsdram.v @@ -42,7 +42,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // }}} module migsdram(i_clk, i_clk_200mhz, o_sys_clk, i_rst, o_sys_reset, // Wishbone components @@ -309,5 +309,5 @@ module migsdram(i_clk, i_clk_200mhz, o_sys_clk, i_rst, o_sys_reset, endmodule `ifndef YOSYS -`default_nettype wire +//`default_nettype wire `endif |