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authorAlejandro Soto <alejandro@34project.org>2024-05-16 01:08:04 -0600
committerAlejandro Soto <alejandro@34project.org>2024-05-24 05:58:19 -0600
commitb21c321a059e11edeece1c90d97776bb0716d7a0 (patch)
treecb7c3e6c2a5f6fd153c3b01d61040a2c901e0ba8 /rtl/wb2axip/axisswitch.v
parenta6c23ba92d0c2cad9862de1cb11c19b4e06fc0e6 (diff)
rtl: fix quartus errors: parser, synthesis, fitter
Diffstat (limited to 'rtl/wb2axip/axisswitch.v')
-rw-r--r--rtl/wb2axip/axisswitch.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/rtl/wb2axip/axisswitch.v b/rtl/wb2axip/axisswitch.v
index bcae4a3..e8b4455 100644
--- a/rtl/wb2axip/axisswitch.v
+++ b/rtl/wb2axip/axisswitch.v
@@ -35,7 +35,7 @@
//
////////////////////////////////////////////////////////////////////////////////
//
-`default_nettype none
+//`default_nettype none
// }}}
module axisswitch #(
// {{{
@@ -44,7 +44,7 @@ module axisswitch #(
// is fixed at a width of 32-bits by Xilinx def'n, and 2) since
// we only ever have a single configuration words.
parameter C_AXI_ADDR_WIDTH = 2,
- localparam C_AXI_DATA_WIDTH = 32,
+ /*local*/parameter C_AXI_DATA_WIDTH = 32,
//
parameter NUM_STREAMS = 4,
parameter C_AXIS_DATA_WIDTH = 32,
@@ -284,7 +284,7 @@ module axisswitch #(
// Place a skidbuffer on every incoming stream input
// {{{
generate for(gk=0; gk<NUM_STREAMS; gk=gk+1)
- begin
+ begin: gkblock
skidbuffer #(
// {{{
.OPT_OUTREG(0),