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authorAlejandro Soto <alejandro@34project.org>2024-05-16 01:08:04 -0600
committerAlejandro Soto <alejandro@34project.org>2024-05-24 05:58:19 -0600
commitb21c321a059e11edeece1c90d97776bb0716d7a0 (patch)
treecb7c3e6c2a5f6fd153c3b01d61040a2c901e0ba8 /rtl/wb2axip/aximwr2wbsp.v
parenta6c23ba92d0c2cad9862de1cb11c19b4e06fc0e6 (diff)
rtl: fix quartus errors: parser, synthesis, fitter
Diffstat (limited to '')
-rw-r--r--rtl/wb2axip/aximwr2wbsp.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/rtl/wb2axip/aximwr2wbsp.v b/rtl/wb2axip/aximwr2wbsp.v
index 074467c..820f004 100644
--- a/rtl/wb2axip/aximwr2wbsp.v
+++ b/rtl/wb2axip/aximwr2wbsp.v
@@ -32,7 +32,7 @@
////////////////////////////////////////////////////////////////////////////////
//
//
-`default_nettype none
+//`default_nettype none
// }}}
module aximwr2wbsp #(
// {{{
@@ -40,8 +40,8 @@ module aximwr2wbsp #(
parameter C_AXI_DATA_WIDTH = 32,
parameter C_AXI_ADDR_WIDTH = 28,
parameter [0:0] OPT_SWAP_ENDIANNESS = 1'b0,
- localparam AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3,
- localparam AW = C_AXI_ADDR_WIDTH-AXI_LSBS,
+ /*local*/parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3,
+ /*local*/parameter AW = C_AXI_ADDR_WIDTH-AXI_LSBS,
parameter LGFIFO = 5
// }}}