diff options
| author | Alejandro Soto <alejandro@34project.org> | 2024-05-16 01:08:04 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-05-24 05:58:19 -0600 |
| commit | b21c321a059e11edeece1c90d97776bb0716d7a0 (patch) | |
| tree | cb7c3e6c2a5f6fd153c3b01d61040a2c901e0ba8 /rtl/wb2axip/aximm2s.v | |
| parent | a6c23ba92d0c2cad9862de1cb11c19b4e06fc0e6 (diff) | |
rtl: fix quartus errors: parser, synthesis, fitter
Diffstat (limited to 'rtl/wb2axip/aximm2s.v')
| -rw-r--r-- | rtl/wb2axip/aximm2s.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/rtl/wb2axip/aximm2s.v b/rtl/wb2axip/aximm2s.v index b4c1056..eae16c8 100644 --- a/rtl/wb2axip/aximm2s.v +++ b/rtl/wb2axip/aximm2s.v @@ -135,7 +135,7 @@ // //////////////////////////////////////////////////////////////////////////////// // -`default_nettype none +//`default_nettype none // }}} module aximm2s #( // {{{ @@ -145,12 +145,12 @@ module aximm2s #( // // We support five 32-bit AXI-lite registers, requiring 5-bits // of AXI-lite addressing - localparam C_AXIL_ADDR_WIDTH = 5, - localparam C_AXIL_DATA_WIDTH = 32, + /*local*/parameter C_AXIL_ADDR_WIDTH = 5, + /*local*/parameter C_AXIL_DATA_WIDTH = 32, // // The bottom ADDRLSB bits of any AXI address are subword bits - localparam ADDRLSB = $clog2(C_AXI_DATA_WIDTH)-3, - localparam AXILLSB = $clog2(C_AXIL_DATA_WIDTH)-3, + /*local*/parameter ADDRLSB = $clog2(C_AXI_DATA_WIDTH)-3, + /*local*/parameter AXILLSB = $clog2(C_AXIL_DATA_WIDTH)-3, // // OPT_UNALIGNED: Allow unaligned accesses, address requests // and sizes which may or may not match the underlying data |