platform: implement SMP controller

2 files changed, 0 insertions, 120 deletions

diff --git a/rtl/mp/mp_ctrl.sv b/rtl/mp/mp_ctrl.sv
deleted file mode 100644
index 362e450..0000000
--- a/rtl/mp/mp_ctrl.sv
+++ /dev/null
@@ -1,73 +0,0 @@
-module mp_ctrl
-(
-	input  logic	   clk,
-	                   rst_n,
-	
-	input  logic       avl_read,
-	                   avl_write,
-	input  logic[31:0] avl_writedata,
-	output logic[31:0] avl_readdata,
-
-	input logic        cpu_halted_0,
-	                   cpu_halted_1,
-	                   cpu_halted_2,
-	                   cpu_halted_3,
-	input logic        breakpoint_0,
-	                   breakpoint_1,
-	                   breakpoint_2,
-	                   breakpoint_3,	
-
-	output logic       halt_0,
-	                   halt_1,
-	                   halt_2,
-	                   halt_3,
-	                   step_0,
-	                   step_1,
-	                   step_2,
-	                   step_3
-);
-
-	logic write;
-	logic[7:0] readdata_3, readdata_2, readdata_1, readdata_0,
-	           writedata_3, writedata_2, writedata_1, writedata_0;
-
-	assign avl_readdata = {readdata_3, readdata_2, readdata_1, readdata_0};
-	assign {writedata_3, writedata_2, writedata_1, writedata_0} = avl_writedata;
-
-	// No hay addresses
-	assign write = avl_write;
-
-	mp_pe pe_1
-	(
-		.step(step_1),
-		.halt(halt_1),
-		.cpu_halted(cpu_halted_1),
-		.breakpoint(breakpoint_1),
-		.readdata(readdata_1),
-		.writedata(writedata_1),
-		.*
-	);
-
-	mp_pe pe_2
-	(
-		.step(step_2),
-		.halt(halt_2),
-		.cpu_halted(cpu_halted_2),
-		.breakpoint(breakpoint_2),
-		.readdata(readdata_2),
-		.writedata(writedata_2),
-		.*
-	);
-
-	mp_pe pe_3
-	(
-		.step(step_3),
-		.halt(halt_3),
-		.cpu_halted(cpu_halted_3),
-		.breakpoint(breakpoint_3),
-		.readdata(readdata_3),
-		.writedata(writedata_3),
-		.*
-	);
-
-endmodule
diff --git a/rtl/mp/pe.sv b/rtl/mp/pe.sv
deleted file mode 100644
index f50ed2f..0000000
--- a/rtl/mp/pe.sv
+++ /dev/null
@@ -1,47 +0,0 @@
-module mp_pe
-#(parameter IS_BSP=0)
-(
-	input  logic	  clk,
-	                  rst_n,
-	
-	input  logic      write,
-	input  logic[7:0] writedata,
-	output logic[7:0] readdata,
-
-	input logic       cpu_halted,
-	                  breakpoint,
-
-	output logic      halt,
-	                  step
-);
-
-	struct packed
-	{
-		logic step, halt, run;
-	} req;
-
-	struct packed
-	{
-		logic breakpoint, cpu_halted;
-	} status;
-
-	assign req = writedata[$bits(req) - 1:0];
-	assign readdata = {{(8 - $bits(status)){1'b0}}, status};
-
-	always @(posedge clk or negedge rst_n)
-		if (!rst_n) begin
-			halt <= IS_BSP ? 0 : 1; // Boot es single-core
-			step <= 0;
-			status <= {($bits(status)){1'b0}};
-		end else begin
-			status.breakpoint <= breakpoint;
-			status.cpu_halted <= cpu_halted;
-
-			//Se hace halt hasta el siguiente ciclo después de que se 
-			//solicita el breakpoint
-			step <= !breakpoint || (req.step && write);
-			halt <= (halt || breakpoint || (req.halt && write))
-			     && !((req.run || req.step) && write);
-		end
-
-endmodule