rtl/gfx: implement SP writeback

6 files changed, 98 insertions, 15 deletions

diff --git a/rtl/gfx/gfx_defs.sv b/rtl/gfx/gfx_defs.sv
index 260b17a..70664d1 100644
--- a/rtl/gfx/gfx_defs.sv
+++ b/rtl/gfx/gfx_defs.sv
@@ -257,4 +257,6 @@ typedef struct packed
 
 `define GFX_SP_COMBINER_FIFO_DEPTH 4 // TODO: optimizar esto
 
+`define GFX_SP_WB_STAGES 2
+
 `endif
diff --git a/rtl/gfx/gfx_sp.sv b/rtl/gfx/gfx_sp.sv
index ea3b126..7add2db 100644
--- a/rtl/gfx/gfx_sp.sv
+++ b/rtl/gfx/gfx_sp.sv
@@ -60,43 +60,59 @@ module gfx_sp
 		.*
 	);
 
+	logic shuffler_wb_valid;
+	wb_op shuffler_wb;
+
 	gfx_sp_shuffler shuffler
 	(
 		.a(),
 		.b(),
-		.wb(),
+		.wb(shuffler_wb),
 		.deco(),
 		.in_ready(),
 		.in_valid(0),
-		.wb_ready(1),
-		.wb_valid(),
+		.wb_ready(shuffler_wb_ready),
+		.wb_valid(shuffler_wb_valid),
 		.*
 	);
 
+	logic combiner_wb_valid;
+	wb_op combiner_wb;
+
 	gfx_sp_combiner combiner
 	(
 		.a(),
 		.b(),
-		.wb(),
+		.wb(combiner_wb),
 		.deco(),
 		.in_ready(),
 		.in_valid(0),
-		.wb_ready(1),
-		.wb_valid(),
+		.wb_ready(combiner_wb_ready),
+		.wb_valid(combiner_wb_valid),
 		.*
 	);
 
-	logic recv_ready;
+	logic recv_ready, stream_wb_valid;
+	wb_op stream_wb;
 
 	gfx_sp_stream stream
 	(
 		.a(),
-		.wb(),
+		.wb(stream_wb),
 		.deco(),
 		.in_ready(),
 		.in_valid(0),
-		.wb_ready(1),
-		.wb_valid(),
+		.wb_ready(stream_wb_ready),
+		.wb_valid(stream_wb_valid),
+		.*
+	);
+
+	mat4 wr_data;
+	logic combiner_wb_ready, shuffler_wb_ready, stream_wb_ready, wr;
+	vreg_num wr_reg;
+
+	gfx_sp_writeback writeback
+	(
 		.*
 	);
 
diff --git a/rtl/gfx/gfx_sp_combiner.sv b/rtl/gfx/gfx_sp_combiner.sv
index 8f16cd3..900af00 100644
--- a/rtl/gfx/gfx_sp_combiner.sv
+++ b/rtl/gfx/gfx_sp_combiner.sv
@@ -11,9 +11,9 @@ module gfx_sp_combiner
 	input  logic     in_valid,
 	output logic     in_ready,
 
-	output wb_op     wb,
 	input  logic     wb_ready,
-	output logic     wb_valid
+	output logic     wb_valid,
+	output wb_op     wb
 );
 
 	wb_op wb_out;
diff --git a/rtl/gfx/gfx_sp_shuffler.sv b/rtl/gfx/gfx_sp_shuffler.sv
index 8e1e461..b813d03 100644
--- a/rtl/gfx/gfx_sp_shuffler.sv
+++ b/rtl/gfx/gfx_sp_shuffler.sv
@@ -11,9 +11,9 @@ module gfx_sp_shuffler
 	input  logic     in_valid,
 	output logic     in_ready,
 
-	output wb_op     wb,
 	input  logic     wb_ready,
-	output logic     wb_valid
+	output logic     wb_valid,
+	output wb_op     wb
 );
 
 	mat4 select_out, swizzle_out;
diff --git a/rtl/gfx/gfx_sp_stream.sv b/rtl/gfx/gfx_sp_stream.sv
index fed8021..7901028 100644
--- a/rtl/gfx/gfx_sp_stream.sv
+++ b/rtl/gfx/gfx_sp_stream.sv
@@ -10,9 +10,9 @@ module gfx_sp_stream
 	input  logic     in_valid,
 	output logic     in_ready,
 
-	output wb_op     wb,
 	input  logic     wb_ready,
 	output logic     wb_valid,
+	output wb_op     wb,
 
 	input  lane_word recv_data,
 	input  lane_mask recv_mask,
diff --git a/rtl/gfx/gfx_sp_writeback.sv b/rtl/gfx/gfx_sp_writeback.sv
new file mode 100644
index 0000000..1195910
--- /dev/null
+++ b/rtl/gfx/gfx_sp_writeback.sv
@@ -0,0 +1,65 @@
+`include "gfx/gfx_defs.sv"
+
+module gfx_sp_writeback
+(
+	input  logic    clk,
+	                rst_n,
+
+	input  wb_op    stream_wb,
+	input  logic    stream_wb_valid,
+	output logic    stream_wb_ready,
+
+	input  wb_op    combiner_wb,
+	input  logic    combiner_wb_valid,
+	output logic    combiner_wb_ready,
+
+	input  wb_op    shuffler_wb,
+	input  logic    shuffler_wb_valid,
+	output logic    shuffler_wb_ready,
+
+	output logic    wr,
+	output vreg_num wr_reg,
+	output mat4     wr_data
+);
+
+	wb_op wb_in, wb_out;
+
+	assign wr_reg = wb_out.dst;
+	assign wr_data = wb_out.data;
+
+	gfx_pipeline_flow #(.STAGES(`GFX_SP_WB_STAGES)) flow
+	(
+		.stall(),
+		.in_ready(),
+		.in_valid(stream_wb_valid || combiner_wb_valid || shuffler_wb_valid),
+		.out_ready(1),
+		.out_valid(wr),
+		.*
+	);
+
+	gfx_pipes #(.WIDTH($bits(wb_out)), .DEPTH(`GFX_SP_WB_STAGES)) pipes
+	(
+		.in(wb_in),
+		.out(wb_out),
+		.stall(0),
+		.*
+	);
+
+	always_comb begin
+		stream_wb_ready = 0;
+		combiner_wb_ready = 0;
+		shuffler_wb_ready = 0;
+
+		if (stream_wb_valid) begin
+			wb_in = stream_wb;
+			stream_wb_ready = 1;
+		end else if (shuffler_wb_valid) begin
+			wb_in = shuffler_wb;
+			shuffler_wb_ready = 1;
+		end else begin
+			wb_in = combiner_wb;
+			combiner_wb_ready = 1;
+		end
+	end
+
+endmodule