rtl/gfx: reimplement multiplier as a much smaller mat-vec pipeline

1 files changed, 0 insertions, 26 deletions

diff --git a/rtl/gfx/pipelined_flow.sv b/rtl/gfx/pipelined_flow.sv
deleted file mode 100644
index 1e3c1ce..0000000
--- a/rtl/gfx/pipelined_flow.sv
+++ /dev/null
@@ -1,26 +0,0 @@
-module pipelined_flow
-#(parameter STAGES=0)
-(
-	input  logic clk,
-	             rst_n,
-
-	input  logic start,
-	output logic done
-);
-
-	logic valid[STAGES];
-
-	assign done = valid[STAGES - 1];
-
-	always_ff @(posedge clk or negedge rst_n)
-		valid[0] <= !rst_n ? 0 : start;
-
-	genvar i;
-	generate
-		for (i = 1; i < STAGES; ++i) begin: pipeline
-			always_ff @(posedge clk or negedge rst_n)
-				valid[i] <= !rst_n ? 0 : valid[i - 1];
-		end
-	endgenerate
-
-endmodule