diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-11-02 22:19:26 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-11-10 01:43:02 -0600 |
| commit | d5de20fade70a0d454e3aa0087313ca715ff8759 (patch) | |
| tree | 55751c829e989500972c56f05a7b0cb5e4e07621 /rtl/gfx/fp_mul.sv | |
| parent | 09fcdbe01553385658fe437dcb1777008c0ceb39 (diff) | |
rtl/gfx: rename modules
Diffstat (limited to 'rtl/gfx/fp_mul.sv')
| -rw-r--r-- | rtl/gfx/fp_mul.sv | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/rtl/gfx/fp_mul.sv b/rtl/gfx/fp_mul.sv deleted file mode 100644 index fda4de2..0000000 --- a/rtl/gfx/fp_mul.sv +++ /dev/null @@ -1,40 +0,0 @@ -`include "gfx/gfx_defs.sv" - -module fp_mul -( - input logic clk, - - input fp a, - b, - input logic stall, - - output fp q -); - -`ifndef VERILATOR - ip_fp_mul ip_mul - ( - .en(!stall), - .areset(0), - .* - ); -`else - fp a_pipeline[`FP_MUL_STAGES - 1], b_pipeline[`FP_MUL_STAGES - 1]; - - integer i; - - always_ff @(posedge clk) - if (!stall) begin - a_pipeline[0] <= a; - b_pipeline[0] <= b; - - for (i = 1; i < `FP_MUL_STAGES - 1; ++i) begin - a_pipeline[i] <= a_pipeline[i - 1]; - b_pipeline[i] <= b_pipeline[i - 1]; - end - - q <= $c("taller::fp_mul(", a_pipeline[`FP_MUL_STAGES - 2], ", ", b_pipeline[`FP_MUL_STAGES - 2], ")"); - end -`endif - -endmodule |