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authorAlejandro Soto <alejandro@34project.org>2024-02-28 16:44:15 -0600
committerAlejandro Soto <alejandro@34project.org>2024-03-03 20:42:36 -0600
commitcce507d21c86f20a83eec1b09fe3231399ffb10c (patch)
treecef497f3eb1767aeb9d8817adbbed467eac3b72d /rtl/dma_axi32/dma_axi32_reg_core0.v
parent872349eb3a3a508abee028e75da546692eb8e0e7 (diff)
rtl/dma_axi32: fix verilator warnings
Diffstat (limited to 'rtl/dma_axi32/dma_axi32_reg_core0.v')
-rw-r--r--rtl/dma_axi32/dma_axi32_reg_core0.v8
1 files changed, 6 insertions, 2 deletions
diff --git a/rtl/dma_axi32/dma_axi32_reg_core0.v b/rtl/dma_axi32/dma_axi32_reg_core0.v
index f42aa20..cacbe92 100644
--- a/rtl/dma_axi32/dma_axi32_reg_core0.v
+++ b/rtl/dma_axi32/dma_axi32_reg_core0.v
@@ -1,3 +1,5 @@
+// verilator lint_off WIDTHEXPAND
+// verilator lint_off WIDTHTRUNC
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
@@ -152,11 +154,11 @@ module dma_axi32_reg_core0(clk,reset,wr_joint,wr_clkdiv,wr_start,wr_prio,pwdata,
always @(posedge clk or posedge reset)
if (reset)
begin
- joint_mode <= #1 1'b0;
+ joint_mode <= 1'b0;
end
else if (wr_joint)
begin
- joint_mode <= #1 pwdata[0];
+ joint_mode <= pwdata[0];
end
@@ -184,3 +186,5 @@ endmodule
+// verilator lint_on WIDTHEXPAND
+// verilator lint_on WIDTHTRUNC