diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-10-23 19:11:51 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-23 19:11:51 -0600 |
| commit | 469e29b90ebc248a3b69aa82a36aabaa14d936f2 (patch) | |
| tree | 4842799d71f5425cfad5769ff24a67502be0ae71 /rtl/core | |
| parent | 40482e26534ac5d0deb9500d205d47ac9a99c3a5 (diff) | |
Fix ldm writeback
Diffstat (limited to 'rtl/core')
| -rw-r--r-- | rtl/core/control/control.sv | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index 95d3bb9..c2484ef 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -238,9 +238,10 @@ module core_control mem_offset <= alu_b; end + writeback <= mem_ready && !mem_write; if(mem_ready) begin + rd <= final_rd; wr_value <= mem_data_rd; - writeback <= !mem_write; end if(cycle != TRANSFER || mem_ready) begin @@ -249,8 +250,8 @@ module core_control saved_base <= q_alu; if(pop_valid) begin - rd <= popped; rb <= popped; + final_rd <= popped; end else rb <= final_rd; // Viene de dec_ldst.rd end |
