diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-07 17:20:38 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-07 17:25:11 -0600 |
| commit | cc7ed6bd05b8143ed4250caf97798c8bbfc6b748 (patch) | |
| tree | 4fef961873f1a52020ee2cb7c49b59c3fc842c10 /rtl/core/uarch.sv | |
| parent | 280cb5bb42f56d13ae2043b955a7bf286022b0b7 (diff) | |
Rework regfile in order to remove negedge trigger
Diffstat (limited to 'rtl/core/uarch.sv')
| -rw-r--r-- | rtl/core/uarch.sv | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv index 2b3c55a..d4654a7 100644 --- a/rtl/core/uarch.sv +++ b/rtl/core/uarch.sv @@ -22,7 +22,8 @@ typedef logic[29:0] ptr; * registers are 32 bits wide and are described in General-purpose registers on * page A2-6. */ -typedef logic[4:0] reg_index; +`define NUM_GPREGS 30 +typedef logic[$clog2(`NUM_GPREGS) - 1:0] reg_index; typedef logic[3:0] alu_op; |