From cc7ed6bd05b8143ed4250caf97798c8bbfc6b748 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 7 Nov 2022 17:20:38 -0600 Subject: Rework regfile in order to remove negedge trigger --- rtl/core/uarch.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'rtl/core/uarch.sv') diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv index 2b3c55a..d4654a7 100644 --- a/rtl/core/uarch.sv +++ b/rtl/core/uarch.sv @@ -22,7 +22,8 @@ typedef logic[29:0] ptr; * registers are 32 bits wide and are described in General-purpose registers on * page A2-6. */ -typedef logic[4:0] reg_index; +`define NUM_GPREGS 30 +typedef logic[$clog2(`NUM_GPREGS) - 1:0] reg_index; typedef logic[3:0] alu_op; -- cgit v1.2.3