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authorAlejandro Soto <alejandro@34project.org>2022-09-25 15:00:25 -0600
committerAlejandro Soto <alejandro@34project.org>2022-09-25 15:00:25 -0600
commit5dc62fde35731279e5ef4c7b334cb97d4f24f656 (patch)
treee2f73fccc7acd3eabfc51bc4871e396e1ed11a3d /rtl/core/uarch.sv
parent601835e33298015cf49f0ab33a7ef3d61b003ad9 (diff)
Implement register file
Diffstat (limited to 'rtl/core/uarch.sv')
-rw-r--r--rtl/core/uarch.sv13
1 files changed, 13 insertions, 0 deletions
diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv
index c5a449c..1ba039e 100644
--- a/rtl/core/uarch.sv
+++ b/rtl/core/uarch.sv
@@ -4,6 +4,19 @@
// Decodifica como andeq r0, r0, r0
`define NOP 32'd0
+typedef logic[31:0] word;
+typedef logic[29:0] ptr;
+
+/* Se necesitan 30 GPRs. De A2.3:
+ *
+ * The ARM processor has a total of 37 registers:
+ *
+ * Thirty-one general-purpose registers, including a program counter. These
+ * registers are 32 bits wide and are described in General-purpose registers on
+ * page A2-6.
+ */
+typedef logic[4:0] reg_index;
+
typedef enum logic[1:0]
{
ALU_ADD,