From 5dc62fde35731279e5ef4c7b334cb97d4f24f656 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 25 Sep 2022 15:00:25 -0600 Subject: Implement register file --- rtl/core/uarch.sv | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'rtl/core/uarch.sv') diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv index c5a449c..1ba039e 100644 --- a/rtl/core/uarch.sv +++ b/rtl/core/uarch.sv @@ -4,6 +4,19 @@ // Decodifica como andeq r0, r0, r0 `define NOP 32'd0 +typedef logic[31:0] word; +typedef logic[29:0] ptr; + +/* Se necesitan 30 GPRs. De A2.3: + * + * The ARM processor has a total of 37 registers: + * + * Thirty-one general-purpose registers, including a program counter. These + * registers are 32 bits wide and are described in General-purpose registers on + * page A2-6. + */ +typedef logic[4:0] reg_index; + typedef enum logic[1:0] { ALU_ADD, -- cgit v1.2.3