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| author | Alejandro Soto <alejandro@34project.org> | 2022-10-23 15:34:57 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-23 15:35:32 -0600 |
| commit | 40482e26534ac5d0deb9500d205d47ac9a99c3a5 (patch) | |
| tree | c646f6848bb18e7e06225121bb03fe508befd51a /rtl/core/shifter.sv | |
| parent | de5debd2c30e9aad633b93c5bfec0780298a61d6 (diff) | |
Fix zero-extended (lsr) vs sign-extended (asr) shifts
Diffstat (limited to 'rtl/core/shifter.sv')
| -rw-r--r-- | rtl/core/shifter.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/rtl/core/shifter.sv b/rtl/core/shifter.sv index 994e76c..2b5739d 100644 --- a/rtl/core/shifter.sv +++ b/rtl/core/shifter.sv @@ -20,7 +20,7 @@ module core_shifter assign sign_mask = {(W + 1){ctrl.sign_extend & base[W - 1]}}; assign {c_shl, q_shl} = {c_in, base} << shift; - assign {q_shr, c_shr} = {base, c_in} >> shift | ~(sign_mask >> shift); + assign {q_shr, c_shr} = {base, c_in} >> shift | (sign_mask & ~(sign_mask >> shift)); logic ror_cycle; logic[LOG - 1:0] ror_shift; |