diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-09-27 19:52:26 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-09-27 19:52:26 -0600 |
| commit | 5e2f6be247018699d71d32887010830ba45b8349 (patch) | |
| tree | 72a45e73de7e15ef0dcfdbc4eaee1f3cd8d286c3 /rtl/core/regs | |
| parent | ec7649eef16c7f9c3ca4b74a1cea95eb2f524b29 (diff) | |
Switch from operand forwarding to next insn stalls (improves Fmax)
Diffstat (limited to 'rtl/core/regs')
| -rw-r--r-- | rtl/core/regs/file.sv | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv index b2dd634..22f7ccf 100644 --- a/rtl/core/regs/file.sv +++ b/rtl/core/regs/file.sv @@ -13,19 +13,12 @@ module core_reg_file // Ver comentario en uarch.sv word file[30]; - word q, wr_value_hold; - logic overwrite_hold; - - assign rd_value = overwrite_hold ? wr_value_hold : q; always @(negedge clk) begin - if(wr_enable) begin + if(wr_enable) file[wr_index] <= wr_value; - wr_value_hold <= wr_value; - end - q <= file[rd_index]; - overwrite_hold <= wr_enable & (rd_index == wr_index); + rd_value <= file[rd_index]; end endmodule |
