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authorAlejandro Soto <alejandro@34project.org>2022-11-07 19:04:39 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-07 19:04:39 -0600
commitc67a1007045a9bf0282c26da74149723c6a2941d (patch)
tree587140176ca929cdadc58866d072b69fc5da91c9 /rtl/core/regs
parentcc7ed6bd05b8143ed4250caf97798c8bbfc6b748 (diff)
Fix long combinational path between regs and fetch
Diffstat (limited to 'rtl/core/regs')
-rw-r--r--rtl/core/regs/regs.sv13
1 files changed, 9 insertions, 4 deletions
diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv
index b25a122..9cf7033 100644
--- a/rtl/core/regs/regs.sv
+++ b/rtl/core/regs/regs.sv
@@ -14,6 +14,7 @@ module core_regs
output word rd_value_a,
rd_value_b,
+ wr_current,
output logic branch
);
@@ -23,11 +24,10 @@ module core_regs
* sincronizadas del archivo de registros.
*/
- word pc_word, wr_current;
+ word pc_word;
logic wr_pc, wr_enable_file;
reg_index wr_index;
- assign branch = wr_enable && wr_pc;
assign pc_word = {pc_visible, 2'b00};
assign wr_enable_file = wr_enable && !wr_pc;
@@ -53,11 +53,16 @@ module core_regs
.index(wr_index)
);
- always_ff @(posedge clk)
+ always_ff @(posedge clk) begin
if(wr_enable)
wr_current <= wr_value;
- initial
+ branch <= wr_enable && wr_pc;
+ end
+
+ initial begin
+ branch = 0;
wr_current = 0;
+ end
endmodule