From c67a1007045a9bf0282c26da74149723c6a2941d Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Mon, 7 Nov 2022 19:04:39 -0600
Subject: Fix long combinational path between regs and fetch

---
 rtl/core/regs/regs.sv | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

(limited to 'rtl/core/regs')

diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv
index b25a122..9cf7033 100644
--- a/rtl/core/regs/regs.sv
+++ b/rtl/core/regs/regs.sv
@@ -14,6 +14,7 @@ module core_regs
 
 	output word     rd_value_a,
 	                rd_value_b,
+	                wr_current,
 	output logic    branch
 );
 
@@ -23,11 +24,10 @@ module core_regs
 	 * sincronizadas del archivo de registros.
 	 */
 
-	word pc_word, wr_current;
+	word pc_word;
 	logic wr_pc, wr_enable_file;
 	reg_index wr_index;
 
-	assign branch = wr_enable && wr_pc;
 	assign pc_word = {pc_visible, 2'b00};
 	assign wr_enable_file = wr_enable && !wr_pc;
 
@@ -53,11 +53,16 @@ module core_regs
 		.index(wr_index)
 	);
 
-	always_ff @(posedge clk)
+	always_ff @(posedge clk) begin
 		if(wr_enable)
 			wr_current <= wr_value;
 
-	initial
+		branch <= wr_enable && wr_pc;
+	end
+
+	initial begin
+		branch = 0;
 		wr_current = 0;
+	end
 
 endmodule
-- 
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