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| author | Alejandro Soto <alejandro@34project.org> | 2022-10-03 12:16:01 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-03 12:16:01 -0600 |
| commit | 7e7c205367558b622fa56edaaa9c76491d57a4fa (patch) | |
| tree | 32a56225a04b94170f214def62e0f9076ed09c89 /rtl/core/regs | |
| parent | 63ec42cc245b2da9ab97cc4eef6bbd21e08cde07 (diff) | |
Fix pipeline hazards
Diffstat (limited to 'rtl/core/regs')
| -rw-r--r-- | rtl/core/regs/regs.sv | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv index 247c120..6ddf335 100644 --- a/rtl/core/regs/regs.sv +++ b/rtl/core/regs/regs.sv @@ -28,8 +28,8 @@ module core_regs word pc_word, file_rd_value_a, file_rd_value_b; assign pc_word = {pc_visible, 2'b00}; - assign rd_value_a = rd_pc_a ? pc_word : file_rd_value_a; - assign rd_value_b = rd_pc_b ? pc_word : file_rd_value_b; + assign rd_value_a = rd_pc_a ? pc_word : (wr_enable && rd_index_a == wr_index) ? wr_value : file_rd_value_a; + assign rd_value_b = rd_pc_b ? pc_word : (wr_enable && rd_index_a == wr_index) ? wr_value : file_rd_value_b; assign file_wr_enable = wr_enable & ~wr_pc; assign branch = wr_enable & wr_pc; |