From 7e7c205367558b622fa56edaaa9c76491d57a4fa Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 3 Oct 2022 12:16:01 -0600 Subject: Fix pipeline hazards --- rtl/core/regs/regs.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'rtl/core/regs') diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv index 247c120..6ddf335 100644 --- a/rtl/core/regs/regs.sv +++ b/rtl/core/regs/regs.sv @@ -28,8 +28,8 @@ module core_regs word pc_word, file_rd_value_a, file_rd_value_b; assign pc_word = {pc_visible, 2'b00}; - assign rd_value_a = rd_pc_a ? pc_word : file_rd_value_a; - assign rd_value_b = rd_pc_b ? pc_word : file_rd_value_b; + assign rd_value_a = rd_pc_a ? pc_word : (wr_enable && rd_index_a == wr_index) ? wr_value : file_rd_value_a; + assign rd_value_b = rd_pc_b ? pc_word : (wr_enable && rd_index_a == wr_index) ? wr_value : file_rd_value_b; assign file_wr_enable = wr_enable & ~wr_pc; assign branch = wr_enable & wr_pc; -- cgit v1.2.3