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authorAlejandro Soto <alejandro@34project.org>2022-09-25 19:22:43 -0600
committerAlejandro Soto <alejandro@34project.org>2022-09-25 19:22:43 -0600
commit3aa075cf009d9aa8c602389853cc3ea78cda8701 (patch)
treed14d298de29c7d0a6040192018200b2a88b2b93e /rtl/core/regs
parentf65e5611fde5e1c3e3a509cb2f3ffcafce5bbd33 (diff)
Fix Quartus issues
Diffstat (limited to 'rtl/core/regs')
-rw-r--r--rtl/core/regs/file.sv15
1 files changed, 11 insertions, 4 deletions
diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv
index 1b10682..e2bcc09 100644
--- a/rtl/core/regs/file.sv
+++ b/rtl/core/regs/file.sv
@@ -13,12 +13,19 @@ module core_reg_file
// Ver comentario en uarch.sv
word file[30];
+ word q, wr_value_hold;
+ logic overwrite_hold;
- always @(posedge clk)
- if(wr_enable)
+ assign rd_value = overwrite_hold ? wr_value_hold : q;
+
+ always @(posedge clk) begin
+ if(wr_enable) begin
file[rd_index] <= wr_value;
+ wr_value_hold <= wr_value;
+ end
- always @(posedge clk)
- rd_value <= wr_enable & (rd_index == wr_index) ? wr_value : file[rd_index];
+ q <= file[rd_index];
+ overwrite_hold <= wr_enable & (rd_index == wr_index);
+ end
endmodule