From 3aa075cf009d9aa8c602389853cc3ea78cda8701 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 25 Sep 2022 19:22:43 -0600 Subject: Fix Quartus issues --- rtl/core/regs/file.sv | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'rtl/core/regs') diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv index 1b10682..e2bcc09 100644 --- a/rtl/core/regs/file.sv +++ b/rtl/core/regs/file.sv @@ -13,12 +13,19 @@ module core_reg_file // Ver comentario en uarch.sv word file[30]; + word q, wr_value_hold; + logic overwrite_hold; - always @(posedge clk) - if(wr_enable) + assign rd_value = overwrite_hold ? wr_value_hold : q; + + always @(posedge clk) begin + if(wr_enable) begin file[rd_index] <= wr_value; + wr_value_hold <= wr_value; + end - always @(posedge clk) - rd_value <= wr_enable & (rd_index == wr_index) ? wr_value : file[rd_index]; + q <= file[rd_index]; + overwrite_hold <= wr_enable & (rd_index == wr_index); + end endmodule -- cgit v1.2.3