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| author | Alejandro Soto <alejandro@34project.org> | 2022-11-09 09:25:48 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-09 09:25:48 -0600 |
| commit | 5d798386c3b1c1dc45a2fbc382c9367ccc27c524 (patch) | |
| tree | a04fff74505af30c8044f80f523fd887331e6234 /rtl/core/mul.sv | |
| parent | 65590be80332d132d7037bfe3bb19e5d6e5bcd7b (diff) | |
Implement reset
Diffstat (limited to 'rtl/core/mul.sv')
| -rw-r--r-- | rtl/core/mul.sv | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/rtl/core/mul.sv b/rtl/core/mul.sv index a801851..e189e45 100644 --- a/rtl/core/mul.sv +++ b/rtl/core/mul.sv @@ -4,6 +4,8 @@ module core_mul ( input logic clk, // clock, ya que es una máquina de estados + rst_n, + input word a, // primer sumando b, // segundo sumando c_hi, // parte más significativa de c @@ -31,7 +33,7 @@ module core_mul dsp_mul ip ( .clock0(clk), - .aclr0(1), //TODO + .aclr0(rst_n), .ena0(start || !ready), .dataa_0(a), .datab_0(b), @@ -49,13 +51,12 @@ module core_mul else c = {{$bits(word){sig && c_lo[$bits(c_lo) - 1]}}, c_lo}; - always_ff @(posedge clk) - if(wait_state > {$bits(wait_state){1'b0}}) + always_ff @(posedge clk or negedge rst_n) + if(!rst_n) + wait_state <= 0; + else if(wait_state > {$bits(wait_state){1'b0}}) wait_state <= wait_state - 1; else if(start) wait_state <= 1; - initial - wait_state = 0; - endmodule |