diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-12-11 14:48:08 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-16 16:27:20 -0600 |
| commit | ff71bcd0c5425c168f111b8f4a92d0a90a6c9c31 (patch) | |
| tree | 41190239b9220db09d8849afb6d6f6dbbc03f59b /rtl/core/mmu/pagewalk.sv | |
| parent | 6fee344b754464b1fd17f7c0429e6597e51dc74d (diff) | |
Implement data aborts
Diffstat (limited to 'rtl/core/mmu/pagewalk.sv')
| -rw-r--r-- | rtl/core/mmu/pagewalk.sv | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/rtl/core/mmu/pagewalk.sv b/rtl/core/mmu/pagewalk.sv index b16ce26..be4aa8b 100644 --- a/rtl/core/mmu/pagewalk.sv +++ b/rtl/core/mmu/pagewalk.sv @@ -25,7 +25,9 @@ module core_mmu_pagewalk bus_write, output logic core_ready, - output word core_data_rd + core_fault, + output word core_data_rd, + output ptr core_fault_addr ); enum int unsigned @@ -71,7 +73,9 @@ module core_mmu_pagewalk bus_data_wr <= 0; core_ready <= 0; + core_fault <= 0; core_data_rd <= 0; + core_fault_addr <= 0; end else begin if(bus_start) bus_start <= 0; @@ -79,6 +83,9 @@ module core_mmu_pagewalk if(core_ready) core_ready <= 0; + if(core_fault) + core_fault <= 0; + unique case(state) IDLE: if(core_start) begin @@ -157,8 +164,12 @@ module core_mmu_pagewalk core_data_rd <= bus_data_rd; end - //TODO - FAULT: ; + FAULT: begin + state <= IDLE; + core_fault <= 1; + core_ready <= 1; + core_fault_addr <= target; + end endcase end |