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authorAlejandro Soto <alejandro@34project.org>2022-12-07 19:18:04 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-07 19:51:41 -0600
commitc39552375661e495b344e8386649ade92a4d45b2 (patch)
tree45623ce35964e43ae7d8804c1ef1c6dedb3ba7a1 /rtl/core/fetch/prefetch.sv
parentb1761b8eac5777c09723bbc8cd31cc05d8ec35ae (diff)
Implement single-stepping
Diffstat (limited to 'rtl/core/fetch/prefetch.sv')
-rw-r--r--rtl/core/fetch/prefetch.sv6
1 files changed, 4 insertions, 2 deletions
diff --git a/rtl/core/fetch/prefetch.sv b/rtl/core/fetch/prefetch.sv
index 2f0a866..1b5a4c5 100644
--- a/rtl/core/fetch/prefetch.sv
+++ b/rtl/core/fetch/prefetch.sv
@@ -13,15 +13,17 @@ module core_prefetch
output word insn,
output ptr insn_pc,
- next_pc,
- output logic fetch
+ output logic fetch,
+ nop
);
localparam SIZE = (1 << ORDER) - 1;
+ ptr next_pc;
logic[31:0] prefetch[SIZE];
logic[ORDER - 1:0] valid;
+ assign nop = flush ? 1 : ~|valid;
assign insn = flush ? `NOP : prefetch[0];
assign next_pc = ~stall & |valid ? insn_pc + 1 : insn_pc;
assign fetch = !stall || ~&valid;